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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/01/08 13:46:59 UTC
[incubator-nuttx] branch master updated (e7f9c7a -> d7ec3e3)
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from e7f9c7a typos: fix typos in Kconfig files
new 4ca38c6 esp32: Add PWM support using the LEDC peripheral
new d7ec3e3 esp32-devkitc: Add support to PWM
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/esp32/Kconfig | 92 +-
arch/xtensa/src/esp32/Make.defs | 4 +
.../src/esp32/esp32_ledc.c} | 262 +-
.../src/esp32/esp32_ledc.h} | 12 +-
arch/xtensa/src/esp32/hardware/esp32_ledc.h | 4192 ++++++++++++++++++++
.../esp32-devkitc/configs/{nsh => pwm}/defconfig | 9 +
boards/xtensa/esp32/esp32-devkitc/src/Make.defs | 4 +
.../xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h | 12 +
.../xtensa/esp32/esp32-devkitc/src/esp32_bringup.c | 8 +
.../esp32/esp32-devkitc/src/esp32_ledc.c} | 38 +-
10 files changed, 4497 insertions(+), 136 deletions(-)
copy arch/{risc-v/src/esp32c3/esp32c3_ledc.c => xtensa/src/esp32/esp32_ledc.c} (74%)
copy arch/{risc-v/src/esp32c3/esp32c3_ledc.h => xtensa/src/esp32/esp32_ledc.h} (87%)
create mode 100644 arch/xtensa/src/esp32/hardware/esp32_ledc.h
copy boards/xtensa/esp32/esp32-devkitc/configs/{nsh => pwm}/defconfig (82%)
copy boards/{risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c => xtensa/esp32/esp32-devkitc/src/esp32_ledc.c} (81%)
[incubator-nuttx] 01/02: esp32: Add PWM support using the LEDC peripheral
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4ca38c6c504efdf03c005bbdb45b2b4ddcdc8630
Author: Alan C. Assis <ac...@gmail.com>
AuthorDate: Thu Jan 6 14:12:55 2022 -0300
esp32: Add PWM support using the LEDC peripheral
Co-authored-by: Petro Karashchenko <pe...@gmail.com>
---
arch/xtensa/src/esp32/Kconfig | 92 +-
arch/xtensa/src/esp32/Make.defs | 4 +
arch/xtensa/src/esp32/esp32_ledc.c | 812 ++++++
arch/xtensa/src/esp32/esp32_ledc.h | 52 +
arch/xtensa/src/esp32/hardware/esp32_ledc.h | 4192 +++++++++++++++++++++++++++
5 files changed, 5149 insertions(+), 3 deletions(-)
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
index f2092d3..67d2894 100644
--- a/arch/xtensa/src/esp32/Kconfig
+++ b/arch/xtensa/src/esp32/Kconfig
@@ -324,11 +324,12 @@ config ESP32_I2S1
No yet implemented
config ESP32_LEDC
- bool "LED PWM (LEDC)"
+ bool "LEDC (PWM)"
default n
- depends on EXPERIMENTAL
+ select PWM
+ select ARCH_HAVE_PWM_MULTICHAN
---help---
- No yet implemented
+ Enable support to PWM on ESP32 using LEDC peripheral.
config ESP32_PCNT
bool "Pulse Count Module (PCNT)"
@@ -1282,6 +1283,91 @@ config ESP32_FREERUN
endmenu # Timer/counter Configuration
endif # ESP32_TIMER
+menu "LEDC configuration"
+ depends on ESP32_LEDC
+
+menuconfig ESP32_LEDC_TIM0
+ bool "Timer 0"
+ default n
+
+if ESP32_LEDC_TIM0
+
+config ESP32_LEDC_TIM0_CHANNELS
+ int "Number of Timer 0 channels"
+ default 2
+
+endif # ESP32_LEDC_TIM0
+
+menuconfig ESP32_LEDC_TIM1
+ bool "Timer 1"
+ default n
+
+if ESP32_LEDC_TIM1
+
+config ESP32_LEDC_TIM1_CHANNELS
+ int "Number of Timer 1 channels"
+ default 2
+
+endif # ESP32_LEDC_TIM1
+
+menuconfig ESP32_LEDC_TIM2
+ bool "Timer 2"
+ default n
+
+if ESP32_LEDC_TIM2
+
+config ESP32_LEDC_TIM2_CHANNELS
+ int "Number of Timer 2 channels"
+ default 2
+
+endif # ESP32_LEDC_TIM2
+
+menuconfig ESP32_LEDC_TIM3
+ bool "Timer 3"
+ default n
+
+if ESP32_LEDC_TIM3
+
+config ESP32_LEDC_TIM3_CHANNELS
+ int "Number of Timer 3 channels"
+ default 2
+
+endif # ESP32_LEDC_TIM2
+
+config ESP32_LEDC_CHANNEL0_PIN
+ int "Channel 0 pin"
+ default 2
+
+config ESP32_LEDC_CHANNEL1_PIN
+ int "Channel 1 pin"
+ default 3
+
+config ESP32_LEDC_CHANNEL2_PIN
+ int "Channel 2 pin"
+ default 4
+
+config ESP32_LEDC_CHANNEL3_PIN
+ int "Channel 3 pin"
+ default 5
+
+config ESP32_LEDC_CHANNEL4_PIN
+ int "Channel 4 pin"
+ default 6
+
+config ESP32_LEDC_CHANNEL5_PIN
+ int "Channel 5 pin"
+ default 7
+
+config ESP32_LEDC_CHANNEL6_PIN
+ int "Channel 6 pin"
+ default 8
+
+config ESP32_LEDC_CHANNEL7_PIN
+ int "Channel 7 pin"
+ default 9
+
+endmenu # LEDC configuration
+
config ESP32_HAVE_OTA_PARTITION
bool
default n
diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs
index 4538e6d..21855af 100644
--- a/arch/xtensa/src/esp32/Make.defs
+++ b/arch/xtensa/src/esp32/Make.defs
@@ -95,6 +95,10 @@ ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y)
CHIP_CSRCS += esp32_imm.c
endif
+ifeq ($(CONFIG_ESP32_LEDC),y)
+CHIP_CSRCS += esp32_ledc.c
+endif
+
ifeq ($(CONFIG_ESP32_I2C),y)
CHIP_CSRCS += esp32_i2c.c
endif
diff --git a/arch/xtensa/src/esp32/esp32_ledc.c b/arch/xtensa/src/esp32/esp32_ledc.c
new file mode 100644
index 0000000..66210fc
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_ledc.c
@@ -0,0 +1,812 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_ledc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <debug.h>
+#include <errno.h>
+
+#include "esp32_clockconfig.h"
+#include "esp32_gpio.h"
+#include "esp32_ledc.h"
+
+#include "xtensa.h"
+#include "hardware/esp32_ledc.h"
+#include "hardware/esp32_dport.h"
+#include "hardware/esp32_gpio_sigmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* LEDC total timers */
+
+#define LEDC_TIMERS (4)
+
+/* LEDC total channels */
+
+#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_CHANNELS (8)
+#else
+# define LEDC_CHANNELS (4)
+#endif
+
+/* LEDC timer0 channels and offset */
+
+#ifdef CONFIG_ESP32_LEDC_TIM0
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM0_CHANS CONFIG_ESP32_LEDC_TIM0_CHANNELS
+# else
+# define LEDC_TIM0_CHANS (1)
+# endif
+# define LEDC_TIM0_CHANS_OFF (0)
+#endif
+
+/* LEDC timer1 channels and offset */
+
+#ifdef CONFIG_ESP32_LEDC_TIM1
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM1_CHANS CONFIG_ESP32_LEDC_TIM1_CHANNELS
+# else
+# define LEDC_TIM1_CHANS (1)
+# endif
+# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS)
+#endif
+
+/* LEDC timer2 channels and offset */
+
+#ifdef CONFIG_ESP32_LEDC_TIM2
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM2_CHANS CONFIG_ESP32_LEDC_TIM2_CHANNELS
+# else
+# define LEDC_TIM2_CHANS (1)
+# endif
+
+# define LEDC_TIM2_CHANS_OFF (LEDC_TIM1_CHANS_OFF + LEDC_TIM1_CHANS)
+#endif
+
+/* LEDC timer3 channels and offset */
+
+#ifdef CONFIG_ESP32_LEDC_TIM3
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM3_CHANS CONFIG_ESP32_LEDC_TIM3_CHANNELS
+# else
+# define LEDC_TIM3_CHANS (1)
+# endif
+
+# define LEDC_TIM3_CHANS_OFF (LEDC_TIM2_CHANS_OFF + LEDC_TIM2_CHANS)
+#endif
+
+/* LEDC clock resource */
+
+#define LEDC_CLK_RES (1) /* APB clock */
+
+/* LEDC timer max reload */
+
+#define LEDC_RELOAD_MAX (1048576) /* 2^20 */
+
+/* LEDC timer max clock divider parameter */
+
+#define LEDC_CLKDIV_MAX (1024) /* 2^10 */
+
+/* LEDC timer registers mapping */
+
+#define LEDC_TIMER_REG(r, n) ((r) + (n) * (LEDC_LSTIMER1_CONF_REG - \
+ LEDC_LSTIMER0_CONF_REG))
+
+/* LEDC timer channel registers mapping */
+
+#define setbits(bs, a) modifyreg32(a, 0, bs)
+#define resetbits(bs, a) modifyreg32(a, bs, 0)
+
+#define LEDC_CHAN_REG(r, n) ((r) + (n) * (LEDC_LSCH1_CONF0_REG - \
+ LEDC_LSCH0_CONF0_REG))
+
+#define SET_TIMER_BITS(t, r, b) setbits(b, LEDC_TIMER_REG(r, (t)->num));
+#define SET_TIMER_REG(t, r, v) putreg32(v, LEDC_TIMER_REG(r, (t)->num));
+
+#define SET_CHAN_BITS(c, r, b) setbits(b, LEDC_CHAN_REG(r, (c)->num));
+#define SET_CHAN_REG(c, r, v) putreg32(v, LEDC_CHAN_REG(r, (c)->num));
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* LEDC timer channel configuration */
+
+struct esp32_ledc_chan_s
+{
+ const uint8_t num; /* Timer channel ID */
+ const uint8_t pin; /* Timer channel GPIO pin number */
+
+ uint16_t duty; /* Timer channel current duty */
+};
+
+/* This structure represents the state of one LEDC timer */
+
+struct esp32_ledc_s
+{
+ const struct pwm_ops_s *ops; /* PWM operations */
+
+ const uint8_t num; /* Timer ID */
+
+ const uint8_t channels; /* Timer channels number */
+ struct esp32_ledc_chan_s *chans; /* Timer channels pointer */
+
+ uint32_t frequency; /* Timer current frequency */
+ uint32_t reload; /* Timer current reload */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int pwm_setup(struct pwm_lowerhalf_s *dev);
+static int pwm_shutdown(struct pwm_lowerhalf_s *dev);
+static int pwm_start(struct pwm_lowerhalf_s *dev,
+ const struct pwm_info_s *info);
+static int pwm_stop(struct pwm_lowerhalf_s *dev);
+static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd,
+ unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* LEDC PWM operations */
+
+static const struct pwm_ops_s g_pwmops =
+{
+ .setup = pwm_setup,
+ .shutdown = pwm_shutdown,
+ .start = pwm_start,
+ .stop = pwm_stop,
+ .ioctl = pwm_ioctl
+};
+
+/* LEDC channels table */
+
+static struct esp32_ledc_chan_s g_ledc_chans[LEDC_CHANNELS] =
+{
+ {
+ .num = 0,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL0_PIN
+ },
+
+ {
+ .num = 1,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL1_PIN
+ },
+
+ {
+ .num = 2,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL2_PIN
+ },
+
+ {
+ .num = 3,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL3_PIN
+ },
+
+#if LEDC_CHANNELS > 4
+ {
+ .num = 4,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL4_PIN
+ },
+
+ {
+ .num = 5,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL5_PIN
+ },
+
+ {
+ .num = 6,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL6_PIN
+ },
+
+ {
+ .num = 7,
+ .pin = CONFIG_ESP32_LEDC_CHANNEL7_PIN
+ }
+#endif
+};
+
+/* LEDC timer0 private data */
+
+#ifdef CONFIG_ESP32_LEDC_TIM0
+static struct esp32_ledc_s g_pwm0dev =
+{
+ .ops = &g_pwmops,
+ .num = 0,
+ .channels = LEDC_TIM0_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM0_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32_LEDC_TIM0 */
+
+/* LEDC timer1 private data */
+
+#ifdef CONFIG_ESP32_LEDC_TIM1
+static struct esp32_ledc_s g_pwm1dev =
+{
+ .ops = &g_pwmops,
+ .num = 1,
+ .channels = LEDC_TIM1_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM1_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32_LEDC_TIM1 */
+
+/* LEDC timer2 private data */
+
+#ifdef CONFIG_ESP32_LEDC_TIM2
+static struct esp32_ledc_s g_pwm2dev =
+{
+ .ops = &g_pwmops,
+ .num = 2,
+ .channels = LEDC_TIM2_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM2_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32_LEDC_TIM2 */
+
+/* LEDC timer3 private data */
+
+#ifdef CONFIG_ESP32_LEDC_TIM3
+static struct esp32_ledc_s g_pwm3dev =
+{
+ .ops = &g_pwmops,
+ .num = 3,
+ .channels = LEDC_TIM3_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM3_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32_LEDC_TIM3 */
+
+/* Clock reference count */
+
+static uint32_t g_clk_ref;
+
+/****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ledc_enable_clk
+ *
+ * Description:
+ * Enable LEDC clock.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void ledc_enable_clk(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ if (g_clk_ref == 0)
+ {
+ setbits(DPORT_LEDC_CLK_EN, DPORT_PERIP_CLK_EN_REG);
+ resetbits(DPORT_LEDC_RST, DPORT_PERIP_RST_EN_REG);
+
+ putreg32(LEDC_CLK_RES, LEDC_CONF_REG);
+
+ pwminfo("Enable ledc clock\n");
+ }
+
+ g_clk_ref++;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: ledc_disable_clk
+ *
+ * Description:
+ * Disable LEDC clock.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void ledc_disable_clk(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ g_clk_ref--;
+
+ if (g_clk_ref == 0)
+ {
+ pwminfo("Disable ledc clock\n");
+
+ setbits(DPORT_LEDC_RST, DPORT_PERIP_RST_EN_REG);
+ resetbits(DPORT_LEDC_CLK_EN, DPORT_PERIP_CLK_EN_REG);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: setup_timer
+ *
+ * Description:
+ * Setup LEDC timer frequency and reload.
+ *
+ * Input Parameters:
+ * priv - A reference to the LEDC timer state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void setup_timer(struct esp32_ledc_s *priv)
+{
+ irqstate_t flags;
+ uint32_t regval;
+ uint32_t reload;
+ uint32_t prescaler;
+ uint32_t shift = 1;
+ uint64_t pwmclk = esp_clk_apb_freq();
+
+ /* Reset timer */
+
+ SET_TIMER_BITS(priv, LEDC_LSTIMER0_CONF_REG, LEDC_LSTIMER0_RST);
+
+ /* Calculate optimal values for the timer prescaler and for the timer
+ * modulo register. If' frequency' is the desired frequency, then
+ *
+ * tpmclk = pwmclk / presc
+ * frequency = tpmclk / reload
+ *
+ * ==>
+ *
+ * reload = pwmclk / presc / frequency
+ *
+ * In ESP32, there are 2 clock resources for PWM:
+ *
+ * 1. APB clock (80 MHz)
+ * 2. RTC clock (8 MHz)
+ *
+ * We mostly use APB clock generally.
+ *
+ * There are many solutions to this, but the best solution will be the one
+ * that has the largest reload value and the smallest prescaler value.
+ * That is the solution that should give us the most accuracy in the timer
+ * control. Subject to:
+ *
+ * 2 <= presc <= 2^20(1,048,576)
+ * 1 <= clkdiv <= 2^10
+ *
+ * clkdiv has 8-bit decimal precision, so
+ * clkdiv = pwmclk * 256 / 1048576 / frequency would be optimal.
+ *
+ * Example:
+ *
+ * pwmclk = 80 MHz
+ * frequency = 100 Hz
+ *
+ * presc = 80,000,000 * 256 / 16,384 / 100
+ * = 12,500
+ * timclk = 80,000,000 / (12,500 / 256)
+ * = 1,638,400
+ * counter = 1,638,400 / 100
+ * = 16,384
+ * = 2^14
+ * shift = 14
+ */
+
+ reload = (pwmclk * 256 / priv->frequency + LEDC_CLKDIV_MAX) /
+ LEDC_CLKDIV_MAX;
+ if (reload == 0)
+ {
+ reload = 1;
+ }
+ else if (reload > LEDC_RELOAD_MAX)
+ {
+ reload = LEDC_RELOAD_MAX;
+ }
+
+ for (int c = 2; c <= LEDC_RELOAD_MAX; c *= 2)
+ {
+ if (c * 2 > reload)
+ {
+ reload = c;
+ break;
+ }
+
+ shift++;
+ }
+
+ prescaler = pwmclk * 256 / reload / priv->frequency;
+
+ pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%"
+ PRIu32 " prescaler=%0.4f\n",
+ priv->num, (float)pwmclk / reload / ((float)prescaler / 256),
+ reload, shift, (float)prescaler / 256);
+
+ /* Store reload for channel duty */
+
+ priv->reload = reload;
+
+ flags = enter_critical_section();
+
+ /* Set timer clock divide and reload */
+
+ regval = (shift << LEDC_LSTIMER0_DUTY_RES_S) |
+ (prescaler << LEDC_DIV_NUM_LSTIMER0_S);
+ SET_TIMER_REG(priv, LEDC_LSTIMER0_CONF_REG, regval);
+
+ /* Setup to timer to use APB clock (80MHz) */
+
+ SET_TIMER_BITS(priv, LEDC_LSTIMER0_CONF_REG, LEDC_TICK_SEL_LSTIMER0);
+
+ /* Update clock divide and reload to hardware */
+
+ SET_TIMER_BITS(priv, LEDC_LSTIMER0_CONF_REG, LEDC_LSTIMER0_PARA_UP);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: setup_channel
+ *
+ * Description:
+ * Setup LEDC timer channel duty.
+ *
+ * Input Parameters:
+ * priv - A reference to the LEDC timer state structure
+ * cn - Timer channel number
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void setup_channel(struct esp32_ledc_s *priv, int cn)
+{
+ irqstate_t flags;
+ uint32_t regval;
+ struct esp32_ledc_chan_s *chan = &priv->chans[cn];
+
+ /* Duty cycle:
+ *
+ * duty cycle = duty / 65536 * reload (fractional value)
+ */
+
+ regval = b16toi(chan->duty * priv->reload + b16HALF);
+
+ pwminfo("channel=%" PRIu8 " duty=%" PRIu16 "(%0.4f) regval=%" PRIu32
+ " reload=%" PRIu32 "\n",
+ chan->num, chan->duty, (float)chan->duty / UINT16_MAX,
+ regval, priv->reload);
+
+ flags = enter_critical_section();
+
+ /* Reset config 0 & 1 registers */
+
+ SET_CHAN_REG(chan, LEDC_LSCH0_CONF0_REG, 0);
+ SET_CHAN_REG(chan, LEDC_LSCH0_CONF1_REG, 0);
+
+ /* Set pulse phase 0 */
+
+ SET_CHAN_REG(chan, LEDC_LSCH0_HPOINT_REG, 0);
+
+ /* Duty register uses bits [18:4] */
+
+ SET_CHAN_REG(chan, LEDC_LSCH0_DUTY_REG, regval << 4);
+
+ /* Start GPIO output */
+
+ SET_CHAN_BITS(chan, LEDC_LSCH0_CONF0_REG, LEDC_SIG_OUT_EN_LSCH0);
+
+ /* Start Duty counter */
+
+ SET_CHAN_BITS(chan, LEDC_LSCH0_CONF1_REG, LEDC_DUTY_START_LSCH0);
+
+ /* Update duty and phase to hardware */
+
+ SET_CHAN_BITS(chan, LEDC_LSCH0_CONF0_REG, LEDC_PARA_UP_LSCH0);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ * This method is called when the driver is opened. The lower half driver
+ * should configure and initialize the device so that it is ready for use.
+ * It should not, however, output pulses until the start method is called.
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_setup(struct pwm_lowerhalf_s *dev)
+{
+ struct esp32_ledc_s *priv = (struct esp32_ledc_s *)dev;
+
+ pwminfo("PWM timer%u\n", priv->num);
+
+ ledc_enable_clk();
+
+ /* Setup channel GPIO pins */
+
+ for (int i = 0; i < priv->channels; i++)
+ {
+ pwminfo("channel%d --> pin%d\n", priv->chans[i].num,
+ priv->chans[i].pin);
+
+ esp32_configgpio(priv->chans[i].pin, OUTPUT | PULLUP);
+ esp32_gpio_matrix_out(priv->chans[i].pin,
+ LEDC_LS_SIG_OUT0_IDX + priv->chans[i].num,
+ 0, 0);
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ * This method is called when the driver is closed. The lower half driver
+ * stop pulsed output, free any resources, disable the timer hardware, and
+ * put the system into the lowest possible power usage state
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
+{
+ struct esp32_ledc_s *priv = (struct esp32_ledc_s *)dev;
+#ifdef CONFIG_PWM_NCHANNELS
+ int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS);
+#else
+ int channels = 1;
+#endif
+
+ /* Stop timer */
+
+ pwm_stop(dev);
+
+ /* Clear timer and channel configuration */
+
+ priv->frequency = 0;
+ priv->reload = 0;
+ for (int i = 0; i < channels; i++)
+ {
+ priv->chans[i].duty = 0;
+ }
+
+ ledc_disable_clk();
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ * (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_start(struct pwm_lowerhalf_s *dev,
+ const struct pwm_info_s *info)
+{
+ struct esp32_ledc_s *priv = (struct esp32_ledc_s *)dev;
+#ifdef CONFIG_PWM_NCHANNELS
+ int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS);
+#else
+ int channels = 1;
+#endif
+
+ pwminfo("PWM timer%d\n", priv->num);
+
+ /* Update timer with given PWM timer frequency */
+
+ if (priv->frequency != info->frequency)
+ {
+ priv->frequency = info->frequency;
+ setup_timer(priv);
+ }
+
+ /* Update timer with given PWM channel duty */
+
+ for (int i = 0; i < channels; i++)
+ {
+#ifdef CONFIG_PWM_NCHANNELS
+ if (priv->chans[i].duty != info->channels[i].duty)
+#else
+ if (priv->chans[i].duty != info[i].duty)
+#endif
+ {
+#ifdef CONFIG_PWM_NCHANNELS
+ priv->chans[i].duty = info->channels[i].duty;
+#else
+ priv->chans[i].duty = info[i].duty;
+#endif
+ setup_channel(priv, i);
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ * Stop the pulsed output and reset the timer resources.
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_stop(struct pwm_lowerhalf_s *dev)
+{
+ irqstate_t flags;
+ struct esp32_ledc_s *priv = (struct esp32_ledc_s *)dev;
+
+ pwminfo("PWM timer%d\n", priv->num);
+
+ flags = enter_critical_section();
+
+ /* Stop timer */
+
+ SET_TIMER_BITS(priv, LEDC_LSTIMER0_CONF_REG, LEDC_LSTIMER0_PAUSE);
+
+ /* Reset timer */
+
+ SET_TIMER_BITS(priv, LEDC_LSTIMER0_CONF_REG, LEDC_LSTIMER0_RST);
+
+ leave_critical_section(flags);
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ * Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * cmd - The ioctl command
+ * arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd,
+ unsigned long arg)
+{
+#ifdef CONFIG_DEBUG_PWM_INFO
+ struct esp32_ledc_s *priv = (struct esp32_ledc_s *)dev;
+
+ pwminfo("PWM timer%d\n", priv->num);
+#endif
+
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_ledc_init
+ *
+ * Description:
+ * Initialize one LEDC timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the ESP32 LEDC lower half PWM driver is
+ * returned. NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+struct pwm_lowerhalf_s *esp32_ledc_init(int timer)
+{
+ struct esp32_ledc_s *lower = NULL;
+
+ pwminfo("TIM%u\n", timer);
+
+ switch (timer)
+ {
+#ifdef CONFIG_ESP32_LEDC_TIM0
+ case 0:
+ lower = &g_pwm0dev;
+ break;
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM1
+ case 1:
+ lower = &g_pwm1dev;
+ break;
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM2
+ case 2:
+ lower = &g_pwm2dev;
+ break;
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM3
+ case 3:
+ lower = &g_pwm3dev;
+ break;
+#endif
+
+ default:
+ pwmerr("ERROR: No such timer configured %d\n", timer);
+ lower = NULL;
+ break;
+ }
+
+ return (struct pwm_lowerhalf_s *)lower;
+}
diff --git a/arch/xtensa/src/esp32/esp32_ledc.h b/arch/xtensa/src/esp32/esp32_ledc.h
new file mode 100644
index 0000000..3c6e2c6
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_ledc.h
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_ledc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_LEDC_H
+#define __ARCH_XTENSA_SRC_ESP32_ESP32_LEDC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/timers/pwm.h>
+
+/****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_ledc_init
+ *
+ * Description:
+ * Initialize one LEDC timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is
+ * returned. NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+struct pwm_lowerhalf_s *esp32_ledc_init(int timer);
+
+#endif /* __ARCH_RISCV_SRC_ESP32_ESP32_LEDC_H */
diff --git a/arch/xtensa/src/esp32/hardware/esp32_ledc.h b/arch/xtensa/src/esp32/hardware/esp32_ledc.h
new file mode 100644
index 0000000..6031d7e
--- /dev/null
+++ b/arch/xtensa/src/esp32/hardware/esp32_ledc.h
@@ -0,0 +1,4192 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/hardware/esp32_ledc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_LEDC_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_LEDC_H
+
+#define LEDC_HSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
+
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+
+/* Description: This bit is clock gating control signal. when software
+ * config LED_PWM internal registers it controls the register clock.
+ */
+
+#define LEDC_CLK_EN (BIT(31))
+#define LEDC_CLK_EN_M (BIT(31))
+#define LEDC_CLK_EN_V 0x1
+#define LEDC_CLK_EN_S 31
+
+/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value when high
+ * speed channel0 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH0 (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_V 0x1
+#define LEDC_IDLE_LV_HSCH0_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit for high
+ * speed channel0
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH0_S 2
+
+/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits are used
+ * to select one of them for high speed channel0.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH0 0x00000003
+#define LEDC_TIMER_SEL_HSCH0_M ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))
+#define LEDC_TIMER_SEL_HSCH0_V 0x3
+#define LEDC_TIMER_SEL_HSCH0_S 0
+
+#define LEDC_HSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)
+
+/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * htimerx(x=[0 3]) selected by high speed channel0 has reached
+ * reg_hpoint_hsch0[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH0 0x000FFFFF
+#define LEDC_HPOINT_HSCH0_M ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))
+#define LEDC_HPOINT_HSCH0_V 0xFFFFF
+#define LEDC_HPOINT_HSCH0_S 0
+
+#define LEDC_HSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)
+
+/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel0
+ * has reached reg_lpoint_hsch0 the output signal changes to low.
+ * reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1)
+ * reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part and
+ * determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH0 0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S 0
+
+#define LEDC_HSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)
+
+/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and
+ * reg_duty_scale_hsch0 has been configured. These registers won't
+ * take effect until set reg_duty_start_hsch0. this bit is automatically
+ * cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH0 (BIT(31))
+#define LEDC_DUTY_START_HSCH0_M (BIT(31))
+#define LEDC_DUTY_START_HSCH0_V 0x1
+#define LEDC_DUTY_START_HSCH0_S 31
+
+/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty of output
+ * signal or decrease the duty of output signal for high speed channel0.
+ */
+
+#define LEDC_DUTY_INC_HSCH0 (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_V 0x1
+#define LEDC_DUTY_INC_HSCH0_S 30
+
+/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel0.
+ */
+
+#define LEDC_DUTY_NUM_HSCH0 0x000003FF
+#define LEDC_DUTY_NUM_HSCH0_M ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))
+#define LEDC_DUTY_NUM_HSCH0_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH0_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease the duty
+ * every reg_duty_cycle_hsch0 cycles for high speed channel0.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH0 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH0_M ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))
+#define LEDC_DUTY_CYCLE_HSCH0_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH0_S 10
+
+/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel0.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH0 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))
+#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH0_S 0
+
+#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)
+
+/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty of the
+ * output signal for high speed channel0.
+ */
+
+#define LEDC_DUTY_HSCH0 0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S 0
+
+#define LEDC_HSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)
+
+/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel1 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH1 (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_V 0x1
+#define LEDC_IDLE_LV_HSCH1_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit for high
+ * speed channel1
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH1_S 2
+
+/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel1.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH1 0x00000003
+#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))
+#define LEDC_TIMER_SEL_HSCH1_V 0x3
+#define LEDC_TIMER_SEL_HSCH1_S 0
+
+#define LEDC_HSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)
+
+/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when htimerx(x=[0 3])
+ * selected by high speed channel1 has reached reg_hpoint_hsch1[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH1 0x000FFFFF
+#define LEDC_HPOINT_HSCH1_M ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))
+#define LEDC_HPOINT_HSCH1_V 0xFFFFF
+#define LEDC_HPOINT_HSCH1_S 0
+
+#define LEDC_HSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)
+
+/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel1 has reached
+ * reg_lpoint_hsch1 the output signal changes to low.
+ * reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1)
+ * reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH1 0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S 0
+
+#define LEDC_HSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)
+
+/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit is
+ * automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH1 (BIT(31))
+#define LEDC_DUTY_START_HSCH1_M (BIT(31))
+#define LEDC_DUTY_START_HSCH1_V 0x1
+#define LEDC_DUTY_START_HSCH1_S 31
+
+/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty of output
+ * signal or decrease the duty of output signal for high speed channel1.
+ */
+
+#define LEDC_DUTY_INC_HSCH1 (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_V 0x1
+#define LEDC_DUTY_INC_HSCH1_S 30
+
+/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel1.
+ */
+
+#define LEDC_DUTY_NUM_HSCH1 0x000003FF
+#define LEDC_DUTY_NUM_HSCH1_M ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))
+#define LEDC_DUTY_NUM_HSCH1_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH1_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch1 cycles for high speed channel1.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH1 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH1_M ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))
+#define LEDC_DUTY_CYCLE_HSCH1_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH1_S 10
+
+/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel1.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH1 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))
+#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH1_S 0
+
+#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)
+
+/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty of the output
+ * signal for high speed channel1.
+ */
+
+#define LEDC_DUTY_HSCH1 0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S 0
+
+#define LEDC_HSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)
+
+/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel2 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH2 (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_V 0x1
+#define LEDC_IDLE_LV_HSCH2_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit for high
+ * speed channel2
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH2_S 2
+
+/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel2.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH2 0x00000003
+#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))
+#define LEDC_TIMER_SEL_HSCH2_V 0x3
+#define LEDC_TIMER_SEL_HSCH2_S 0
+
+#define LEDC_HSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)
+
+/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * htimerx(x=[0 3]) selected by high speed channel2 has reached
+ * reg_hpoint_hsch2[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH2 0x000FFFFF
+#define LEDC_HPOINT_HSCH2_M ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))
+#define LEDC_HPOINT_HSCH2_V 0xFFFFF
+#define LEDC_HPOINT_HSCH2_S 0
+
+#define LEDC_HSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)
+
+/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel2 has reached
+ * reg_lpoint_hsch2 the output signal changes to low.
+ * reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1)
+ * reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part and
+ * determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH2 0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S 0
+
+#define LEDC_HSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)
+
+/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2
+ * and reg_duty_scale_hsch2 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch2.
+ * This bit is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH2 (BIT(31))
+#define LEDC_DUTY_START_HSCH2_M (BIT(31))
+#define LEDC_DUTY_START_HSCH2_V 0x1
+#define LEDC_DUTY_START_HSCH2_S 31
+
+/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for high speed channel2.
+ */
+
+#define LEDC_DUTY_INC_HSCH2 (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_V 0x1
+#define LEDC_DUTY_INC_HSCH2_S 30
+
+/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num
+ * of increased or decreased times for high speed channel2.
+ */
+
+#define LEDC_DUTY_NUM_HSCH2 0x000003FF
+#define LEDC_DUTY_NUM_HSCH2_M ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))
+#define LEDC_DUTY_NUM_HSCH2_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH2_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch2 cycles for high speed channel2.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH2 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH2_M ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))
+#define LEDC_DUTY_CYCLE_HSCH2_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH2_S 10
+
+/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel2.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH2 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))
+#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH2_S 0
+
+#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)
+
+/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for high speed channel2.
+ */
+
+#define LEDC_DUTY_HSCH2 0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S 0
+
+#define LEDC_HSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)
+
+/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel3 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH3 (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_V 0x1
+#define LEDC_IDLE_LV_HSCH3_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for high speed channel3
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH3_S 2
+
+/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel3.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH3 0x00000003
+#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))
+#define LEDC_TIMER_SEL_HSCH3_V 0x3
+#define LEDC_TIMER_SEL_HSCH3_S 0
+
+#define LEDC_HSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)
+
+/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when htimerx(x=[0 3])
+ * selected by high speed channel3 has reached reg_hpoint_hsch3[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH3 0x000FFFFF
+#define LEDC_HPOINT_HSCH3_M ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))
+#define LEDC_HPOINT_HSCH3_V 0xFFFFF
+#define LEDC_HPOINT_HSCH3_S 0
+
+#define LEDC_HSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)
+
+/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel3 has reached
+ * reg_lpoint_hsch3 the output signal changes to low.
+ * reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1)
+ * reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH3 0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S 0
+
+#define LEDC_HSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)
+
+/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3
+ * and reg_duty_scale_hsch3 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch3. This bit is
+ * automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH3 (BIT(31))
+#define LEDC_DUTY_START_HSCH3_M (BIT(31))
+#define LEDC_DUTY_START_HSCH3_V 0x1
+#define LEDC_DUTY_START_HSCH3_S 31
+
+/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for high speed channel3.
+ */
+
+#define LEDC_DUTY_INC_HSCH3 (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_V 0x1
+#define LEDC_DUTY_INC_HSCH3_S 30
+
+/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel3.
+ */
+
+#define LEDC_DUTY_NUM_HSCH3 0x000003FF
+#define LEDC_DUTY_NUM_HSCH3_M ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))
+#define LEDC_DUTY_NUM_HSCH3_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH3_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch3 cycles for high speed channel3.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH3 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH3_M ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))
+#define LEDC_DUTY_CYCLE_HSCH3_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH3_S 10
+
+/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel3.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH3 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))
+#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH3_S 0
+
+#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)
+
+/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty of the output
+ * signal for high speed channel3.
+ */
+
+#define LEDC_DUTY_HSCH3 0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S 0
+
+#define LEDC_HSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)
+
+/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel4 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH4 (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_V 0x1
+#define LEDC_IDLE_LV_HSCH4_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for high speed channel4
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH4_S 2
+
+/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel4.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH4 0x00000003
+#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))
+#define LEDC_TIMER_SEL_HSCH4_V 0x3
+#define LEDC_TIMER_SEL_HSCH4_S 0
+
+#define LEDC_HSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)
+
+/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * htimerx(x=[0 3]) selected by high speed channel4 has reached
+ * reg_hpoint_hsch4[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH4 0x000FFFFF
+#define LEDC_HPOINT_HSCH4_M ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))
+#define LEDC_HPOINT_HSCH4_V 0xFFFFF
+#define LEDC_HPOINT_HSCH4_S 0
+
+#define LEDC_HSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)
+
+/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel4 has reached
+ * reg_lpoint_hsch4 the output signal changes to low.
+ * reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1)
+ * reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH4 0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S 0
+
+#define LEDC_HSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)
+
+/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH4 (BIT(31))
+#define LEDC_DUTY_START_HSCH4_M (BIT(31))
+#define LEDC_DUTY_START_HSCH4_V 0x1
+#define LEDC_DUTY_START_HSCH4_S 31
+
+/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty of output
+ * signal or decrease the duty of output signal for high speed channel4.
+ */
+
+#define LEDC_DUTY_INC_HSCH4 (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_V 0x1
+#define LEDC_DUTY_INC_HSCH4_S 30
+
+/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel1.
+ */
+
+#define LEDC_DUTY_NUM_HSCH4 0x000003FF
+#define LEDC_DUTY_NUM_HSCH4_M ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))
+#define LEDC_DUTY_NUM_HSCH4_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH4_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch4 cycles for high speed channel4.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH4 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH4_M ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))
+#define LEDC_DUTY_CYCLE_HSCH4_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH4_S 10
+
+/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel4.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH4 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))
+#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH4_S 0
+
+#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)
+
+/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for high speed channel4.
+ */
+
+#define LEDC_DUTY_HSCH4 0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S 0
+
+#define LEDC_HSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)
+
+/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel5 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH5 (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_V 0x1
+#define LEDC_IDLE_LV_HSCH5_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for high speed channel5.
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH5_S 2
+
+/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel5.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH5 0x00000003
+#define LEDC_TIMER_SEL_HSCH5_M ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))
+#define LEDC_TIMER_SEL_HSCH5_V 0x3
+#define LEDC_TIMER_SEL_HSCH5_S 0
+
+#define LEDC_HSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)
+
+/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high
+ * when htimerx(x=[0 3]) selected by high speed channel5 has reached
+ * reg_hpoint_hsch5[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH5 0x000FFFFF
+#define LEDC_HPOINT_HSCH5_M ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))
+#define LEDC_HPOINT_HSCH5_V 0xFFFFF
+#define LEDC_HPOINT_HSCH5_S 0
+
+#define LEDC_HSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)
+
+/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel5 has reached
+ * reg_lpoint_hsch5 the output signal changes to low.
+ * reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1)
+ * reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH5 0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S 0
+
+#define LEDC_HSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)
+
+/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5
+ * and reg_duty_scale_hsch5 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch5. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH5 (BIT(31))
+#define LEDC_DUTY_START_HSCH5_M (BIT(31))
+#define LEDC_DUTY_START_HSCH5_V 0x1
+#define LEDC_DUTY_START_HSCH5_S 31
+
+/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for high speed channel5.
+ */
+
+#define LEDC_DUTY_INC_HSCH5 (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_V 0x1
+#define LEDC_DUTY_INC_HSCH5_S 30
+
+/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel5.
+ */
+
+#define LEDC_DUTY_NUM_HSCH5 0x000003FF
+#define LEDC_DUTY_NUM_HSCH5_M ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))
+#define LEDC_DUTY_NUM_HSCH5_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH5_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch5 cycles for high speed channel5.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH5 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH5_M ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))
+#define LEDC_DUTY_CYCLE_HSCH5_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH5_S 10
+
+/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel5.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH5 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))
+#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH5_S 0
+
+#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)
+
+/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for high speed channel5.
+ */
+
+#define LEDC_DUTY_HSCH5 0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S 0
+
+#define LEDC_HSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)
+
+/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel6 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH6 (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_V 0x1
+#define LEDC_IDLE_LV_HSCH6_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for high speed channel6
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH6_S 2
+
+/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel6.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH6 0x00000003
+#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))
+#define LEDC_TIMER_SEL_HSCH6_V 0x3
+#define LEDC_TIMER_SEL_HSCH6_S 0
+
+#define LEDC_HSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)
+
+/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high
+ * when htimerx(x=[0 3]) selected by high speed channel6 has reached
+ * reg_hpoint_hsch6[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH6 0x000FFFFF
+#define LEDC_HPOINT_HSCH6_M ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))
+#define LEDC_HPOINT_HSCH6_V 0xFFFFF
+#define LEDC_HPOINT_HSCH6_S 0
+
+#define LEDC_HSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)
+
+/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel6 has reached
+ * reg_lpoint_hsch6 the output signal changes to low.
+ * reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1)
+ * reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH6 0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S 0
+
+#define LEDC_HSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)
+
+/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH6 (BIT(31))
+#define LEDC_DUTY_START_HSCH6_M (BIT(31))
+#define LEDC_DUTY_START_HSCH6_V 0x1
+#define LEDC_DUTY_START_HSCH6_S 31
+
+/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for high speed channel6.
+ */
+
+#define LEDC_DUTY_INC_HSCH6 (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_V 0x1
+#define LEDC_DUTY_INC_HSCH6_S 30
+
+/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel6.
+ */
+
+#define LEDC_DUTY_NUM_HSCH6 0x000003FF
+#define LEDC_DUTY_NUM_HSCH6_M ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))
+#define LEDC_DUTY_NUM_HSCH6_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH6_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch6 cycles for high speed channel6.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH6 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH6_M ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))
+#define LEDC_DUTY_CYCLE_HSCH6_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH6_S 10
+
+/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel6.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH6 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))
+#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH6_S 0
+
+#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)
+
+/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for high speed channel6.
+ */
+
+#define LEDC_DUTY_HSCH6 0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S 0
+
+#define LEDC_HSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)
+
+/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when high speed channel7 is off.
+ */
+
+#define LEDC_IDLE_LV_HSCH7 (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_M (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_V 0x1
+#define LEDC_IDLE_LV_HSCH7_S 3
+
+/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for high speed channel7.
+ */
+
+#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_V 0x1
+#define LEDC_SIG_OUT_EN_HSCH7_S 2
+
+/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four high speed timers the two bits
+ * are used to select one of them for high speed channel7.
+ * 2'b00: seletc hstimer0.
+ * 2'b01: select hstimer1.
+ * 2'b10: select hstimer2.
+ * 2'b11: select hstimer3.
+ */
+
+#define LEDC_TIMER_SEL_HSCH7 0x00000003
+#define LEDC_TIMER_SEL_HSCH7_M ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))
+#define LEDC_TIMER_SEL_HSCH7_V 0x3
+#define LEDC_TIMER_SEL_HSCH7_S 0
+
+#define LEDC_HSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)
+
+/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high
+ * when htimerx(x=[0 3]) selected by high speed channel7
+ * has reached reg_hpoint_hsch7[19:0]
+ */
+
+#define LEDC_HPOINT_HSCH7 0x000FFFFF
+#define LEDC_HPOINT_HSCH7_M ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))
+#define LEDC_HPOINT_HSCH7_V 0xFFFFF
+#define LEDC_HPOINT_HSCH7_S 0
+
+#define LEDC_HSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)
+
+/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When hstimerx(x=[0 3]) choosed by high speed channel7 has reached
+ * reg_lpoint_hsch7 the output signal changes to low.
+ * reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1)
+ * reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_HSCH7 0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S 0
+
+#define LEDC_HSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)
+
+/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_HSCH7 (BIT(31))
+#define LEDC_DUTY_START_HSCH7_M (BIT(31))
+#define LEDC_DUTY_START_HSCH7_V 0x1
+#define LEDC_DUTY_START_HSCH7_S 31
+
+/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for high speed channel6.
+ */
+
+#define LEDC_DUTY_INC_HSCH7 (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_M (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_V 0x1
+#define LEDC_DUTY_INC_HSCH7_S 30
+
+/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for high speed channel6.
+ */
+
+#define LEDC_DUTY_NUM_HSCH7 0x000003FF
+#define LEDC_DUTY_NUM_HSCH7_M ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))
+#define LEDC_DUTY_NUM_HSCH7_V 0x3FF
+#define LEDC_DUTY_NUM_HSCH7_S 20
+
+/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_hsch7 cycles for high speed channel7.
+ */
+
+#define LEDC_DUTY_CYCLE_HSCH7 0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH7_M ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))
+#define LEDC_DUTY_CYCLE_HSCH7_V 0x3FF
+#define LEDC_DUTY_CYCLE_HSCH7_S 10
+
+/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for high speed channel7.
+ */
+
+#define LEDC_DUTY_SCALE_HSCH7 0x000003FF
+#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))
+#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF
+#define LEDC_DUTY_SCALE_HSCH7_S 0
+
+#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)
+
+/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty of the output
+ * signal for high speed channel7.
+ */
+
+#define LEDC_DUTY_HSCH7 0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S 0
+
+#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x00A0)
+
+/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH0_HPOINT
+ * and LEDC_LSCH0_DUTY for low speed channel0.
+ */
+
+#define LEDC_PARA_UP_LSCH0 (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V 0x1
+#define LEDC_PARA_UP_LSCH0_S 4
+
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel0 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH0 (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V 0x1
+#define LEDC_IDLE_LV_LSCH0_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel0.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S 2
+
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel0.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH0 0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V 0x3
+#define LEDC_TIMER_SEL_LSCH0_S 0
+
+#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x00A4)
+
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel0 has reached
+ * reg_hpoint_lsch0[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH0 0x000FFFFF
+#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V 0xFFFFF
+#define LEDC_HPOINT_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x00A8)
+
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel0 has reached
+ * reg_lpoint_lsch0 the output signal changes to low.
+ * reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1)
+ * reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH0 0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x00AC)
+
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH0 (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V 0x1
+#define LEDC_DUTY_START_LSCH0_S 31
+
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel6.
+ */
+
+#define LEDC_DUTY_INC_LSCH0 (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V 0x1
+#define LEDC_DUTY_INC_LSCH0_S 30
+
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel6.
+ */
+
+#define LEDC_DUTY_NUM_LSCH0 0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase
+ * or decrease the duty every reg_duty_cycle_lsch0 cycles
+ * for low speed channel0.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S 10
+
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel0.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH0 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0)
+
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel0.
+ */
+
+#define LEDC_DUTY_LSCH0 0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x00B4)
+
+/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH1_HPOINT
+ * and LEDC_LSCH1_DUTY for low speed channel1.
+ */
+
+#define LEDC_PARA_UP_LSCH1 (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V 0x1
+#define LEDC_PARA_UP_LSCH1_S 4
+
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel1 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH1 (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V 0x1
+#define LEDC_IDLE_LV_LSCH1_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel1.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S 2
+
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel1.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH1 0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V 0x3
+#define LEDC_TIMER_SEL_LSCH1_S 0
+
+#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x00B8)
+
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel1 has reached
+ * reg_hpoint_lsch1[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH1 0x000FFFFF
+#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V 0xFFFFF
+#define LEDC_HPOINT_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x00BC)
+
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel1 has reached
+ * reg_lpoint_lsch1 the output signal changes to low.
+ * reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1)
+ * reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH1 0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x00C0)
+
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1
+ * and reg_duty_scale_hsch1 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch1. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH1 (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V 0x1
+#define LEDC_DUTY_START_LSCH1_S 31
+
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel1.
+ */
+
+#define LEDC_DUTY_INC_LSCH1 (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V 0x1
+#define LEDC_DUTY_INC_LSCH1_S 30
+
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel1.
+ */
+
+#define LEDC_DUTY_NUM_LSCH1 0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease the duty
+ * every reg_duty_cycle_lsch1 cycles for low speed channel1.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S 10
+
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease step
+ * scale for low speed channel1.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH1 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4)
+
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel1.
+ */
+
+#define LEDC_DUTY_LSCH1 0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x00C8)
+
+/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH2_HPOINT
+ * and LEDC_LSCH2_DUTY for low speed channel2.
+ */
+
+#define LEDC_PARA_UP_LSCH2 (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V 0x1
+#define LEDC_PARA_UP_LSCH2_S 4
+
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value when low
+ * speed channel2 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH2 (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V 0x1
+#define LEDC_IDLE_LV_LSCH2_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel2.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S 2
+
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel2.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH2 0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V 0x3
+#define LEDC_TIMER_SEL_LSCH2_S 0
+
+#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x00CC)
+
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel2 has reached
+ * reg_hpoint_lsch2[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH2 0x000FFFFF
+#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V 0xFFFFF
+#define LEDC_HPOINT_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x00D0)
+
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel2 has reached
+ * reg_lpoint_lsch2 the output signal changes to low.
+ * reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1)
+ * reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH2 0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x00D4)
+
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2
+ * and reg_duty_scale_hsch2 has been configured. These register
+ * won't take effect until set reg_duty_start_hsch2. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH2 (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V 0x1
+#define LEDC_DUTY_START_LSCH2_S 31
+
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel2.
+ */
+
+#define LEDC_DUTY_INC_LSCH2 (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V 0x1
+#define LEDC_DUTY_INC_LSCH2_S 30
+
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel2.
+ */
+
+#define LEDC_DUTY_NUM_LSCH2 0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_lsch2 cycles for low speed channel2.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S 10
+
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel2.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH2 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8)
+
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel2.
+ */
+
+#define LEDC_DUTY_LSCH2 0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x00DC)
+
+/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH3_HPOINT
+ * and LEDC_LSCH3_DUTY for low speed channel3.
+ */
+
+#define LEDC_PARA_UP_LSCH3 (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V 0x1
+#define LEDC_PARA_UP_LSCH3_S 4
+
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel3 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH3 (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V 0x1
+#define LEDC_IDLE_LV_LSCH3_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel3.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S 2
+
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel3.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH3 0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V 0x3
+#define LEDC_TIMER_SEL_LSCH3_S 0
+
+#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x00E0)
+
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel3 has reached
+ * reg_hpoint_lsch3[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH3 0x000FFFFF
+#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V 0xFFFFF
+#define LEDC_HPOINT_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x00E4)
+
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel3 has reached
+ * reg_lpoint_lsch3 the output signal changes to low.
+ * reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1)
+ * reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH3 0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x00E8)
+
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3
+ * and reg_duty_scale_hsch3 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch3. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH3 (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V 0x1
+#define LEDC_DUTY_START_LSCH3_S 31
+
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel3.
+ */
+
+#define LEDC_DUTY_INC_LSCH3 (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V 0x1
+#define LEDC_DUTY_INC_LSCH3_S 30
+
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel3.
+ */
+
+#define LEDC_DUTY_NUM_LSCH3 0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_lsch3 cycles for low speed channel3.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S 10
+
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel3.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH3 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC)
+
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel3.
+ */
+
+#define LEDC_DUTY_LSCH3 0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x00F0)
+
+/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH4_HPOINT
+ * and LEDC_LSCH4_DUTY for low speed channel4.
+ */
+
+#define LEDC_PARA_UP_LSCH4 (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V 0x1
+#define LEDC_PARA_UP_LSCH4_S 4
+
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel4 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH4 (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V 0x1
+#define LEDC_IDLE_LV_LSCH4_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel4.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S 2
+
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel4.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH4 0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V 0x3
+#define LEDC_TIMER_SEL_LSCH4_S 0
+
+#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x00F4)
+
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel4 has reached
+ * reg_hpoint_lsch4[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH4 0x000FFFFF
+#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V 0xFFFFF
+#define LEDC_HPOINT_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x00F8)
+
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel4 has reached
+ * reg_lpoint_lsch4 the output signal changes to low.
+ * reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1)
+ * reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH4 0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x00FC)
+
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4
+ * and reg_duty_scale_hsch4 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch4. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH4 (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V 0x1
+#define LEDC_DUTY_START_LSCH4_S 31
+
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel4.
+ */
+
+#define LEDC_DUTY_INC_LSCH4 (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V 0x1
+#define LEDC_DUTY_INC_LSCH4_S 30
+
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel4.
+ */
+
+#define LEDC_DUTY_NUM_LSCH4 0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_lsch4 cycles for low speed channel4.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S 10
+
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel4.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH4 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100)
+
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel4.
+ */
+
+#define LEDC_DUTY_LSCH4 0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0104)
+
+/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH5_HPOINT
+ * and LEDC_LSCH5_DUTY for low speed channel5.
+ */
+
+#define LEDC_PARA_UP_LSCH5 (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V 0x1
+#define LEDC_PARA_UP_LSCH5_S 4
+
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel5 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH5 (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V 0x1
+#define LEDC_IDLE_LV_LSCH5_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel5.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S 2
+
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel5.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH5 0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V 0x3
+#define LEDC_TIMER_SEL_LSCH5_S 0
+
+#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0108)
+
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel5 has reached
+ * reg_hpoint_lsch5[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH5 0x000FFFFF
+#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V 0xFFFFF
+#define LEDC_HPOINT_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x010C)
+
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel5 has reached
+ * reg_lpoint_lsch5 the output signal changes to low.
+ * reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1)
+ * reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH5 0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0110)
+
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4
+ * and reg_duty_scale_hsch4 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch4. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH5 (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V 0x1
+#define LEDC_DUTY_START_LSCH5_S 31
+
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel5.
+ */
+
+#define LEDC_DUTY_INC_LSCH5 (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V 0x1
+#define LEDC_DUTY_INC_LSCH5_S 30
+
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel5.
+ */
+
+#define LEDC_DUTY_NUM_LSCH5 0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease the duty
+ * every reg_duty_cycle_lsch5 cycles for low speed channel4.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S 10
+
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel5.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH5 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114)
+
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel5.
+ */
+
+#define LEDC_DUTY_LSCH5 0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0118)
+
+/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH6_HPOINT
+ * and LEDC_LSCH6_DUTY for low speed channel6.
+ */
+
+#define LEDC_PARA_UP_LSCH6 (BIT(4))
+#define LEDC_PARA_UP_LSCH6_M (BIT(4))
+#define LEDC_PARA_UP_LSCH6_V 0x1
+#define LEDC_PARA_UP_LSCH6_S 4
+
+/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output value
+ * when low speed channel6 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH6 (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_V 0x1
+#define LEDC_IDLE_LV_LSCH6_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel6.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH6_S 2
+
+/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel6.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH6 0x00000003
+#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))
+#define LEDC_TIMER_SEL_LSCH6_V 0x3
+#define LEDC_TIMER_SEL_LSCH6_S 0
+
+#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x011C)
+
+/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel6 has reached
+ * reg_hpoint_lsch6[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH6 0x000FFFFF
+#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))
+#define LEDC_HPOINT_LSCH6_V 0xFFFFF
+#define LEDC_HPOINT_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0120)
+
+/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel6 has reached
+ * reg_lpoint_lsch6 the output signal changes to low.
+ * reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1)
+ * reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH6 0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0124)
+
+/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch6 reg_duty_cycle_hsch6
+ * and reg_duty_scale_hsch6 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch6. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH6 (BIT(31))
+#define LEDC_DUTY_START_LSCH6_M (BIT(31))
+#define LEDC_DUTY_START_LSCH6_V 0x1
+#define LEDC_DUTY_START_LSCH6_S 31
+
+/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel6.
+ */
+
+#define LEDC_DUTY_INC_LSCH6 (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_V 0x1
+#define LEDC_DUTY_INC_LSCH6_S 30
+
+/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel6.
+ */
+
+#define LEDC_DUTY_NUM_LSCH6 0x000003FF
+#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))
+#define LEDC_DUTY_NUM_LSCH6_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH6_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_lsch6 cycles for low speed channel6.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))
+#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH6_S 10
+
+/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel6.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH6 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))
+#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128)
+
+/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel6.
+ */
+
+#define LEDC_DUTY_LSCH6 0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x012C)
+
+/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: This bit is used to update register LEDC_LSCH7_HPOINT
+ * and LEDC_LSCH7_DUTY for low speed channel7.
+ */
+
+#define LEDC_PARA_UP_LSCH7 (BIT(4))
+#define LEDC_PARA_UP_LSCH7_M (BIT(4))
+#define LEDC_PARA_UP_LSCH7_V 0x1
+#define LEDC_PARA_UP_LSCH7_S 4
+
+/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: This bit is used to control the output
+ * value when low speed channel7 is off.
+ */
+
+#define LEDC_IDLE_LV_LSCH7 (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_V 0x1
+#define LEDC_IDLE_LV_LSCH7_S 3
+
+/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: This is the output enable control bit
+ * for low speed channel7.
+ */
+
+#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH7_S 2
+
+/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+
+/* Description: There are four low speed timers the two bits
+ * are used to select one of them for low speed channel7.
+ * 2'b00: seletc lstimer0.
+ * 2'b01: select lstimer1.
+ * 2'b10: select lstimer2.
+ * 2'b11: select lstimer3.
+ */
+
+#define LEDC_TIMER_SEL_LSCH7 0x00000003
+#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))
+#define LEDC_TIMER_SEL_LSCH7_V 0x3
+#define LEDC_TIMER_SEL_LSCH7_S 0
+
+#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0130)
+
+/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+
+/* Description: The output value changes to high when
+ * lstimerx(x=[0 3]) selected by low speed channel7 has reached
+ * reg_hpoint_lsch7[19:0]
+ */
+
+#define LEDC_HPOINT_LSCH7 0x000FFFFF
+#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))
+#define LEDC_HPOINT_LSCH7_V 0xFFFFF
+#define LEDC_HPOINT_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0134)
+
+/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: The register is used to control output duty.
+ * When lstimerx(x=[0 3]) choosed by low speed channel7 has reached
+ * reg_lpoint_lsch7 the output signal changes to low.
+ * reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1)
+ * reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] + 1) (2)
+ * The least four bits in this register represent the decimal part
+ * and determines when to choose (1) or (2)
+ */
+
+#define LEDC_DUTY_LSCH7 0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0138)
+
+/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+
+/* Description: When reg_duty_num_hsch4 reg_duty_cycle_hsch4
+ * and reg_duty_scale_hsch4 has been configured. These registers
+ * won't take effect until set reg_duty_start_hsch4. This bit
+ * is automatically cleared by hardware.
+ */
+
+#define LEDC_DUTY_START_LSCH7 (BIT(31))
+#define LEDC_DUTY_START_LSCH7_M (BIT(31))
+#define LEDC_DUTY_START_LSCH7_V 0x1
+#define LEDC_DUTY_START_LSCH7_S 31
+
+/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+
+/* Description: This register is used to increase the duty
+ * of output signal or decrease the duty of output signal
+ * for low speed channel4.
+ */
+
+#define LEDC_DUTY_INC_LSCH7 (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_V 0x1
+#define LEDC_DUTY_INC_LSCH7_S 30
+
+/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+
+/* Description: This register is used to control the num of increased
+ * or decreased times for low speed channel4.
+ */
+
+#define LEDC_DUTY_NUM_LSCH7 0x000003FF
+#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))
+#define LEDC_DUTY_NUM_LSCH7_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH7_S 20
+
+/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+
+/* Description: This register is used to increase or decrease
+ * the duty every reg_duty_cycle_lsch7 cycles for low speed channel7.
+ */
+
+#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))
+#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH7_S 10
+
+/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+
+/* Description: This register controls the increase or decrease
+ * step scale for low speed channel7.
+ */
+
+#define LEDC_DUTY_SCALE_LSCH7 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))
+#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C)
+
+/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+
+/* Description: This register represents the current duty
+ * of the output signal for low speed channel7.
+ */
+
+#define LEDC_DUTY_LSCH7 0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_HSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0140)
+
+/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose apb_clk or ref_tick
+ * for high speed timer0.
+ * 1'b1:apb_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_HSTIMER0 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_V 0x1
+#define LEDC_TICK_SEL_HSTIMER0_S 25
+
+/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset high speed timer0
+ * the counter will be 0 after reset.
+ */
+
+#define LEDC_HSTIMER0_RST (BIT(24))
+#define LEDC_HSTIMER0_RST_M (BIT(24))
+#define LEDC_HSTIMER0_RST_V 0x1
+#define LEDC_HSTIMER0_RST_S 24
+
+/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in high speed timer0 */
+
+#define LEDC_HSTIMER0_PAUSE (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_V 0x1
+#define LEDC_HSTIMER0_PAUSE_S 23
+
+/* LEDC_DIV_NUM_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter for divider
+ * in high speed timer0 the least significant eight bits represent the
+ * decimal part.
+ */
+
+#define LEDC_DIV_NUM_HSTIMER0 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER0_M ((LEDC_DIV_NUM_HSTIMER0_V)<<(LEDC_DIV_NUM_HSTIMER0_S))
+#define LEDC_DIV_NUM_HSTIMER0_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER0_S 5
+
+/* LEDC_HSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in high speed timer0. the counter range is [0 2**reg_hstimer0_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_HSTIMER0_DUTY_RES 0x0000001F
+#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
+#define LEDC_HSTIMER0_DUTY_RES_V 0x1F
+#define LEDC_HSTIMER0_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_HSTIMER0_LIM LEDC_HSTIMER0_DUTY_RES
+#define LEDC_HSTIMER0_LIM_M LEDC_HSTIMER0_DUTY_RES_M
+#define LEDC_HSTIMER0_LIM_V LEDC_HSTIMER0_DUTY_RES_V
+#define LEDC_HSTIMER0_LIM_S LEDC_HSTIMER0_DUTY_RES_S
+
+#define LEDC_HSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0144)
+
+/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in high speed timer0
+ */
+
+#define LEDC_HSTIMER0_CNT 0x000FFFFF
+#define LEDC_HSTIMER0_CNT_M ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))
+#define LEDC_HSTIMER0_CNT_V 0xFFFFF
+#define LEDC_HSTIMER0_CNT_S 0
+
+#define LEDC_HSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0148)
+
+/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose apb_clk or ref_tick
+ * for high speed timer1. 1'b1:apb_clk 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_HSTIMER1 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_V 0x1
+#define LEDC_TICK_SEL_HSTIMER1_S 25
+
+/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset high speed timer1 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_HSTIMER1_RST (BIT(24))
+#define LEDC_HSTIMER1_RST_M (BIT(24))
+#define LEDC_HSTIMER1_RST_V 0x1
+#define LEDC_HSTIMER1_RST_S 24
+
+/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in high speed timer1 */
+
+#define LEDC_HSTIMER1_PAUSE (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_V 0x1
+#define LEDC_HSTIMER1_PAUSE_S 23
+
+/* LEDC_DIV_NUM_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter
+ * for divider in high speed timer1 the least significant eight bits
+ * represent the decimal part.
+ */
+
+#define LEDC_DIV_NUM_HSTIMER1 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER1_M ((LEDC_DIV_NUM_HSTIMER1_V)<<(LEDC_DIV_NUM_HSTIMER1_S))
+#define LEDC_DIV_NUM_HSTIMER1_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER1_S 5
+
+/* LEDC_HSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in high speed timer1. the counter range is [0 2**reg_hstimer1_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_HSTIMER1_DUTY_RES 0x0000001F
+#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
+#define LEDC_HSTIMER1_DUTY_RES_V 0x1F
+#define LEDC_HSTIMER1_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_HSTIMER1_LIM LEDC_HSTIMER1_DUTY_RES
+#define LEDC_HSTIMER1_LIM_M LEDC_HSTIMER1_DUTY_RES_M
+#define LEDC_HSTIMER1_LIM_V LEDC_HSTIMER1_DUTY_RES_V
+#define LEDC_HSTIMER1_LIM_S LEDC_HSTIMER1_DUTY_RES_S
+
+#define LEDC_HSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x014C)
+
+/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current counter
+ * value in high speed timer1.
+ */
+
+#define LEDC_HSTIMER1_CNT 0x000FFFFF
+#define LEDC_HSTIMER1_CNT_M ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))
+#define LEDC_HSTIMER1_CNT_V 0xFFFFF
+#define LEDC_HSTIMER1_CNT_S 0
+
+#define LEDC_HSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0150)
+
+/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose apb_clk or ref_tick for high
+ * speed timer2.
+ * 1:apb_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_HSTIMER2 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_V 0x1
+#define LEDC_TICK_SEL_HSTIMER2_S 25
+
+/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset high speed timer2 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_HSTIMER2_RST (BIT(24))
+#define LEDC_HSTIMER2_RST_M (BIT(24))
+#define LEDC_HSTIMER2_RST_V 0x1
+#define LEDC_HSTIMER2_RST_S 24
+
+/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in high
+ * speed timer2
+ */
+
+#define LEDC_HSTIMER2_PAUSE (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_V 0x1
+#define LEDC_HSTIMER2_PAUSE_S 23
+
+/* LEDC_DIV_NUM_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter for divider
+ * in high speed timer2 the least significant eight bits represent
+ * the decimal part.
+ */
+
+#define LEDC_DIV_NUM_HSTIMER2 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER2_M ((LEDC_DIV_NUM_HSTIMER2_V)<<(LEDC_DIV_NUM_HSTIMER2_S))
+#define LEDC_DIV_NUM_HSTIMER2_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER2_S 5
+
+/* LEDC_HSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in high speed timer2. the counter range is [0 2**reg_hstimer2_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_HSTIMER2_DUTY_RES 0x0000001F
+#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
+#define LEDC_HSTIMER2_DUTY_RES_V 0x1F
+#define LEDC_HSTIMER2_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_HSTIMER2_LIM LEDC_HSTIMER2_DUTY_RES
+#define LEDC_HSTIMER2_LIM_M LEDC_HSTIMER2_DUTY_RES_M
+#define LEDC_HSTIMER2_LIM_V LEDC_HSTIMER2_DUTY_RES_V
+#define LEDC_HSTIMER2_LIM_S LEDC_HSTIMER2_DUTY_RES_S
+
+#define LEDC_HSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0154)
+
+/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in high speed timer2
+ */
+
+#define LEDC_HSTIMER2_CNT 0x000FFFFF
+#define LEDC_HSTIMER2_CNT_M ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))
+#define LEDC_HSTIMER2_CNT_V 0xFFFFF
+#define LEDC_HSTIMER2_CNT_S 0
+
+#define LEDC_HSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0158)
+
+/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose apb_clk or ref_tick
+ * for high speed timer3.
+ * 1'b1:apb_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_HSTIMER3 (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_V 0x1
+#define LEDC_TICK_SEL_HSTIMER3_S 25
+
+/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset high speed timer3
+ * the counter will be 0 after reset.
+ */
+
+#define LEDC_HSTIMER3_RST (BIT(24))
+#define LEDC_HSTIMER3_RST_M (BIT(24))
+#define LEDC_HSTIMER3_RST_V 0x1
+#define LEDC_HSTIMER3_RST_S 24
+
+/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter
+ * in high speed timer3
+ */
+
+#define LEDC_HSTIMER3_PAUSE (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_M (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_V 0x1
+#define LEDC_HSTIMER3_PAUSE_S 23
+
+/* LEDC_DIV_NUM_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter
+ * for divider in high speed timer3 the least significant eight bits
+ * represent the decimal part.
+ */
+
+#define LEDC_DIV_NUM_HSTIMER3 0x0003FFFF
+#define LEDC_DIV_NUM_HSTIMER3_M ((LEDC_DIV_NUM_HSTIMER3_V)<<(LEDC_DIV_NUM_HSTIMER3_S))
+#define LEDC_DIV_NUM_HSTIMER3_V 0x3FFFF
+#define LEDC_DIV_NUM_HSTIMER3_S 5
+
+/* LEDC_HSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in high speed timer3. The counter range is [0 2**reg_hstimer3_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_HSTIMER3_DUTY_RES 0x0000001F
+#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
+#define LEDC_HSTIMER3_DUTY_RES_V 0x1F
+#define LEDC_HSTIMER3_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_HSTIMER3_LIM LEDC_HSTIMER3_DUTY_RES
+#define LEDC_HSTIMER3_LIM_M LEDC_HSTIMER3_DUTY_RES_M
+#define LEDC_HSTIMER3_LIM_V LEDC_HSTIMER3_DUTY_RES_V
+#define LEDC_HSTIMER3_LIM_S LEDC_HSTIMER3_DUTY_RES_S
+
+#define LEDC_HSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x015C)
+
+/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in high speed timer3
+ */
+
+#define LEDC_HSTIMER3_CNT 0x000FFFFF
+#define LEDC_HSTIMER3_CNT_M ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))
+#define LEDC_HSTIMER3_CNT_V 0xFFFFF
+#define LEDC_HSTIMER3_CNT_S 0
+
+#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x0160)
+
+/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+
+/* Description: Set this bit to update reg_div_num_lstime0
+ * and reg_lstimer0_lim.
+ */
+
+#define LEDC_LSTIMER0_PARA_UP (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_V 0x1
+#define LEDC_LSTIMER0_PARA_UP_S 26
+
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose slow_clk or ref_tick
+ * for low speed timer0.
+ * 1'b1:slow_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_LSTIMER0 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_V 0x1
+#define LEDC_TICK_SEL_LSTIMER0_S 25
+
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset low speed timer0 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_LSTIMER0_RST (BIT(24))
+#define LEDC_LSTIMER0_RST_M (BIT(24))
+#define LEDC_LSTIMER0_RST_V 0x1
+#define LEDC_LSTIMER0_RST_S 24
+
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in low speed timer0. */
+
+#define LEDC_LSTIMER0_PAUSE (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_V 0x1
+#define LEDC_LSTIMER0_PAUSE_S 23
+
+/* LEDC_DIV_NUM_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter
+ * for divider in low speed timer0 the least significant eight bits
+ * represent the decimal part.
+ */
+
+#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))
+#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER0_S 5
+
+/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in low speed timer0. the counter range is [0 2**reg_lstimer0_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_LSTIMER0_DUTY_RES 0x0000001F
+#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V 0x1F
+#define LEDC_LSTIMER0_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_LSTIMER0_LIM LEDC_LSTIMER0_DUTY_RES
+#define LEDC_LSTIMER0_LIM_M LEDC_LSTIMER0_DUTY_RES_M
+#define LEDC_LSTIMER0_LIM_V LEDC_LSTIMER0_DUTY_RES_V
+#define LEDC_LSTIMER0_LIM_S LEDC_LSTIMER0_DUTY_RES_S
+
+#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x0164)
+
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in low speed timer0.
+ */
+
+#define LEDC_LSTIMER0_CNT 0x000FFFFF
+#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V 0xFFFFF
+#define LEDC_LSTIMER0_CNT_S 0
+
+#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168)
+
+/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+
+/* Description: Set this bit to update reg_div_num_lstime1
+ * and reg_lstimer1_lim.
+ */
+
+#define LEDC_LSTIMER1_PARA_UP (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_V 0x1
+#define LEDC_LSTIMER1_PARA_UP_S 26
+
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose slow_clk or ref_tick
+ * for low speed timer1.
+ * 1:slow_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_LSTIMER1 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_V 0x1
+#define LEDC_TICK_SEL_LSTIMER1_S 25
+
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset low speed timer1 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_LSTIMER1_RST (BIT(24))
+#define LEDC_LSTIMER1_RST_M (BIT(24))
+#define LEDC_LSTIMER1_RST_V 0x1
+#define LEDC_LSTIMER1_RST_S 24
+
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter
+ * in low speed timer1.
+ */
+
+#define LEDC_LSTIMER1_PAUSE (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_V 0x1
+#define LEDC_LSTIMER1_PAUSE_S 23
+
+/* LEDC_DIV_NUM_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter for divider
+ * in low speed timer1 the least significant eight bits represent the
+ * decimal part.
+ */
+
+#define LEDC_DIV_NUM_LSTIMER1 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER1_M ((LEDC_DIV_NUM_LSTIMER1_V)<<(LEDC_DIV_NUM_LSTIMER1_S))
+#define LEDC_DIV_NUM_LSTIMER1_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER1_S 5
+
+/* LEDC_LSTIMER1_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in low speed timer1. The counter range is [0 2**reg_lstimer1_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_LSTIMER1_DUTY_RES 0x0000001F
+#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V 0x1F
+#define LEDC_LSTIMER1_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_LSTIMER1_LIM LEDC_LSTIMER1_DUTY_RES
+#define LEDC_LSTIMER1_LIM_M LEDC_LSTIMER1_DUTY_RES_M
+#define LEDC_LSTIMER1_LIM_V LEDC_LSTIMER1_DUTY_RES_V
+#define LEDC_LSTIMER1_LIM_S LEDC_LSTIMER1_DUTY_RES_S
+
+#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x016C)
+
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in low speed timer1.
+ */
+
+#define LEDC_LSTIMER1_CNT 0x000FFFFF
+#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V 0xFFFFF
+#define LEDC_LSTIMER1_CNT_S 0
+
+#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x0170)
+
+/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+
+/* Description: Set this bit to update reg_div_num_lstime2
+ * and reg_lstimer2_lim.
+ */
+
+#define LEDC_LSTIMER2_PARA_UP (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_V 0x1
+#define LEDC_LSTIMER2_PARA_UP_S 26
+
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose slow_clk or ref_tick
+ * for low speed timer2.
+ * 1:slow_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_LSTIMER2 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_V 0x1
+#define LEDC_TICK_SEL_LSTIMER2_S 25
+
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset low speed timer2 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_LSTIMER2_RST (BIT(24))
+#define LEDC_LSTIMER2_RST_M (BIT(24))
+#define LEDC_LSTIMER2_RST_V 0x1
+#define LEDC_LSTIMER2_RST_S 24
+
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in low speed timer2. */
+
+#define LEDC_LSTIMER2_PAUSE (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_V 0x1
+#define LEDC_LSTIMER2_PAUSE_S 23
+
+/* LEDC_DIV_NUM_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter
+ * for divider in low speed timer2 the least significant eight bits
+ * represent the decimal part.
+ */
+
+#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))
+#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER2_S 5
+
+/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in low speed timer2. the counter range is [0 2**reg_lstimer2_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_LSTIMER2_DUTY_RES 0x0000001F
+#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V 0x1F
+#define LEDC_LSTIMER2_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_LSTIMER2_LIM LEDC_LSTIMER2_DUTY_RES
+#define LEDC_LSTIMER2_LIM_M LEDC_LSTIMER2_DUTY_RES_M
+#define LEDC_LSTIMER2_LIM_V LEDC_LSTIMER2_DUTY_RES_V
+#define LEDC_LSTIMER2_LIM_S LEDC_LSTIMER2_DUTY_RES_S
+
+#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x0174)
+
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in low speed timer2.
+ */
+
+#define LEDC_LSTIMER2_CNT 0x000FFFFF
+#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V 0xFFFFF
+#define LEDC_LSTIMER2_CNT_S 0
+
+#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178)
+
+/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+
+/* Description: Set this bit to update reg_div_num_lstime3
+ * and reg_lstimer3_lim.
+ */
+
+#define LEDC_LSTIMER3_PARA_UP (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_M (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_V 0x1
+#define LEDC_LSTIMER3_PARA_UP_S 26
+
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+
+/* Description: This bit is used to choose slow_clk or ref_tick
+ * for low speed timer3.
+ * 1:slow_clk
+ * 0:ref_tick
+ */
+
+#define LEDC_TICK_SEL_LSTIMER3 (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_M (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_V 0x1
+#define LEDC_TICK_SEL_LSTIMER3_S 25
+
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+
+/* Description: This bit is used to reset low speed timer3 the counter
+ * will be 0 after reset.
+ */
+
+#define LEDC_LSTIMER3_RST (BIT(24))
+#define LEDC_LSTIMER3_RST_M (BIT(24))
+#define LEDC_LSTIMER3_RST_V 0x1
+#define LEDC_LSTIMER3_RST_S 24
+
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: This bit is used to pause the counter in low speed timer3. */
+
+#define LEDC_LSTIMER3_PAUSE (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_M (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_V 0x1
+#define LEDC_LSTIMER3_PAUSE_S 23
+
+/* LEDC_DIV_NUM_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+
+/* Description: This register is used to configure parameter for divider
+ * in low speed timer3 the least significant eight bits represent the
+ * decimal part.
+ */
+
+#define LEDC_DIV_NUM_LSTIMER3 0x0003FFFF
+#define LEDC_DIV_NUM_LSTIMER3_M ((LEDC_DIV_NUM_LSTIMER3_V)<<(LEDC_DIV_NUM_LSTIMER3_S))
+#define LEDC_DIV_NUM_LSTIMER3_V 0x3FFFF
+#define LEDC_DIV_NUM_LSTIMER3_S 5
+
+/* LEDC_LSTIMER3_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+/* Description: This register controls the range of the counter
+ * in low speed timer3. the counter range is [0 2**reg_lstimer3_lim]
+ * the max bit width for counter is 20.
+ */
+
+#define LEDC_LSTIMER3_DUTY_RES 0x0000001F
+#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V 0x1F
+#define LEDC_LSTIMER3_DUTY_RES_S 0
+
+/* Keep the definitions below to be compatible with previous version */
+
+#define LEDC_LSTIMER3_LIM LEDC_LSTIMER3_DUTY_RES
+#define LEDC_LSTIMER3_LIM_M LEDC_LSTIMER3_DUTY_RES_M
+#define LEDC_LSTIMER3_LIM_V LEDC_LSTIMER3_DUTY_RES_V
+#define LEDC_LSTIMER3_LIM_S LEDC_LSTIMER3_DUTY_RES_S
+
+#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x017C)
+
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+
+/* Description: software can read this register to get the current
+ * counter value in low speed timer3.
+ */
+
+#define LEDC_LSTIMER3_CNT 0x000FFFFF
+#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V 0xFFFFF
+#define LEDC_LSTIMER3_CNT_S 0
+
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x0180)
+
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 7 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23
+
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 6 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 22
+
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 5 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 21
+
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 4 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20
+
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 3 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 19
+
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 2 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 18
+
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 1 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17
+
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel 0 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 16
+
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 7 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S 15
+
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 6 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14
+
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 5 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S 13
+
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 4 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S 12
+
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 3 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11
+
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 2 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S 10
+
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 1 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S 9
+
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel 0 duty
+ * change done.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8
+
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel3
+ * counter overflow.
+ */
+
+#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S 7
+
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel2
+ * counter overflow.
+ */
+
+#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S 6
+
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel1
+ * counter overflow.
+ */
+
+#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S 5
+
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for low speed channel0
+ * counter overflow.
+ */
+
+#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S 4
+
+/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel3
+ * counter overflow.
+ */
+
+#define LEDC_HSTIMER3_OVF_INT_RAW (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_RAW_S 3
+
+/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel2
+ * counter overflow.
+ */
+
+#define LEDC_HSTIMER2_OVF_INT_RAW (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_RAW_S 2
+
+/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel1
+ * counter overflow.
+ */
+
+#define LEDC_HSTIMER1_OVF_INT_RAW (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_RAW_S 1
+
+/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+
+/* Description: The interrupt raw bit for high speed channel0
+ * counter overflow.
+ */
+
+#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_RAW_S 0
+
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184)
+
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */
+
+/* Description: The interrupt status bit for low speed channel 7 duty
+ * change done event
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 23
+
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 6 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 22
+
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 5 duty change
+ * done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21
+
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 4 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 20
+
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 3 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 19
+
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 2 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18
+
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 1 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 17
+
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel 0 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 16
+
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 7 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15
+
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 6 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S 14
+
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 5 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S 13
+
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 4 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12
+
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 3 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S 11
+
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 2 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S 10
+
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 1 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9
+
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel 0 duty
+ * change done event.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S 8
+
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel3
+ * counter overflow event.
+ */
+
+#define LEDC_LSTIMER3_OVF_INT_ST (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S 7
+
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel2
+ * counter overflow event.
+ */
+
+#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S 6
+
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel1
+ * counter overflow event.
+ */
+
+#define LEDC_LSTIMER1_OVF_INT_ST (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S 5
+
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for low speed channel0
+ * counter overflow event.
+ */
+
+#define LEDC_LSTIMER0_OVF_INT_ST (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S 4
+
+/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel3
+ * counter overflow event.
+ */
+
+#define LEDC_HSTIMER3_OVF_INT_ST (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_ST_S 3
+
+/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel2
+ * counter overflow event.
+ */
+
+#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_ST_S 2
+
+/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel1
+ * counter overflow event.
+ */
+
+#define LEDC_HSTIMER1_OVF_INT_ST (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_ST_S 1
+
+/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+
+/* Description: The interrupt status bit for high speed channel0
+ * counter overflow event.
+ */
+
+#define LEDC_HSTIMER0_OVF_INT_ST (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_ST_S 0
+
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x0188)
+
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 7 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23
+
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 6 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 22
+
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 5 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 21
+
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 4 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20
+
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 3 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 19
+
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 2 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 18
+
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 1 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17
+
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel 0 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 16
+
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 7 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S 15
+
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 6 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14
+
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 5 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S 13
+
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 4 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S 12
+
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 3 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11
+
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 2 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S 10
+
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 1 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S 9
+
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel 0 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8
+
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel3 counter
+ * overflow interrupt.
+ */
+
+#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S 7
+
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel2 counter
+ * overflow interrupt.
+ */
+
+#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S 6
+
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel1
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S 5
+
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for low speed channel0
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S 4
+
+/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel3
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER3_OVF_INT_ENA (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_ENA_S 3
+
+/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel2
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER2_OVF_INT_ENA (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_ENA_S 2
+
+/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel1
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_ENA_S 1
+
+/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+
+/* Description: The interrupt enable bit for high speed channel0
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER0_OVF_INT_ENA (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_ENA_S 0
+
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x018C)
+
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */
+
+/* Description: Set this bit to clear low speed channel 7 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 23
+
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 6 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22
+
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 5 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 21
+
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 4 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 20
+
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 3 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19
+
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 2 duty change
+ * done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 18
+
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 1 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 17
+
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel 0 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16
+
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 7 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S 15
+
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 6 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S 14
+
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 5 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13
+
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 4 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S 12
+
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 3 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S 11
+
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 2 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10
+
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 1 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S 9
+
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel 0 duty
+ * change done interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S 8
+
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel3
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S 7
+
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel2
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S 6
+
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel1
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S 5
+
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear low speed channel0
+ * counter overflow interrupt.
+ */
+
+#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S 4
+
+/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel3
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER3_OVF_INT_CLR_S 3
+
+/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel2
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER2_OVF_INT_CLR (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_M (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER2_OVF_INT_CLR_S 2
+
+/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel1
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER1_OVF_INT_CLR (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_M (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER1_OVF_INT_CLR_S 1
+
+/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+
+/* Description: Set this bit to clear high speed channel0
+ * counter overflow interrupt.
+ */
+
+#define LEDC_HSTIMER0_OVF_INT_CLR (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_M (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_V 0x1
+#define LEDC_HSTIMER0_OVF_INT_CLR_S 0
+
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x0190)
+
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+
+/* Description: This bit is used to set the frequency of slow_clk.
+ * 1'b1:80mhz
+ * 1'b0:8mhz
+ */
+
+#define LEDC_APB_CLK_SEL (BIT(0))
+#define LEDC_APB_CLK_SEL_M (BIT(0))
+#define LEDC_APB_CLK_SEL_V 0x1
+#define LEDC_APB_CLK_SEL_S 0
+
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC)
+
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */
+
+/* Description: This register represents the version. */
+
+#define LEDC_DATE 0xFFFFFFFF
+#define LEDC_DATE_M ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V 0xFFFFFFFF
+#define LEDC_DATE_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_LEDC_H */
[incubator-nuttx] 02/02: esp32-devkitc: Add support to PWM
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d7ec3e30aeedce5575a57ffddce3907660c37ae2
Author: Alan C. Assis <ac...@gmail.com>
AuthorDate: Thu Jan 6 14:13:58 2022 -0300
esp32-devkitc: Add support to PWM
---
.../esp32/esp32-devkitc/configs/pwm/defconfig | 55 +++++++++
boards/xtensa/esp32/esp32-devkitc/src/Make.defs | 4 +
.../xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h | 12 ++
.../xtensa/esp32/esp32-devkitc/src/esp32_bringup.c | 8 ++
boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c | 134 +++++++++++++++++++++
5 files changed, 213 insertions(+)
diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig
new file mode 100644
index 0000000..0a620e4
--- /dev/null
+++ b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig
@@ -0,0 +1,55 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32-devkitc"
+CONFIG_ARCH_BOARD_ESP32_DEVKITC=y
+CONFIG_ARCH_CHIP="esp32"
+CONFIG_ARCH_CHIP_ESP32=y
+CONFIG_ARCH_CHIP_ESP32WROVER=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_ESP32_LEDC=y
+CONFIG_ESP32_LEDC_CHANNEL0_PIN=12
+CONFIG_ESP32_LEDC_CHANNEL1_PIN=13
+CONFIG_ESP32_LEDC_CHANNEL2_PIN=14
+CONFIG_ESP32_LEDC_CHANNEL3_PIN=15
+CONFIG_ESP32_LEDC_TIM0=y
+CONFIG_ESP32_LEDC_TIM1=y
+CONFIG_ESP32_UART0=y
+CONFIG_EXAMPLES_PWM=y
+CONFIG_EXAMPLES_PWM_FREQUENCY=10000
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MM_REGIONS=3
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
diff --git a/boards/xtensa/esp32/esp32-devkitc/src/Make.defs b/boards/xtensa/esp32/esp32-devkitc/src/Make.defs
index 9400680..dcc7c6b 100644
--- a/boards/xtensa/esp32/esp32-devkitc/src/Make.defs
+++ b/boards/xtensa/esp32/esp32-devkitc/src/Make.defs
@@ -39,6 +39,10 @@ ifeq ($(CONFIG_DEV_GPIO),y)
CSRCS += esp32_gpio.c
endif
+ifeq ($(CONFIG_PWM),y)
+CSRCS += esp32_ledc.c
+endif
+
ifeq ($(CONFIG_USERLED),y)
CSRCS += esp32_userleds.c
endif
diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h b/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h
index ed50556..2640f5a 100644
--- a/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h
+++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h
@@ -110,6 +110,18 @@ int esp32_gpio_init(void);
#endif
/****************************************************************************
+ * Name: esp32_ledc_setup
+ *
+ * Description:
+ * Initialize LEDC PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32_LEDC
+int esp32_pwm_setup(void);
+#endif
+
+/****************************************************************************
* Name: board_spidev_initialize
*
* Description:
diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
index b14cab0..393e902 100644
--- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
+++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c
@@ -223,6 +223,14 @@ int esp32_bringup(void)
}
#endif
+#ifdef CONFIG_ESP32_LEDC
+ ret = esp32_pwm_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: esp32_pwm_setup() failed: %d\n", ret);
+ }
+#endif /* CONFIG_ESP32_LEDC */
+
#ifdef CONFIG_ESP32_RT_TIMER
ret = esp32_rt_timer_init();
if (ret < 0)
diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c
new file mode 100644
index 0000000..ed85838
--- /dev/null
+++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c
@@ -0,0 +1,134 @@
+/****************************************************************************
+ * boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/timers/pwm.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "esp32_ledc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_pwm_setup
+ *
+ * Description:
+ * Initialize LEDC PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+int esp32_pwm_setup(void)
+{
+ int ret;
+ struct pwm_lowerhalf_s *pwm;
+
+#ifdef CONFIG_ESP32_LEDC_TIM0
+ pwm = esp32_ledc_init(0);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm0" */
+
+ ret = pwm_register("/dev/pwm0", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM1
+ pwm = esp32_ledc_init(1);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm1" */
+
+ ret = pwm_register("/dev/pwm1", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM2
+ pwm = esp32_ledc_init(2);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm2" */
+
+ ret = pwm_register("/dev/pwm2", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_ESP32_LEDC_TIM3
+ pwm = esp32_ledc_init(3);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 3 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm3" */
+
+ ret = pwm_register("/dev/pwm3", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ return OK;
+}
+