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Posted to commits@nuttx.apache.org by da...@apache.org on 2021/12/16 12:23:51 UTC
[incubator-nuttx] 01/01: Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working."
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch revert-5010-stm32h7_sdmmc_50MHz_clk
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 157cb668c7c2c9ecaa85723c622d1fbb2a50449c
Author: David Sidrane <Da...@Nscdg.com>
AuthorDate: Thu Dec 16 04:23:46 2021 -0800
Revert "stm32h7 sdmmc: set SDMMC_CK pin to high speed (50 MHz) mode. When it was in slow speed mode (by default), the output SDMMC_CK clock rise and fall times were about 13 ns each, that were very slow and prevented some SDIO devices from working."
This reverts commit 0aecfe86913074586efc64798fae205e0d78104e.
---
arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 15 ++++-----------
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
index 8a1724e..54a59e7 100644
--- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
@@ -1049,17 +1049,10 @@
#define GPIO_SAI4_SD_B_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTE|GPIO_PIN3)
#define GPIO_SAI4_SD_B_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTF|GPIO_PIN6)
-/* SD/MMC
- *
- * Note that the below configures GPIO_SPEED_50MHz I/O. In case of using
- * the SD/MMC it is recommended to enable I/O compensation cell for slew rate
- * control on I/O commutation to reduce the I/O noise on power supply.
- * The I/O commutation cell can be enabled by setting
- * CONFIG_STM32_SYSCFG_IOCOMPENSATION=y option in your board configuration.
- */
+/* SD/MMC */
#define GPIO_SDMMC1_CDIR (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CKIN (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN8)
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
@@ -1073,8 +1066,8 @@
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
-#define GPIO_SDMMC2_CK_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
-#define GPIO_SDMMC2_CK_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_SDMMC2_CK_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6)
+#define GPIO_SDMMC2_CK_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN1)
#define GPIO_SDMMC2_CMD_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN7)
#define GPIO_SDMMC2_CMD_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
#define GPIO_SDMMC2_D0 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)