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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/06/16 14:20:39 UTC
[incubator-nuttx] 02/02: esp32s3: Add support to USBSERIAL to use as console
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4eddde90b073615cdf55b168c20063f898cc9423
Author: Alan Carvalho de Assis <ac...@gmail.com>
AuthorDate: Wed Jun 15 15:56:10 2022 -0300
esp32s3: Add support to USBSERIAL to use as console
---
arch/xtensa/src/esp32s3/Kconfig | 6 +
arch/xtensa/src/esp32s3/Make.defs | 4 +
arch/xtensa/src/esp32s3/esp32s3_config.h | 5 +
arch/xtensa/src/esp32s3/esp32s3_serial.c | 15 +-
arch/xtensa/src/esp32s3/esp32s3_usbserial.c | 480 ++++++++
.../{esp32s3_config.h => esp32s3_usbserial.h} | 51 +-
.../src/esp32s3/hardware/esp32s3_usb_serial_jtag.h | 1233 ++++++++++++++++++++
7 files changed, 1761 insertions(+), 33 deletions(-)
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
index 8e9bdca7a6..33f3026db7 100644
--- a/arch/xtensa/src/esp32s3/Kconfig
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -351,6 +351,12 @@ config ESP32S3_UART2
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
+config ESP32S3_USBSERIAL
+ bool "USB-Serial Driver"
+ default n
+ select OTHER_UART_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
config ESP32S3_TIMER0
bool "54-bit Timer 0 (Group 0 Timer 0)"
default n
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
index c9ac4576b4..482b91346d 100644
--- a/arch/xtensa/src/esp32s3/Make.defs
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -89,6 +89,10 @@ CHIP_ASRCS = esp32s3_cpuindex.S
CHIP_CSRCS += esp32s3_cpuidlestack.c esp32s3_cpustart.c esp32s3_intercpu_interrupt.c
endif
+ifeq ($(CONFIG_ESP32S3_USBSERIAL),y)
+CHIP_CSRCS += esp32s3_usbserial.c
+endif
+
ifeq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += esp32s3_tickless.c
else
diff --git a/arch/xtensa/src/esp32s3/esp32s3_config.h b/arch/xtensa/src/esp32s3/esp32s3_config.h
index ea510fdf18..8305d587a2 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_config.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_config.h
@@ -61,4 +61,9 @@
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define HAVE_SERIAL_CONSOLE 1
+# define HAVE_UART_DEVICE 1
+#endif
+
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_serial.c b/arch/xtensa/src/esp32s3/esp32s3_serial.c
index a560fa2268..30ea4a0aaf 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_serial.c
+++ b/arch/xtensa/src/esp32s3/esp32s3_serial.c
@@ -48,6 +48,10 @@
#include "hardware/esp32s3_uart.h"
#include "hardware/esp32s3_system.h"
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -89,6 +93,11 @@
# endif
#endif /* CONSOLE_UART */
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
/* Pick ttyS1 */
#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
@@ -1070,7 +1079,7 @@ void xtensa_earlyserialinit(void)
void xtensa_serialinit(void)
{
-#ifdef CONSOLE_UART
+#ifdef CONSOLE_DEV
uart_register("/dev/console", &CONSOLE_DEV);
#endif
@@ -1081,6 +1090,10 @@ void xtensa_serialinit(void)
#ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+ uart_register("/dev/ttyACM0", &TTYACM0_DEV);
+#endif
}
/****************************************************************************
diff --git a/arch/xtensa/src/esp32s3/esp32s3_usbserial.c b/arch/xtensa/src/esp32s3/esp32s3_usbserial.c
new file mode 100644
index 0000000000..f117ff1611
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_usbserial.c
@@ -0,0 +1,480 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_usbserial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/serial/tioctl.h>
+#include <arch/irq.h>
+
+#include "xtensa.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_usb_serial_jtag.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* The hardware buffer has a fixed size of 64 bytes */
+
+#define ESP32S3_USBCDC_BUFFERSIZE 64
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32s3_priv_s
+{
+ const uint8_t periph; /* peripheral ID */
+ const uint8_t irq; /* IRQ number assigned to the peripheral */
+ int cpu; /* CPU id */
+ int cpuint; /* CPU interrupt assigned */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int esp32s3_interrupt(int irq, void *context, void *arg);
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static char g_rxbuffer[ESP32S3_USBCDC_BUFFERSIZE];
+static char g_txbuffer[ESP32S3_USBCDC_BUFFERSIZE];
+
+static struct esp32s3_priv_s g_usbserial_priv =
+{
+ .periph = ESP32S3_PERIPH_USB_DEVICE,
+ .irq = ESP32S3_IRQ_USB_DEVICE,
+ .cpu = 0,
+ .cpuint = -ENOMEM,
+};
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uart_dev_t g_uart_usbserial =
+{
+ .isconsole = true,
+ .recv =
+ {
+ .size = ESP32S3_USBCDC_BUFFERSIZE,
+ .buffer = g_rxbuffer,
+ },
+ .xmit =
+ {
+ .size = ESP32S3_USBCDC_BUFFERSIZE,
+ .buffer = g_txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_usbserial_priv,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_interrupt
+ *
+ * Description:
+ * This is the common UART interrupt handler. It will be invoked
+ * when an interrupt received on the device. It should call
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ****************************************************************************/
+
+static int esp32s3_interrupt(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_INT_ST_REG);
+
+ /* Send buffer has room and can accept new data. */
+
+ if (regval & USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST)
+ {
+ putreg32(USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR,
+ USB_SERIAL_JTAG_INT_CLR_REG);
+ uart_xmitchars(dev);
+ }
+
+ /* Data from the host are available to read. */
+
+ if (regval & USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST)
+ {
+ putreg32(USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR,
+ USB_SERIAL_JTAG_INT_CLR_REG);
+ uart_recvchars(dev);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * This method is called the first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * This method is called when the serial port is closed.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ if (enable)
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG, 0,
+ USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA);
+ }
+ else
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG,
+ USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Call to enable or disable RXRDY interrupts
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ if (enable)
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG, 0,
+ USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA);
+ }
+ else
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG,
+ USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_priv_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Try to attach the IRQ to a CPU int */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->periph,
+ ESP32S3_INT_PRIO_DEF,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, esp32s3_interrupt, dev);
+ if (ret == OK)
+ {
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_priv_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+
+ priv->cpuint = -ENOMEM;
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Return true if the receive holding register is not empty
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_EP1_CONF_REG);
+
+ return regval & USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Return true if the transmit holding register is empty (TXRDY)
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_JFIFO_ST_REG);
+
+ return regval & USB_SERIAL_JTAG_OUT_FIFO_EMPTY;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Return true if the transmit holding register is empty (TXRDY)
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_EP1_CONF_REG);
+
+ return regval & USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE;
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * This method will send one byte on the UART.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ /* Write the character to the buffer. */
+
+ putreg32(ch, USB_SERIAL_JTAG_EP1_REG);
+
+ /* Flush the character out. */
+
+ putreg32(USB_SERIAL_JTAG_WR_DONE, USB_SERIAL_JTAG_EP1_CONF_REG);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one character.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ *status = 0;
+ return getreg32(USB_SERIAL_JTAG_EP1_REG) & USB_SERIAL_JTAG_RDWR_BYTE;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#if defined(CONFIG_SERIAL_TERMIOS)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TERMIOS
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ /* The USB Serial Console has fixed configuration of:
+ * 9600 baudrate, no parity, 8 bits, 1 stopbit.
+ */
+
+ termiosp->c_cflag = CS8;
+ cfsetispeed(termiosp, 9600);
+ }
+ }
+ break;
+
+ case TCSETS:
+ ret = -ENOTTY;
+ break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_usbserial_write
+ *
+ * Description:
+ * Write one character through the USB serial. Used mainly for early
+ * debugging.
+ *
+ ****************************************************************************/
+
+void esp32s3_usbserial_write(char ch)
+{
+ while (!esp32s3_txready(&g_uart_usbserial));
+
+ esp32s3_send(&g_uart_usbserial, ch);
+}
+
diff --git a/arch/xtensa/src/esp32s3/esp32s3_config.h b/arch/xtensa/src/esp32s3/esp32s3_usbserial.h
similarity index 55%
copy from arch/xtensa/src/esp32s3/esp32s3_config.h
copy to arch/xtensa/src/esp32s3/esp32s3_usbserial.h
index ea510fdf18..ace8414e3f 100644
--- a/arch/xtensa/src/esp32s3/esp32s3_config.h
+++ b/arch/xtensa/src/esp32s3/esp32s3_usbserial.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/xtensa/src/esp32s3/esp32s3_config.h
+ * arch/xtensa/src/esp32s3/esp32s3_usbserial.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,47 +18,34 @@
*
****************************************************************************/
-#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
-#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USBSERIAL_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USBSERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
-#include <nuttx/config.h>
-
-#include <arch/chip/chip.h>
-#include <arch/board/board.h>
+#include <nuttx/serial/serial.h>
/****************************************************************************
- * Pre-processor Definitions
+ * Public Data
****************************************************************************/
-/* UARTs ********************************************************************/
-
-/* Are any UARTs enabled? */
-
-#undef HAVE_UART_DEVICE
-#ifdef CONFIG_ESP32S3_UART
-# define HAVE_UART_DEVICE 1
-#endif
+extern uart_dev_t g_uart_usbserial;
-/* Serial Console ***********************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
-/* Is there a serial console? There should be no more than one defined. It
- * could be on any UARTn. n E {0,1}
- */
+/****************************************************************************
+ * Name: esp32s3_usbserial_write
+ *
+ * Description:
+ * Write one character through the USB serial. Used mainly for early
+ * debugging.
+ *
+ ****************************************************************************/
-#undef CONSOLE_UART
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART0)
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# define CONSOLE_UART 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART1)
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# define CONSOLE_UART 1
-#else
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART1_SERIAL_CONSOLE
-#endif
+void esp32s3_usbserial_write(char ch);
-#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_USBSERIAL_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
new file mode 100644
index 0000000000..7b351b327f
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
@@ -0,0 +1,1233 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_USB_SERIAL_JTAG_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_USB_SERIAL_JTAG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/** Configuration Registers */
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ * USB_SERIAL_JTAG_EP1_REG.
+ */
+
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
+
+/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
+ * Write and read byte data to/from UART Tx/Rx FIFO through this field.
+ * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
+ * data (up to 64 bytes) into UART Tx FIFO. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
+ * know how many data is received, then read that amount of data from UART
+ * Rx
+ * FIFO.
+ */
+
+#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000ff
+#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000ff
+#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ * USB_SERIAL_JTAG_CONF0_REG.
+ */
+
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
+
+/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
+ * PHY
+ */
+
+#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001
+#define USB_SERIAL_JTAG_PHY_SEL_S 0
+
+/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ * Enable software control USB D+ D-
+ * exchange
+ */
+
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
+
+/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ * USB D+ D-
+ * exchange
+ */
+
+#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
+
+/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
+ * Control single-end input high threshold. 1.76V to 2V, step
+ * 80mV
+ */
+
+#define USB_SERIAL_JTAG_VREFL 0x00000003
+#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V 0x00000003
+#define USB_SERIAL_JTAG_VREFL_S 3
+
+/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
+ * Control single-end input low threshold. 0.8V to 1.04V, step
+ * 80mV
+ */
+
+#define USB_SERIAL_JTAG_VREFH 0x00000003
+#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V 0x00000003
+#define USB_SERIAL_JTAG_VREFH_S 5
+
+/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ * Enable software control input
+ * threshold
+ */
+
+#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
+
+/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ * Enable software control USB D+ D- pullup
+ * pulldown
+ */
+
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
+
+/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ * Control USB D+ pull
+ * up.
+ */
+
+#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001
+#define USB_SERIAL_JTAG_DP_PULLUP_S 9
+
+/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ * Control USB D+ pull
+ * down.
+ */
+
+#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
+
+/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ * Control USB D- pull
+ * up.
+ */
+
+#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001
+#define USB_SERIAL_JTAG_DM_PULLUP_S 11
+
+/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ * Control USB D- pull
+ * down.
+ */
+
+#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
+
+/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ * Control pull up
+ * value.
+ */
+
+#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
+
+/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ * Enable USB pad
+ * function.
+ */
+
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ * USB_SERIAL_JTAG_TEST_REG.
+ */
+
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
+
+/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ * Enable test of the USB
+ * pad
+ */
+
+#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
+
+/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ * USB pad oen in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
+
+/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ * USB D+ tx value in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
+
+/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ * USB D- tx value in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ * USB_SERIAL_JTAG_MISC_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
+
+/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ * 1'h1: Force clock on for register. 1'h0: Support clock only when
+ * application writes
+ * registers.
+ */
+
+#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
+#define USB_SERIAL_JTAG_CLK_EN_S 0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ * USB_SERIAL_JTAG_MEM_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
+
+/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ * 1: power down usb
+ * memory.
+ */
+
+#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
+
+/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ * 1: Force clock on for usb
+ * memory.
+ */
+
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
+
+/** Status Registers */
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ * USB_SERIAL_JTAG_EP1_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
+
+/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ * Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ * This bit then stays 0 until data in UART Tx FIFO is read by the USB
+ * Host.
+ */
+
+#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001
+#define USB_SERIAL_JTAG_WR_DONE_S 0
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ * 1'b1: Indicate UART Tx FIFO is not full and data can be written into
+ * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
+ * data is sent to the USB
+ * Host.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ * 1'b1: Indicate there is data in UART Rx
+ * FIFO.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ * USB_SERIAL_JTAG_JFIFO_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
+/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
+ * JTAG in fifo
+ * counter.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
+
+/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ * 1: JTAG in fifo is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
+
+/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ * 1: JTAG in fifo is
+ * full.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
+
+/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
+ * JTAT out fifo
+ * counter.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
+
+/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ * 1: JTAG out fifo is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
+
+/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ * 1: JTAG out fifo is
+ * full.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
+
+/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ * Write 1 to reset JTAG in
+ * fifo.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
+
+/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ * Write 1 to reset JTAG out
+ * fifo.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ * USB_SERIAL_JTAG_FRAM_NUM_REG.
+ */
+
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
+
+/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
+ * Frame index of received SOF
+ * frame.
+ */
+
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007ff
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007ff
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP0_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
+
+/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP1_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
+
+/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP2_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
+
+/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP3_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
+
+/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
+
+/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 0. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
+ * EP0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
+
+/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 1. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
+ * EP1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
+ * Data count in OUT endpoint 1 when one packet is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
+
+/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 2. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
+ * EP2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
+
+/** Interrupt Registers */
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ * USB_SERIAL_JTAG_INT_RAW_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when a flush command is
+ * received for IN endpoint 2 of
+ * JTAG.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when a SOF frame is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW :
+ * R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when the Serial Port OUT
+ * Endpoint received one
+ * packet.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW:
+ * R/WTC/SS; bitpos: [3]; default: 1;
+ * The raw interrupt bit turns to high level when the Serial Port IN
+ * Endpoint is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when a PID error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC5 error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC16 error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when a bit stuffing error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW:
+ * R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when an IN token for IN
+ * endpoint 1 is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * The raw interrupt bit turns to high level when a USB bus reset is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW:
+ * R/WTC/SS; bitpos: [10]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 1 received
+ * packet with zero
+ * payload.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW:
+ * R/WTC/SS; bitpos: [11]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 2 received
+ * packet with zero
+ * payload.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ * USB_SERIAL_JTAG_INT_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST: RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST: RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ * USB_SERIAL_JTAG_INT_ENA_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA: R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA: R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA :
+ * R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA :
+ * R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
+
+/* USB_SERIAL_JTAG_INT_CLR_REG register
+ * USB_SERIAL_JTAG_INT_CLR_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR: WT; bitpos: [10]; default: 0
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR:
+ * WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
+
+/* Version Registers */
+
+/* USB_SERIAL_JTAG_DATE_REG register
+ * USB_SERIAL_JTAG_DATE_REG.
+ */
+
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
+
+/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
+ * register version.
+ */
+
+#define USB_SERIAL_JTAG_DATE 0xffffffff
+#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V 0xffffffff
+#define USB_SERIAL_JTAG_DATE_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_USB_SERIAL_JTAG_H */