[GitHub] [tvm-vta] adavare commented on a change in pull request #30: Chisel Pipelined GEMM

[GitBox <gi...@apache.org>]

adavare commented on a change in pull request #30:
URL: https://github.com/apache/tvm-vta/pull/30#discussion_r654050694



##########
File path: hardware/chisel/src/main/scala/core/TensorGemm.scala
##########
@@ -421,3 +544,218 @@ class TensorGemm(debug: Boolean = false)(implicit p: Parameters) extends TensorG
     }
   }
 }
+
+class TensorGemmPipelinedSplit (implicit p: Parameters) extends TensorGemmIfc {
+  val sIdle::sRun::sWait::Nil = Enum(3);
+  val numMVMs = p(CoreKey).blockOutFactor
+  val numOuts = p(CoreKey).blockOut / numMVMs
+  require (numOuts > 0, "-F- Cannot factor more groups than blockOut")
+  val batch = p(CoreKey).batch
+
+  val m = Module(new TensorGemmIndexGenerator)
+
+  // additional pipe latency of wgt/inp read if needed
+  val scratchpadReadLatency = 0
+  val inpReadIdxLatency = 0
+  val uopReadLatency = 0
+
+  val delayed_valid = ShiftRegister(m.io.valid, uopReadLatency + 1, resetData = false.B, en = true.B)
+  val delayed_acc_i = ShiftRegister(m.io.acc_i, uopReadLatency + 1)
+  val delayed_inp_i = ShiftRegister(m.io.inp_i, uopReadLatency + 1)
+  val delayed_wgt_i = ShiftRegister(m.io.wgt_i, uopReadLatency + 1)
+
+  val state = RegInit(sIdle)
+  val inflight = RegInit(0.U(inflightBits.W))
+
+  val capture_dec = Reg( chiselTypeOf( io.dec))
+
+  io.done := false.B
+  when( state === sIdle && io.start) {
+    state := sRun
+    capture_dec := io.dec
+    // if (io.dec.empty_0 != None) assert(io.dec.empty_0.get === 0.U)
+    // if (io.dec.empty_1 != None) assert(io.dec.empty_1.get === 0.U)
+  }.elsewhen( state === sRun && m.io.last) {
+    state := sWait
+  }.elsewhen( state === sWait && inflight === 0.U) {
+    state := sIdle
+    io.done := true.B
+  }
+  io.state := state
+
+  if ( false) {

Review comment:
       @stevenmburns: Removed, thanks for catching this!




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