You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@harmony.apache.org by gs...@apache.org on 2007/04/17 13:05:11 UTC
svn commit: r529560 -
/harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp
Author: gshimansky
Date: Tue Apr 17 04:05:10 2007
New Revision: 529560
URL: http://svn.apache.org/viewvc?view=rev&rev=529560
Log:
Added conditional compilation for x86_64 and ia64 platforms. Assembly implementation for these
platforms should be different.
Modified:
harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp
Modified: harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp
URL: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp?view=diff&rev=529560&r1=529559&r2=529560
==============================================================================
--- harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp (original)
+++ harmony/enhanced/drlvm/trunk/vm/vmcore/src/thread/linux/atomics.cpp Tue Apr 17 04:05:10 2007
@@ -18,6 +18,11 @@
void MemoryReadWriteBarrier() {
+#if defined(_EM64T_)
+ asm volatile ("mfence");
+#elif defined(_IPF_)
+ asm volatile ("mf" ::: "memory");
+#else // General x86 case
/*
* This code must use a lock-prefixed assembly instruction, so that
* we can support P3 processors (SSE2 only). With P4 and SSE3, we
@@ -30,15 +35,20 @@
* This is a GCC inline assembly command. The final bit, "memory", will
* clobber all of the memory registers.
*/
- asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
+ asm volatile ("lock; addl $0,0(%%esp)" : : : "memory");
+#endif
}
void MemoryWriteBarrier() {
+#if defined(_IPF_)
+ asm volatile ("mf" ::: "memory");
+#else // General x86 and x86_64 case
/*
* We could use the same lock-prefixed assembly instruction above,
* but since we have support for P3 processors (SSE2) we'll just
* use 'sfence'.
*/
asm volatile ("sfence" : : : "memory");
+#endif
}