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Posted to commits@nuttx.apache.org by "xiaoxiang781216 (via GitHub)" <gi...@apache.org> on 2024/02/03 18:51:43 UTC
Re: [PR] RP2040: Support Clock Outputs [nuttx]
xiaoxiang781216 commented on code in PR #11648:
URL: https://github.com/apache/nuttx/pull/11648#discussion_r1477112270
##########
arch/arm/src/rp2040/rp2040_gpio.h:
##########
@@ -55,12 +55,18 @@
#define RP2040_GPIO_FUNC_USB RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_USB
#define RP2040_GPIO_FUNC_NULL RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL
+/* GPIO function pins *******************************************************/
Review Comment:
add blank line
##########
arch/arm/src/rp2040/Kconfig:
##########
@@ -663,6 +663,211 @@ endif # ADC
endif # RP2040_ADC
+#####################################################################
+# CLK_GPOUT Configuration
+#####################################################################
+menu "GPIO Clock Output"
+config RP2040_CLK_GPOUT_ENABLE
+ bool "Enable Clock Outputs"
+ default n
+
+config RP2040_CLK_GPOUT0
+ bool "CLK_GPOUT0 Clock Output (pin 21)"
+ depends on RP2040_CLK_GPOUT_ENABLE
+ default n
+ ---help---
+ Enable CLK_GPOUT0
+
+if RP2040_CLK_GPOUT0
+choice
+ prompt "Source Clock"
+ depends on RP2040_CLK_GPOUT0
+
+ config RP2040_CLK_GPOUT0_SRC_REF
+ bool "REF (6 - 12 MHz)"
+ ---help---
+ Reference clock that is always running unless in DORMANT mode. Runs from
+ Ring Oscillator (ROSC) at power-up but can be switched to Crystal
+ Oscillator (XOSC) for more accuracy.
+ config RP2040_CLK_GPOUT0_SRC_SYS
+ bool "SYS (125 MHz)"
+ ---help---
+ System clock that is always running unless in DORMANT mode. Runs from
+ clk_ref at power-up but is typically switched to a PLL.
+ config RP2040_CLK_GPOUT0_SRC_USB
+ bool "USB (48 MHz)"
+ ---help---
+ USB reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_ADC
+ bool "ADC (48 MHz)"
+ ---help---
+ ADC reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_RTC
+ bool "RTC (46875 Hz)"
+ ---help---
+ RTC reference clock. The RTC divides this clock to generate a 1 second reference.
+endchoice
+
+config RP2040_CLK_GPOUT0_DIVINT
+ int "Divisor (Integer)"
+ depends on RP2040_CLK_GPOUT0
+ default 1
+
+config RP2040_CLK_GPOUT0_DIVFRAC
+ int "Divisor (Fractional)"
+ depends on RP2040_CLK_GPOUT0
Review Comment:
remove
##########
arch/arm/src/rp2040/Kconfig:
##########
@@ -663,6 +663,211 @@ endif # ADC
endif # RP2040_ADC
+#####################################################################
+# CLK_GPOUT Configuration
+#####################################################################
Review Comment:
add blank line
##########
arch/arm/src/rp2040/Kconfig:
##########
@@ -663,6 +663,211 @@ endif # ADC
endif # RP2040_ADC
+#####################################################################
+# CLK_GPOUT Configuration
+#####################################################################
+menu "GPIO Clock Output"
+config RP2040_CLK_GPOUT_ENABLE
+ bool "Enable Clock Outputs"
+ default n
+
+config RP2040_CLK_GPOUT0
+ bool "CLK_GPOUT0 Clock Output (pin 21)"
+ depends on RP2040_CLK_GPOUT_ENABLE
+ default n
+ ---help---
+ Enable CLK_GPOUT0
+
+if RP2040_CLK_GPOUT0
+choice
+ prompt "Source Clock"
+ depends on RP2040_CLK_GPOUT0
+
+ config RP2040_CLK_GPOUT0_SRC_REF
+ bool "REF (6 - 12 MHz)"
+ ---help---
+ Reference clock that is always running unless in DORMANT mode. Runs from
+ Ring Oscillator (ROSC) at power-up but can be switched to Crystal
+ Oscillator (XOSC) for more accuracy.
+ config RP2040_CLK_GPOUT0_SRC_SYS
+ bool "SYS (125 MHz)"
+ ---help---
+ System clock that is always running unless in DORMANT mode. Runs from
+ clk_ref at power-up but is typically switched to a PLL.
+ config RP2040_CLK_GPOUT0_SRC_USB
+ bool "USB (48 MHz)"
+ ---help---
+ USB reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_ADC
+ bool "ADC (48 MHz)"
+ ---help---
+ ADC reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_RTC
+ bool "RTC (46875 Hz)"
+ ---help---
+ RTC reference clock. The RTC divides this clock to generate a 1 second reference.
+endchoice
+
+config RP2040_CLK_GPOUT0_DIVINT
+ int "Divisor (Integer)"
+ depends on RP2040_CLK_GPOUT0
+ default 1
+
+config RP2040_CLK_GPOUT0_DIVFRAC
+ int "Divisor (Fractional)"
+ depends on RP2040_CLK_GPOUT0
+ default 0
+
+endif # RP2040_CLK_GPOUT0
+
+config RP2040_CLK_GPOUT1
+ bool "CLK_GPOUT1 Clock Output (pin 23)"
+ depends on RP2040_CLK_GPOUT_ENABLE
+ default n
+ ---help---
+ Enable CLK_GPOUT1
+
+if RP2040_CLK_GPOUT1
+choice
+ prompt "Source Clock"
+ depends on RP2040_CLK_GPOUT1
Review Comment:
apply the same change to 1, 2, 3
##########
arch/arm/src/rp2040/Kconfig:
##########
@@ -663,6 +663,211 @@ endif # ADC
endif # RP2040_ADC
+#####################################################################
+# CLK_GPOUT Configuration
+#####################################################################
+menu "GPIO Clock Output"
+config RP2040_CLK_GPOUT_ENABLE
+ bool "Enable Clock Outputs"
+ default n
+
+config RP2040_CLK_GPOUT0
+ bool "CLK_GPOUT0 Clock Output (pin 21)"
+ depends on RP2040_CLK_GPOUT_ENABLE
+ default n
+ ---help---
+ Enable CLK_GPOUT0
+
+if RP2040_CLK_GPOUT0
+choice
+ prompt "Source Clock"
+ depends on RP2040_CLK_GPOUT0
+
+ config RP2040_CLK_GPOUT0_SRC_REF
+ bool "REF (6 - 12 MHz)"
+ ---help---
+ Reference clock that is always running unless in DORMANT mode. Runs from
+ Ring Oscillator (ROSC) at power-up but can be switched to Crystal
+ Oscillator (XOSC) for more accuracy.
+ config RP2040_CLK_GPOUT0_SRC_SYS
+ bool "SYS (125 MHz)"
+ ---help---
+ System clock that is always running unless in DORMANT mode. Runs from
+ clk_ref at power-up but is typically switched to a PLL.
+ config RP2040_CLK_GPOUT0_SRC_USB
+ bool "USB (48 MHz)"
+ ---help---
+ USB reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_ADC
+ bool "ADC (48 MHz)"
+ ---help---
+ ADC reference clock. Must be 48MHz.
+ config RP2040_CLK_GPOUT0_SRC_RTC
+ bool "RTC (46875 Hz)"
+ ---help---
+ RTC reference clock. The RTC divides this clock to generate a 1 second reference.
+endchoice
+
+config RP2040_CLK_GPOUT0_DIVINT
+ int "Divisor (Integer)"
+ depends on RP2040_CLK_GPOUT0
Review Comment:
remove
##########
arch/arm/src/rp2040/Kconfig:
##########
@@ -663,6 +663,211 @@ endif # ADC
endif # RP2040_ADC
+#####################################################################
+# CLK_GPOUT Configuration
+#####################################################################
+menu "GPIO Clock Output"
+config RP2040_CLK_GPOUT_ENABLE
+ bool "Enable Clock Outputs"
+ default n
+
+config RP2040_CLK_GPOUT0
+ bool "CLK_GPOUT0 Clock Output (pin 21)"
+ depends on RP2040_CLK_GPOUT_ENABLE
+ default n
+ ---help---
+ Enable CLK_GPOUT0
+
+if RP2040_CLK_GPOUT0
+choice
+ prompt "Source Clock"
+ depends on RP2040_CLK_GPOUT0
Review Comment:
remove, guard by line 681
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