You are viewing a plain text version of this content. The canonical link for it is here.

Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/04/19 16:04:13 UTC

[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6101: arch/risc-v: Merge status/fpu context save/load to save_ctx/load_ctx

xiaoxiang781216 commented on code in PR #6101:
URL: https://github.com/apache/incubator-nuttx/pull/6101#discussion_r853245880


##########
arch/risc-v/src/common/riscv_exception_common.S:
##########
@@ -83,20 +83,6 @@ exception_common:
   addi       sp, sp, -XCPTCONTEXT_SIZE
   save_ctx   sp

Review Comment:
   could we define three macro: riscv_savectx, riscv_savecpu and riscv_savefpu?



-- 
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.

To unsubscribe, e-mail: commits-unsubscribe@nuttx.apache.org

For queries about this service, please contact Infrastructure at:
users@infra.apache.org