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Posted to commits@mynewt.apache.org by ma...@apache.org on 2016/02/10 19:59:41 UTC
[21/25] incubator-mynewt-larva git commit: Moving STM32F3xx support
to a separate repository.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/38e36345/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_flash.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_flash.h b/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_flash.h
deleted file mode 100644
index e086289..0000000
--- a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_flash.h
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_flash.h
- * @author MCD Application Team
- * @version V1.2.3
- * @date 10-July-2015
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_FLASH_H
-#define __STM32F30x_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup Flash_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
-#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1) || \
- ((LATENCY) == FLASH_Latency_2))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-
-#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
-#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-/**
- * @}
- */
-/** @defgroup FLASH_Address
- * @{
- */
-
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_DATA_ADDRESS
- * @{
- */
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Write_Protection
- * @{
- */
-
-#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
-#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
-#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
-#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
-#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
-#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
-#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
-#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
-#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
-#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
-#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
-#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
-#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
-#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
-#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
-#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
-#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-
-#ifdef STM32F303xE
-#define OB_WRP_Pages62to263 ((uint32_t)0x80000000) /* Write protection of page 62 to 263 */
-#else
-#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
-#endif /* STM32F303xE */
-
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_Read_Protection
- * @{
- */
-
-/**
- * @brief Read Protection Level
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0xBB)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_IWatchdog
- * @{
- */
-
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STOP
- * @{
- */
-
-#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
- * @}
- */
-
-/** @defgroup Option_Bytes_nRST_STDBY
- * @{
- */
-
-#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-/**
- * @}
- */
-/** @defgroup Option_Bytes_BOOT1
- * @{
- */
-
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-/**
- * @}
- */
-/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
- * @{
- */
-
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
- * @{
- */
-
-#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
-#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
-
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
-/**
- * @}
- */
-/** @defgroup Timeout_definition
- * @{
- */
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-/* Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_Launch(void);
-FLASH_Status FLASH_OB_Erase(void);
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-uint8_t FLASH_OB_GetUser(void);
-uint32_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-
-/* Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/38e36345/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_fmc.h
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diff --git a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_fmc.h b/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_fmc.h
deleted file mode 100644
index ad256d6..0000000
--- a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_fmc.h
+++ /dev/null
@@ -1,722 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_fmc.h
- * @author MCD Application Team
- * @version V1.2.3
- * @date 10-July-2015
- * @brief This file contains all the functions prototypes for the FMC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_FMC_H
-#define __STM32F30x_FMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 1 and 15.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 1 and 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 2 and 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 2 and 17 in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
- uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the databus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FMC_Memory_Type */
-
- uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
- uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
- uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
- uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FMC_Wrap_Mode */
-
- uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
-
- uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
-
- uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
-
- uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
-
- uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
-
- uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
-
-
- FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
-
- FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
-}FMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 255.*/
-
- uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0 and 255 */
-
- uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0 and 255 */
-
- uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- databus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0 and 255 */
-}FMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
- uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
-
- uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
-
- uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
-
- uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 255. */
-
- uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0 and 255 */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
-}FMC_NANDInitTypeDef;
-
-/**
- * @brief FMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 255. */
-
- uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0 and 255 */
-
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
-}FMC_PCCARDInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Bank
- * @{
- */
-#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
- ((BANK) == FMC_Bank1_NORSRAM2) || \
- ((BANK) == FMC_Bank1_NORSRAM3) || \
- ((BANK) == FMC_Bank1_NORSRAM4))
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Bank
- * @{
- */
-#define FMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FMC_Bank3_NAND ((uint32_t)0x00000100)
-
-#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND))
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Bank
- * @{
- */
-#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-
-/** @defgroup FMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-
-#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
- ((MUX) == FMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Memory_Type
- * @{
- */
-
-#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
-
-#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
- ((MEMORY) == FMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Data_Width
- * @{
- */
-
-#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
- ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FMC_Burst_Access_Mode
- * @{
- */
-
-#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-
-#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
- ((STATE) == FMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_AsynchronousWait
- * @{
- */
-#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-
-#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
- ((STATE) == FMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal_Polarity
- * @{
- */
-#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-
-#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wrap_Mode
- * @{
- */
-#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
-
-#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
- ((MODE) == FMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Timing
- * @{
- */
-#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Operation
- * @{
- */
-#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
-
-#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
- ((OPERATION) == FMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal
- * @{
- */
-#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
-
-#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
- ((SIGNAL) == FMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Extended_Mode
- * @{
- */
-#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
- ((MODE) == FMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Burst
- * @{
- */
-
-#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
-
-#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
- ((BURST) == FMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock
- * @{
- */
-
-#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
-#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
-
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
- ((CCLOCK) == FMC_CClock_SyncAsync))
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Setup_Time
- * @{
- */
-#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Hold_Time
- * @{
- */
-#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Setup_Time
- * @{
- */
-#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_CLK_Division
- * @{
- */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Latency
- * @{
- */
-#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FMC_Access_Mode
- * @{
- */
-#define FMC_AccessMode_A ((uint32_t)0x00000000)
-#define FMC_AccessMode_B ((uint32_t)0x10000000)
-#define FMC_AccessMode_C ((uint32_t)0x20000000)
-#define FMC_AccessMode_D ((uint32_t)0x30000000)
-
-#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
- ((MODE) == FMC_AccessMode_B) || \
- ((MODE) == FMC_AccessMode_C) || \
- ((MODE) == FMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FMC_Wait_feature
- * @{
- */
-#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
-
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
- ((FEATURE) == FMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Data_Width
- * @{
- */
-#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
-
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
- ((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC
- * @{
- */
-#define FMC_ECC_Disable ((uint32_t)0x00000000)
-#define FMC_ECC_Enable ((uint32_t)0x00000040)
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
- ((STATE) == FMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC_Page_Size
- * @{
- */
-#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_TAR_Setup_Time
- * @{
- */
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time
- * @{
- */
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Setup_Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time
- * @{
- */
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt_sources
- * @{
- */
-#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FMC_IT_Level ((uint32_t)0x00000010)
-#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
-
-#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
- ((IT) == FMC_IT_Level) || \
- ((IT) == FMC_IT_FallingEdge))
-
-#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND) || \
- ((BANK) == FMC_Bank4_PCCARD))
-/**
- * @}
- */
-
-/** @defgroup FMC_Flags
- * @{
- */
-#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FMC_FLAG_Level ((uint32_t)0x00000002)
-#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
-
-#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
- ((FLAG) == FMC_FLAG_Level) || \
- ((FLAG) == FMC_FLAG_FallingEdge) || \
- ((FLAG) == FMC_FLAG_FEMPT))
-
-#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND) || \
- ((BANK) == FMC_Bank4_PCCARD))
-
-#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
-void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
-void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
-void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FMC_NANDDeInit(uint32_t FMC_Bank);
-void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
-void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
-void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
-void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
-uint32_t FMC_GetECC(uint32_t FMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FMC_PCCARDDeInit(void);
-void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
-void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
-void FMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
-FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
-void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
-ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
-void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F30x_FMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-larva/blob/38e36345/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_gpio.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_gpio.h b/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_gpio.h
deleted file mode 100644
index feed303..0000000
--- a/hw/mcu/stm/stm32f3xx/include/mcu/stm32f30x_gpio.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f30x_gpio.h
- * @author MCD Application Team
- * @version V1.2.3
- * @date 10-July-2015
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F30x_GPIO_H
-#define __STM32F30x_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f30x.h"
-
-/** @addtogroup STM32F30x_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF) || \
- ((PERIPH) == GPIOG) || \
- ((PERIPH) == GPIOH))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC)|| \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOF))
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
- GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
- GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
- ((SPEED) == GPIO_Speed_Level_3))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternate_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
- MCO, NJTRST, TRACED, TRACECK */
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
-
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
-
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
-
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
- USART1, USART2, USART3 */
-
-/**
- * @brief AF 8 selection
- */
-#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
- COMP5_OUT, COMP6_OUT */
-
-/**
- * @brief AF 9 selection
- */
-#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
-
-/**
- * @brief AF 10 selection
- */
-#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
-
-/**
- * @brief AF 11 selection
- */
-#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
-
-/**
- * @brief AF 12 selection
- */
-#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
-
-/**
- * @brief AF 13 selection
- */
-#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
-
-/**
- * @brief AF 14 selection
- */
-#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
-
-/**
- * @brief AF 15 selection
- */
-#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
- ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
- ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
- ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
- ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
- ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
- ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
- ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Speed_Legacy
- * @{
- */
-
-#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
-#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F30x_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/