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Posted to commits@nuttx.apache.org by je...@apache.org on 2025/07/21 10:56:36 UTC
(nuttx) branch master updated: xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
This is an automated email from the ASF dual-hosted git repository.
jerpelea pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 9e53aab5b3 xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
9e53aab5b3 is described below
commit 9e53aab5b35167d7284cfcae951b8a300b7dfb06
Author: chao an <an...@bytedance.com>
AuthorDate: Sat Jul 19 15:50:50 2025 +0800
xtensa/isa: fix build break if compiler without ISA - XCHAL_HAVE_THREADPTR support
common/xtensa_context.S: Assembler messages:
common/xtensa_context.S:134: Error: invalid register number (231) for 'rur' instruction
common/xtensa_context.S:283: Error: invalid register number (231) for 'wur' instruction
clang-10: error: Xtensa-as command failed with exit code 1 (use -v to see invocation)
make[1]: *** [Makefile:143: xtensa_context.o] Error 1
make[1]: *** Waiting for unfinished jobs....
Signed-off-by: chao an <an...@bytedance.com>
---
arch/xtensa/include/irq.h | 11 +++++++++--
arch/xtensa/src/common/xtensa_context.S | 4 ++++
arch/xtensa/src/common/xtensa_saveusercontext.c | 2 ++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h
index 9bff4d0bd1..5dc3e54b6c 100644
--- a/arch/xtensa/include/irq.h
+++ b/arch/xtensa/include/irq.h
@@ -94,9 +94,16 @@
#define REG_SAR (18)
#define REG_EXCCAUSE (19)
#define REG_EXCVADDR (20)
-#define REG_THREADPTR (21)
-#define _REG_EXTRA_START (22)
+#ifdef CONFIG_SCHED_THREAD_LOCAL
+# ifndef XCHAL_HAVE_THREADPTR || XCHAL_HAVE_THREADPTR == 0
+# error architecture-specific TLS depends on ISA THREADPTR(Thread Porinter)
+# endif
+# define REG_THREADPTR (21)
+# define _REG_EXTRA_START (22)
+#else
+# define _REG_EXTRA_START (21)
+#endif
#if XCHAL_HAVE_S32C1I != 0
# define REG_SCOMPARE1 (_REG_EXTRA_START + 0)
diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S
index dd9156e3c6..01ae6618a9 100644
--- a/arch/xtensa/src/common/xtensa_context.S
+++ b/arch/xtensa/src/common/xtensa_context.S
@@ -131,8 +131,10 @@ _xtensa_context_save:
s32i a15, sp, (4 * REG_A15)
#endif
+#ifdef CONFIG_SCHED_THREAD_LOCAL
rur a3, THREADPTR
s32i a3, sp, (4 * REG_THREADPTR)
+#endif
rsr a3, SAR
s32i a3, sp, (4 * REG_SAR)
@@ -279,8 +281,10 @@ _xtensa_context_restore:
wsr a3, SCOMPARE1
#endif
+#ifdef CONFIG_SCHED_THREAD_LOCAL
l32i a3, a2, (4 * REG_THREADPTR)
wur a3, THREADPTR
+#endif
l32i a3, a2, (4 * REG_SAR)
wsr a3, SAR
diff --git a/arch/xtensa/src/common/xtensa_saveusercontext.c b/arch/xtensa/src/common/xtensa_saveusercontext.c
index e877a65c53..29842c49ae 100644
--- a/arch/xtensa/src/common/xtensa_saveusercontext.c
+++ b/arch/xtensa/src/common/xtensa_saveusercontext.c
@@ -79,8 +79,10 @@ int up_saveusercontext(void *saveregs)
" s32i a14, %0, (4 * " STRINGIFY(REG_A14) ")\n"
" s32i a15, %0, (4 * " STRINGIFY(REG_A15) ")\n"
#endif
+#ifdef CONFIG_SCHED_THREAD_LOCAL
" rur a2, THREADPTR\n"
" s32i a2, %0, (4 * " STRINGIFY(THREADPTR) ")\n"
+#endif
" rsr a2, SAR\n"
" s32i a2, %0, (4 * " STRINGIFY(REG_SAR) ")\n"
#if XCHAL_HAVE_S32C1I != 0