Re: [PR] arch/risc-v/litex: provide architecture specific perfmon bindings. [nuttx]

["g2gps (via GitHub)" <gi...@apache.org>]

g2gps commented on PR #12460:
URL: https://github.com/apache/nuttx/pull/12460#issuecomment-2342443077

   A couple of questions have come up in the details whilst revisiting this:
   
   - The `vexriscv_smp` core doesn't implement the performance counter by default. Opensbi handles this case on startup by attempting a read and trapping the exception.
   - The currently implementation could be moved to `riscv_perf.c` instead, however some risc-v ports, e.g  `esp32c3_perf` already have there own architecture specific implementation, so there would need to be some conditional logic around this.
   - Assuming the Litex architecture specific perf_xx implementation is kept, I'll need to update this to handle the standard `vexriscv` core, which only has the m-mode timer.


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