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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/06/28 13:29:38 UTC
(nuttx) branch master updated: arm64: inline up_cpu_index
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 13bbea0f1c arm64: inline up_cpu_index
13bbea0f1c is described below
commit 13bbea0f1c69f0126e47d5c8cfe93d1e1e264a8f
Author: hujun5 <hu...@xiaomi.com>
AuthorDate: Thu Dec 14 10:25:35 2023 +0800
arm64: inline up_cpu_index
reduce the time consumed by function call
test:
We can use qemu for testing.
compiling
make distclean -j20; ./tools/configure.sh -l qemu-armv8a:nsh_smp ;make -j20
running
qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline -kernel ./nuttx
Signed-off-by: hujun5 <hu...@xiaomi.com>
---
arch/arm64/include/fvp-v8r/irq.h | 3 ++-
arch/arm64/include/goldfish/irq.h | 3 ++-
arch/arm64/include/irq.h | 40 ++++++++++++++++++++++++++++-----
arch/arm64/include/qemu/irq.h | 3 ++-
arch/arm64/src/common/arm64_arch.h | 30 +------------------------
arch/arm64/src/fvp-v8r/fvp_boot.c | 31 +------------------------
arch/arm64/src/goldfish/goldfish_boot.c | 31 +------------------------
arch/arm64/src/qemu/qemu_boot.c | 31 +------------------------
8 files changed, 44 insertions(+), 128 deletions(-)
diff --git a/arch/arm64/include/fvp-v8r/irq.h b/arch/arm64/include/fvp-v8r/irq.h
index 19cc56028f..d285e695de 100644
--- a/arch/arm64/include/fvp-v8r/irq.h
+++ b/arch/arm64/include/fvp-v8r/irq.h
@@ -29,6 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define NR_IRQS 220 /* Total number of interrupts */
+#define NR_IRQS 220 /* Total number of interrupts */
+#define MPID_TO_CORE(mpid) (((mpid) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
#endif /* __ARCH_ARM64_INCLUDE_FVP_V8R_IRQ_H */
diff --git a/arch/arm64/include/goldfish/irq.h b/arch/arm64/include/goldfish/irq.h
index a7ab171d20..29b884f261 100644
--- a/arch/arm64/include/goldfish/irq.h
+++ b/arch/arm64/include/goldfish/irq.h
@@ -29,6 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define NR_IRQS 220 /* Total number of interrupts */
+#define NR_IRQS 220 /* Total number of interrupts */
+#define MPID_TO_CORE(mpid) (((mpid) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
#endif /* __ARCH_ARM64_INCLUDE_GOLDFISH_IRQ_H */
diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h
index 56ac7278a8..baa5c08ab7 100644
--- a/arch/arm64/include/irq.h
+++ b/arch/arm64/include/irq.h
@@ -44,15 +44,43 @@
#include <arch/chip/irq.h>
-#ifndef __ASSEMBLY__
-# include <stdint.h>
-#endif
-
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
-#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+#define up_getsp() (uintptr_t)__builtin_frame_address(0)
+
+/* MPIDR_EL1, Multiprocessor Affinity Register */
+
+#define MPIDR_AFFLVL_MASK (0xff)
+
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF1_SHIFT (8)
+#define MPIDR_AFF2_SHIFT (16)
+#define MPIDR_AFF3_SHIFT (32)
+
+/* mpidr_el1 register, the register is define:
+ * - bit 0~7: Aff0
+ * - bit 8~15: Aff1
+ * - bit 16~23: Aff2
+ * - bit 24: MT, multithreading
+ * - bit 25~29: RES0
+ * - bit 30: U, multiprocessor/Uniprocessor
+ * - bit 31: RES1
+ * - bit 32~39: Aff3
+ * - bit 40~63: RES0
+ * Different ARM64 Core will use different Affn define, the mpidr_el1
+ * value is not CPU number, So we need to change CPU number to mpid
+ * and vice versa
+ */
+
+#define GET_MPIDR() \
+ ({ \
+ uint64_t __val; \
+ __asm__ volatile ("mrs %0, mpidr_el1" \
+ : "=r" (__val) :: "memory"); \
+ __val; \
+ })
/****************************************************************************
* Exception stack frame format:
@@ -376,7 +404,7 @@ static inline void up_irq_restore(irqstate_t flags)
****************************************************************************/
#ifdef CONFIG_SMP
-int up_cpu_index(void);
+# define up_cpu_index() ((int)MPID_TO_CORE(GET_MPIDR()))
#else
# define up_cpu_index() (0)
#endif
diff --git a/arch/arm64/include/qemu/irq.h b/arch/arm64/include/qemu/irq.h
index cbff0135ce..0937a49502 100644
--- a/arch/arm64/include/qemu/irq.h
+++ b/arch/arm64/include/qemu/irq.h
@@ -29,6 +29,7 @@
* Pre-processor Definitions
****************************************************************************/
-#define NR_IRQS 220 /* Total number of interrupts */
+#define NR_IRQS 220 /* Total number of interrupts */
+#define MPID_TO_CORE(mpid) (((mpid) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
#endif /* __ARCH_ARM64_INCLUDE_QEMU_IRQ_H */
diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h
index d329365303..facf2da475 100644
--- a/arch/arm64/src/common/arm64_arch.h
+++ b/arch/arm64/src/common/arm64_arch.h
@@ -148,39 +148,11 @@
#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
-/* MPIDR_EL1, Multiprocessor Affinity Register */
-
-#define MPIDR_AFFLVL_MASK (0xff)
-#define MPIDR_ID_MASK (0xff00ffffff)
-
-#define MPIDR_AFF0_SHIFT (0)
-#define MPIDR_AFF1_SHIFT (8)
-#define MPIDR_AFF2_SHIFT (16)
-#define MPIDR_AFF3_SHIFT (32)
-
-/* mpidr_el1 register, the register is define:
- * - bit 0~7: Aff0
- * - bit 8~15: Aff1
- * - bit 16~23: Aff2
- * - bit 24: MT, multithreading
- * - bit 25~29: RES0
- * - bit 30: U, multiprocessor/Uniprocessor
- * - bit 31: RES1
- * - bit 32~39: Aff3
- * - bit 40~63: RES0
- * Different ARM64 Core will use different Affn define, the mpidr_el1
- * value is not CPU number, So we need to change CPU number to mpid
- * and vice versa
- */
-
-#define GET_MPIDR() read_sysreg(mpidr_el1)
+#define MPIDR_ID_MASK (0xff00ffffff)
#define MPIDR_AFFLVL(mpidr, aff_level) \
(((mpidr) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
-#define MPID_TO_CORE(mpid, aff_level) \
- (((mpid) >> MPIDR_AFF ## aff_level ## _SHIFT) & MPIDR_AFFLVL_MASK)
-
#define CORE_TO_MPID(core, aff_level) \
({ \
uint64_t __mpidr = GET_MPIDR(); \
diff --git a/arch/arm64/src/fvp-v8r/fvp_boot.c b/arch/arm64/src/fvp-v8r/fvp_boot.c
index 6017a28fca..3cd7ca0499 100644
--- a/arch/arm64/src/fvp-v8r/fvp_boot.c
+++ b/arch/arm64/src/fvp-v8r/fvp_boot.c
@@ -120,35 +120,6 @@ void arm64_el_init(void)
* Public Functions
****************************************************************************/
-/****************************************************************************
- * Name: up_cpu_index
- *
- * Description:
- * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- * If TLS is enabled, then the RTOS can get this information from the TLS
- * info structure. Otherwise, the MCU-specific logic must provide some
- * mechanism to provide the CPU index.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- ****************************************************************************/
-
-int up_cpu_index(void)
-{
- /* Read the Multiprocessor Affinity Register (MPIDR)
- * And return the CPU ID field
- */
-
- return MPID_TO_CORE(GET_MPIDR(), 0);
-}
-
/****************************************************************************
* Name: arm64_get_mpid
*
@@ -175,7 +146,7 @@ uint64_t arm64_get_mpid(int cpu)
int arm64_get_cpuid(uint64_t mpid)
{
- return MPID_TO_CORE(mpid, 0);
+ return MPID_TO_CORE(mpid);
}
#endif /* CONFIG_SMP */
diff --git a/arch/arm64/src/goldfish/goldfish_boot.c b/arch/arm64/src/goldfish/goldfish_boot.c
index d9ed9be9f0..f9674b1e69 100644
--- a/arch/arm64/src/goldfish/goldfish_boot.c
+++ b/arch/arm64/src/goldfish/goldfish_boot.c
@@ -84,35 +84,6 @@ const struct arm_mmu_config g_mmu_config =
* Public Functions
****************************************************************************/
-/****************************************************************************
- * Name: up_cpu_index
- *
- * Description:
- * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- * If TLS is enabled, then the RTOS can get this information from the TLS
- * info structure. Otherwise, the MCU-specific logic must provide some
- * mechanism to provide the CPU index.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- ****************************************************************************/
-
-int up_cpu_index(void)
-{
- /* Read the Multiprocessor Affinity Register (MPIDR)
- * And return the CPU ID field
- */
-
- return MPID_TO_CORE(GET_MPIDR(), 0);
-}
-
/****************************************************************************
* Name: arm64_get_mpid
*
@@ -139,7 +110,7 @@ uint64_t arm64_get_mpid(int cpu)
int arm64_get_cpuid(uint64_t mpid)
{
- return MPID_TO_CORE(mpid, 0);
+ return MPID_TO_CORE(mpid);
}
#endif /* CONFIG_SMP */
diff --git a/arch/arm64/src/qemu/qemu_boot.c b/arch/arm64/src/qemu/qemu_boot.c
index 38a39a0632..364f93d2c3 100644
--- a/arch/arm64/src/qemu/qemu_boot.c
+++ b/arch/arm64/src/qemu/qemu_boot.c
@@ -80,35 +80,6 @@ const struct arm_mmu_config g_mmu_config =
* Public Functions
****************************************************************************/
-/****************************************************************************
- * Name: up_cpu_index
- *
- * Description:
- * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- * If TLS is enabled, then the RTOS can get this information from the TLS
- * info structure. Otherwise, the MCU-specific logic must provide some
- * mechanism to provide the CPU index.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
- * corresponds to the currently executing CPU.
- *
- ****************************************************************************/
-
-int up_cpu_index(void)
-{
- /* Read the Multiprocessor Affinity Register (MPIDR)
- * And return the CPU ID field
- */
-
- return MPID_TO_CORE(GET_MPIDR(), 0);
-}
-
/****************************************************************************
* Name: arm64_get_mpid
*
@@ -135,7 +106,7 @@ uint64_t arm64_get_mpid(int cpu)
int arm64_get_cpuid(uint64_t mpid)
{
- return MPID_TO_CORE(mpid, 0);
+ return MPID_TO_CORE(mpid);
}
#endif /* CONFIG_SMP */