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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2019/01/04 16:40:01 UTC
[GitHub] mlaz closed pull request #1540: Update nrfx to release 1.4.0
mlaz closed pull request #1540: Update nrfx to release 1.4.0
URL: https://github.com/apache/mynewt-core/pull/1540
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diff --git a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
index fe4f2b97a9..71c0dd2319 100644
--- a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
+++ b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
@@ -1,6 +1,76 @@
# Changelog
All notable changes to this project are documented in this file.
+## [1.4.0] - 2018-11-30
+### Added
+- Added the nrfx_is_word_aligned() function for checking whether an address is word-aligned.
+- Added HAL for ACL.
+- Added functions for disabling and re-enabling interrupts in the SWI driver.
+- Added possibility to completely remove interrupt handling from the WDT driver.
+
+### Changed
+- Updated the documentation for the nrfx_uarte_rx() function. It now correctly reflects the actual behavior of the function.
+
+### Fixed
+- Corrected the type of the nrfx_uarte_xfer_evt_t structure field that holds the amount of transferred bytes.
+- Corrected the way of disabling interrupts in the NFCT driver when moving the peripheral to the disabled state.
+- Fixed a typo in the name of the bmRequest field in the nrfx_usbd_setup_t structure. The new correct name is bRequest.
+- Fixed the nrfx_ppi_channel_fork_assign() function. It now accepts also pre-programmed channels.
+- Fixed handling of long custom instruction responses in the QSPI driver.
+- Fixed a bug affecting the conversion of time to ticks in the TIMER HAL.
+
+## [1.3.1] - 2018-09-28
+### Fixed
+- Corrected the type of nrfx_usbd_ep_status_get() return value.
+- Corrected calls to undefined macros in NFCT and USBD drivers.
+
+## [1.3.0] - 2018-09-21
+### Added
+- Added HAL and driver for NFCT.
+- Added driver for USBD.
+- Added function for setting the burst mode in the SAADC HAL.
+- Added the NRFX_ARRAY_SIZE macro.
+
+### Changed
+- Moved the implementation of nrfx_power_clock_irq_handler() to nrfx_power.c, removed nrfx_power_clock.c.
+
+### Fixed
+- Replaced ARRAY_SIZE macro calls with NRFX_ARRAY_SIZE ones.
+
+## [1.2.0] - 2018-09-06
+### Added
+- Added function for checking if a specific channel is enabled in the GPIOTE HAL.
+- Added support for using the QDEC driver without LED.
+- Added functions for modifying only the event endpoint or only the task endpoint in the PPI HAL.
+- Added function for reading the pin pull configuration in the GPIO HAL.
+
+### Changed
+- Corrected ISOSPLIT enumerator names in the USBD HAL.
+
+### Fixed
+- Fixed a double buffering bug that occurred in the UARTE driver after the RX abort.
+- Fixed the TXRX transfers in the TWIM driver. They can now be started after transfers that are not ended with the stop condition.
+
+## [1.1.0] - 2018-06-15
+### Added
+- Implemented workaround for nRF52832 and nRF52840 anomaly 194 in the I2S driver.
+- Implemented workaround for nRF52840 anomaly 195 in the SPIM driver.
+- Added HALs for CCM, ECB, and RADIO.
+- Extended HALs for GPIO, PPI, SAADC, and USBD.
+- Added support for external LFCLK sources.
+
+### Changed
+- Corrected handling of transfer lengths in the TWI driver.
+- Updated MDK to version 8.17.0.
+
+### Fixed
+- Fixed logging in the PPI driver.
+- Fixed SPIM interrupt definition for nRF52810.
+- Fixed Slave Select configuration in the SPIM driver.
+- Corrected default settings for NRF_SPIM3.
+- Fixed a typo in the UARTE TXDRDY event definition.
+- Corrected the TIMEOUT event clearing in the WDT interrupt handler.
+
## [1.0.0] - 2018-03-21
### Added
- Added the NRFX_WAIT_FOR macro to improve the time-out functionality in QSPI and SAADC drivers.
@@ -17,7 +87,7 @@ All notable changes to this project are documented in this file.
- Changed the RNG bias correction configuration option to be enabled by default.
- Refactored the ADC driver and HAL.
- Corrected assertions in the TIMER driver to make it usable in debug version with PPI.
-- Improved buffer handling in the I2S driver. The API of the driver has been sligthly modified.
+- Improved buffer handling in the I2S driver. The API of the driver has been slightly modified.
- Enhanced SPIS driver API: added the "p_context" parameter, allowed NULL pointers for zero-length buffers.
### Fixed
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
index f1f593048f..229f88b8e5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrf_bitmask.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
index dbb7293042..a2361fd82d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_adc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -164,6 +164,9 @@ void nrfx_adc_uninit(void);
* This function configures and enables the channel. When @ref nrfx_adc_buffer_convert is
* called, all channels that have been enabled with this function are sampled.
*
+ * This function can be called only when there is no conversion in progress
+ * (the ADC is not busy).
+ *
* @note The channel instance variable @p p_channel is used by the driver as an item
* in a list. Therefore, it cannot be an automatic variable that is located on the stack.
*/
@@ -171,9 +174,20 @@ void nrfx_adc_channel_enable(nrfx_adc_channel_t * const p_channel);
/**
* @brief Function for disabling an ADC channel.
+ *
+ * This function can be called only when there is no conversion in progress
+ * (the ADC is not busy).
*/
void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel);
+/**
+ * @brief Function for disabling all ADC channels.
+ *
+ * This function can be called only when there is no conversion in progress
+ * (the ADC is not busy).
+ */
+void nrfx_adc_all_channels_disable(void);
+
/**
* @brief Function for starting ADC sampling.
*
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
index 27cd4236a8..151d70f089 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
index e337429df5..f7a5c13c6e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_comp.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
index 24e9eed905..c0b1886ccd 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_gpiote.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
index f7766a6150..ea4e4d0b30 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_i2s.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
index 6acecc0c82..fada3ae50c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_lpcomp.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
new file mode 100644
index 0000000000..ceb5a340b7
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_NFCT_H__
+#define NRFX_NFCT_H__
+
+#include <nrfx.h>
+#include <hal/nrf_nfct.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_nfct NFCT driver
+ * @{
+ * @ingroup nrf_nfct
+ * @brief Near Field Communication Tag (NFCT) peripheral driver.
+ */
+
+#define NRFX_NFCT_NFCID1_SINGLE_SIZE 4u ///< Length of single-size NFCID1.
+#define NRFX_NFCT_NFCID1_DOUBLE_SIZE 7u ///< Length of double-size NFCID1.
+#define NRFX_NFCT_NFCID1_TRIPLE_SIZE 10u ///< Length of triple-size NFCID1.
+
+#define NRFX_NFCT_NFCID1_DEFAULT_LEN NRFX_NFCT_NFCID1_DOUBLE_SIZE ///< Default length of NFC ID. */
+
+/**
+ * @brief NFCT hardware states.
+ */
+typedef enum
+{
+ NRFX_NFCT_STATE_DISABLED = NRF_NFCT_TASK_DISABLE, ///< NFC Tag is disabled (no sensing of an external NFC field).
+ NRFX_NFCT_STATE_SENSING = NRF_NFCT_TASK_SENSE, ///< NFC Tag is sensing whether there is an external NFC field.
+ NRFX_NFCT_STATE_ACTIVATED = NRF_NFCT_TASK_ACTIVATE, ///< NFC Tag is powered-up (see @ref nrfx_nfct_active_state_t for possible substates).
+} nrfx_nfct_state_t;
+
+/**
+ * @brief NFC tag states, when NFCT hardware is activated.
+ *
+ * @details These states are substates of the @ref NRFX_NFCT_STATE_ACTIVATED state.
+ */
+typedef enum
+{
+ NRFX_NFCT_ACTIVE_STATE_IDLE = NRF_NFCT_TASK_GOIDLE, ///< NFC Tag is activated and idle (not selected by a reader).
+ NRFX_NFCT_ACTIVE_STATE_SLEEP = NRF_NFCT_TASK_GOSLEEP, ///< NFC Tag is sleeping.
+ NRFX_NFCT_ACTIVE_STATE_DEFAULT, ///< NFC Tag is either sleeping or idle, depending on the previous state before being selected by a poller.
+} nrfx_nfct_active_state_t;
+
+/**
+ * @brief NFCT driver event types, passed to the upper-layer callback function
+ * provided during the initialization.
+ */
+typedef enum
+{
+ NRFX_NFCT_EVT_FIELD_DETECTED = NRF_NFCT_INT_FIELDDETECTED_MASK, ///< External NFC field is detected.
+ NRFX_NFCT_EVT_FIELD_LOST = NRF_NFCT_INT_FIELDLOST_MASK, ///< External NFC Field is lost.
+ NRFX_NFCT_EVT_SELECTED = NRF_NFCT_INT_SELECTED_MASK, ///< Tag was selected by the poller.
+ NRFX_NFCT_EVT_RX_FRAMESTART = NRF_NFCT_INT_RXFRAMESTART_MASK, ///< Data frame reception started.
+ NRFX_NFCT_EVT_RX_FRAMEEND = NRF_NFCT_INT_RXFRAMEEND_MASK, ///< Data frame is received.
+ NRFX_NFCT_EVT_TX_FRAMESTART = NRF_NFCT_INT_TXFRAMESTART_MASK, ///< Data frame transmission started.
+ NRFX_NFCT_EVT_TX_FRAMEEND = NRF_NFCT_INT_TXFRAMEEND_MASK, ///< Data frame is transmitted.
+ NRFX_NFCT_EVT_ERROR = NRF_NFCT_INT_ERROR_MASK, ///< Error occurred in an NFC communication.
+} nrfx_nfct_evt_id_t;
+
+/**
+ * @brief NFCT timing-related error types.
+ */
+typedef enum
+{
+ NRFX_NFCT_ERROR_FRAMEDELAYTIMEOUT, ///< No response frame was transmitted to the poller in the transmit window.
+ NRFX_NFCT_ERROR_NUM, ///< Total number of possible errors.
+} nrfx_nfct_error_t;
+
+/**
+ * @brief NFCT driver parameter types.
+ */
+typedef enum
+{
+ NRFX_NFCT_PARAM_ID_FDT, ///< NFC-A Frame Delay Time parameter.
+ NRFX_NFCT_PARAM_ID_SEL_RES, ///< Value of the 'Protocol' field in the NFC-A SEL_RES frame.
+ NRFX_NFCT_PARAM_ID_NFCID1, ///< NFC-A NFCID1 setting (NFC tag identifier).
+} nrfx_nfct_param_id_t;
+
+/**
+ * @brief NFCID1 descriptor.
+ */
+typedef struct
+{
+ uint8_t const * p_id; ///< NFCID1 data.
+ uint8_t id_size; ///< NFCID1 size.
+} nrfx_nfct_nfcid1_t;
+
+/**
+ * @brief NFCT driver parameter descriptor.
+ */
+typedef struct
+{
+ nrfx_nfct_param_id_t id; ///< Type of parameter.
+ union
+ {
+ uint32_t fdt; ///< NFC-A Frame Delay Time. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_FDT.
+ uint8_t sel_res_protocol; ///< NFC-A value of the 'Protocol' field in the SEL_RES frame. Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_SEL_RES.
+ nrfx_nfct_nfcid1_t nfcid1; ///< NFC-A NFCID1 value (tag identifier). Filled when nrfx_nfct_param_t::id is @ref NRFX_NFCT_PARAM_ID_NFCID1.
+ } data;
+} nrfx_nfct_param_t;
+
+/**
+ * @brief NFCT driver RX/TX buffer descriptor.
+ */
+typedef struct
+{
+ uint32_t data_size; ///< RX/TX buffer size.
+ uint8_t const * p_data; ///< RX/TX buffer.
+} nrfx_nfct_data_desc_t;
+
+/**
+ * @brief Structure used to describe the @ref NRFX_NFCT_EVT_RX_FRAMEEND event type.
+ */
+typedef struct
+{
+ uint32_t rx_status; ///< RX error status.
+ nrfx_nfct_data_desc_t rx_data; ///< RX buffer.
+} nrfx_nfct_evt_rx_frameend_t;
+
+/**
+ * @brief Structure used to describe the @ref NRFX_NFCT_EVT_TX_FRAMESTART event type.
+ */
+typedef struct
+{
+ nrfx_nfct_data_desc_t tx_data; ///< TX buffer.
+} nrfx_nfct_evt_tx_framestart_t;
+
+/**
+ * @brief Structure used to describe the @ref NRFX_NFCT_EVT_ERROR event type.
+ */
+typedef struct
+{
+ nrfx_nfct_error_t reason; ///< Reason for error.
+} nrfx_nfct_evt_error_t;
+
+/**
+ * @brief NFCT driver event.
+ */
+typedef struct
+{
+ nrfx_nfct_evt_id_t evt_id; ///< Type of event.
+ union
+ {
+ nrfx_nfct_evt_rx_frameend_t rx_frameend; ///< End of the RX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_RX_FRAMEEND.
+ nrfx_nfct_evt_tx_framestart_t tx_framestart; ///< Start of the TX frame data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_TX_FRAMESTART.
+ nrfx_nfct_evt_error_t error; ///< Error data. Filled when nrfx_nfct_evt_t::evt_id is @ref NRFX_NFCT_EVT_ERROR.
+ } params;
+} nrfx_nfct_evt_t;
+
+/**
+ * @brief Callback descriptor to pass events from the NFCT driver to the upper layer.
+ *
+ * @param[in] p_event Pointer to the event descriptor.
+ */
+typedef void (*nrfx_nfct_handler_t)(nrfx_nfct_evt_t const * p_event);
+
+/**
+ * @brief NFCT driver configuration structure.
+ */
+typedef struct
+{
+ uint32_t rxtx_int_mask; ///< Mask for enabling RX/TX events. Indicate which events must be forwarded to the upper layer by using @ref nrfx_nfct_evt_id_t. By default, no events are enabled. */
+ nrfx_nfct_handler_t cb; ///< Callback.
+} nrfx_nfct_config_t;
+
+/**
+ * @brief Function for initializing the NFCT driver.
+ *
+ * @param[in] p_config Pointer to the NFCT driver configuration structure.
+ *
+ * @retval NRFX_SUCCESS If the NFCT driver was initialized successfully.
+ * @retval NRFX_ERROR_INVALID_STATE If the NFCT driver is already initialized.
+ */
+nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config);
+
+/**
+ * @brief Function for uninitializing the NFCT driver.
+ *
+ * After uninitialization, the instance is in disabled state.
+ */
+void nrfx_nfct_uninit(void);
+
+/**
+ * @brief Function for starting the NFC subsystem.
+ *
+ * After this function completes, NFC readers are able to detect the tag.
+ */
+void nrfx_nfct_enable(void);
+
+/**
+ * @brief Function for disabling the NFCT driver.
+ *
+ * After this function returns, NFC readers are no longer able to connect
+ * to the tag.
+ */
+void nrfx_nfct_disable(void);
+
+/**
+ * @brief Function for checking whether the external NFC field is present in the range of the tag.
+ *
+ * @retval true If the NFC field is present.
+ * @retval false If no NFC field is present.
+ */
+bool nrfx_nfct_field_check(void);
+
+/**
+ * @brief Function for preparing the NFCT driver for receiving an NFC frame.
+ *
+ * @param[in] p_rx_data Pointer to the RX buffer.
+ */
+void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data);
+
+/**
+ * @brief Function for transmitting an NFC frame.
+ *
+ * @param[in] p_tx_data Pointer to the TX buffer.
+ * @param[in] delay_mode Delay mode of the NFCT frame timer.
+ *
+ * @retval NRFX_SUCCESS If the operation was successful.
+ * @retval NRFX_ERROR_INVALID_LENGTH If the TX buffer size is invalid.
+ */
+nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
+ nrf_nfct_frame_delay_mode_t delay_mode);
+
+/**
+ * @brief Function for moving the NFCT to a new state.
+ *
+ * @note The HFCLK must be running before activating the NFCT with
+ * @ref NRFX_NFCT_STATE_ACTIVATED.
+ *
+ * @param[in] state The required state.
+ */
+void nrfx_nfct_state_force(nrfx_nfct_state_t state);
+
+/**
+ * @brief Function for moving the NFCT to a new initial substate within @ref NRFX_NFCT_STATE_ACTIVATED.
+ *
+ * @param[in] sub_state The required substate.
+ */
+void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state);
+
+/**
+ * @brief Function for setting the NFC communication parameter.
+ *
+ * @note Parameter validation for length and acceptable values.
+ *
+ * @param[in] p_param Pointer to parameter descriptor.
+ *
+ * @retval NRFX_SUCCESS If the operation was successful.
+ * @retval NRFX_ERROR_INVALID_PARAM If the parameter data is invalid.
+ */
+nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
+
+/**
+ * @brief Function for getting default bytes for NFCID1.
+ *
+ * @param[in,out] p_nfcid1_buff In: empty buffer for data;
+ * Out: buffer with the NFCID1 default data. These values
+ * can be used to fill the Type 2 Tag Internal Bytes.
+ * @param[in] nfcid1_buff_len Length of the NFCID1 buffer.
+ *
+ * @retval NRFX_SUCCESS If the operation was successful.
+ * @retval NRFX_ERROR_INVALID_LENGTH If length of the NFCID buffer is different than
+ * @ref NRFX_NFCT_NFCID1_SINGLE_SIZE,
+ * @ref NRFX_NFCT_NFCID1_DOUBLE_SIZE, or
+ * @ref NRFX_NFCT_NFCID1_TRIPLE_SIZE.
+ */
+nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
+ uint32_t nfcid1_buff_len);
+
+/**
+ * @brief Function for enabling the automatic collision resolution.
+ *
+ * @details As defined by the NFC Forum Digital Protocol Technical Specification (and ISO 14443-3),
+ * the automatic collision resolution is implemented in the NFCT hardware.
+ * This function allows enabling and disabling this feature.
+ */
+void nrfx_nfct_autocolres_enable(void);
+
+/**
+ * @brief Function for disabling the automatic collision resolution.
+ *
+ * @details See also details in @ref nrfx_nfct_autocolres_enable.
+ */
+void nrfx_nfct_autocolres_disable(void);
+
+
+void nrfx_nfct_irq_handler(void);
+
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/**
+ * @defgroup nrfx_nfct_fixes NFCT driver fixes and workarounds
+ * @{
+ * @ingroup nrf_nfct
+ * @brief Fixes for hardware-related anomalies.
+ *
+ * If you are using the nRF52832 chip, the workarounds for the following anomalies are applied:
+ * - 79. NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost.
+ * - 116. NFCT does not release HFCLK when switching from ACTIVATED to SENSE mode.
+ * To implement the first workaround, an instance of NRF_TIMER is used. After the NFC field is detected,
+ * the timing module periodically polls its state to determine when the field is turned off.
+ * To implement the second workaround, power reset is used to release the clock acquired by NFCT
+ * after the field is turned off. Note that the NFCT register configuration is restored to defaults.
+ *
+ * If you are using the nRF52840 chip, rev. Engineering A, the workarounds for the following anomalies
+ * are applied:
+ * - 98. NFCT: The NFCT is not able to communicate with the peer.
+ * - 116. NFCT does not release HFCLK when switching from ACTIVATED to SENSE mode.
+ * - 144. NFCT: Not optimal NFC performance
+ *
+ * If you are using the nRF52840 chip, rev. 1, or rev. Engineering B or C, the workarounds for the following
+ * anomalies are applied:
+ * - 190. NFCT: Event FIELDDETECTED can be generated too early.
+ * To implement this workaround, an instance of NRF_TIMER is used. After the NFC field is detected,
+ * the timing module measures the necessary waiting period after which NFCT can be activated.
+ * This debouncing technique is used to filter possible field instabilities.
+ *
+ * The application of the implemented workarounds for the nRF52840 chip is determined at runtime and depends
+ * on the chip variant.
+ *
+ * The current code contains a patch for the anomaly 25 (NFCT: Reset value of
+ * SENSRES register is incorrect), so that the module now works on Windows Phone.
+ * @}
+ */
+
+#endif // NRFX_NFCT_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
index a0cdda1a9a..49d5dbf7cc 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pdm.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
index 34f15f332c..a587630928 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
index cc3a594328..3615f89885 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_power_clock.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
index 69b4d7707a..193148ebff 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_ppi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
index d65dbb4f65..6e72486be0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_pwm.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
index 7d6bdfb9a6..c8b3f6447e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qdec.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
index 9259441b8e..8e2de16930 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_qspi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
index 56ec5f75b8..2188b10dd0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rng.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
index 8e84051c3e..1cc9eedafa 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_rtc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
index df5f3eaac5..db5687505e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_saadc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
index cacf1ad692..929a267ac5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
index f9763dfa93..cc94991459 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -132,8 +132,8 @@ typedef struct
*/
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \
.dcx_pin = NRFX_SPIM_PIN_NOT_USED, \
- .rx_delay = 0x00, \
- .ss_duration = 0x00, \
+ .rx_delay = 0x02, \
+ .ss_duration = 0x02, \
.use_hw_ss = false,
#else
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
index 5ea0699302..6783674988 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spis.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_swi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_swi.h
index 7c297fe420..37583e2945 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_swi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_swi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
index b6c42f6c8d..9e9678c543 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_systick.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
index 2fbfc569d7..b6c648af55 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_timer.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
index ab68c6d6ae..f7e2dff4f8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
index 211a669434..93dd09006f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twim.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
index a424a1e98f..049a37c7d6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_twis.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
index 3af649b5fe..53bd7a4fa4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uart.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
index 4ce3ae7d72..00ba08abca 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h
new file mode 100644
index 0000000000..d60b5335b0
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_usbd.h
@@ -0,0 +1,863 @@
+/*
+ * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_USBD_H__
+#define NRFX_USBD_H__
+
+#include <nrfx.h>
+#include <hal/nrf_usbd.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_usbd USBD driver
+ * @{
+ * @ingroup nrf_usbd
+ * @brief Universal Serial Bus Device (USBD) peripheral driver.
+ */
+
+/**
+ * @brief Number of bytes in the endpoint.
+ */
+#define NRFX_USBD_EPSIZE 64
+
+/**
+ * @brief Number of bytes for isochronous endpoints.
+ *
+ * Number of bytes for isochronous endpoints in total.
+ * This number would be shared between IN and OUT endpoint.
+ * It may be also assigned totaly to one endpoint.
+ * @sa nrf_usbd_isosplit_set
+ * @sa nrf_usbd_isosplit_get
+ */
+#define NRFX_USBD_ISOSIZE 1024
+
+/**
+ * @brief The size of internal feeder buffer.
+ *
+ * @sa nrfx_usbd_feeder_buffer_get
+ */
+#define NRFX_USBD_FEEDER_BUFFER_SIZE NRFX_USBD_EPSIZE
+
+/**
+ * @name Macros for creating endpoint identifiers.
+ *
+ * Auxiliary macros for creating endpoint identifiers compatible with the USB specification.
+ * @{
+ * @brief Create identifier for IN endpoint.
+ *
+ * Simple macro to create IN endpoint identifier for given endpoint number.
+ *
+ * @param[in] n Endpoint number.
+ *
+ * @return Endpoint identifier that connects endpoint number and endpoint direction.
+ */
+#define NRFX_USBD_EPIN(n) ((nrfx_usbd_ep_t)NRF_USBD_EPIN(n))
+/**
+ * @brief Create identifier for OUT endpoint.
+ *
+ * Simple macro to create OUT endpoint identifier for given endpoint number.
+ *
+ * @param[in] n Endpoint number.
+ *
+ * @return Endpoint identifier that connects endpoint number and endpoint direction.
+ */
+#define NRFX_USBD_EPOUT(n) ((nrfx_usbd_ep_t)NRF_USBD_EPOUT(n))
+/** @} */
+
+/**
+ * @brief Endpoint identifier.
+ *
+ * Endpoint identifier used in the driver.
+ * This endpoint number is consistent with USB 2.0 specification.
+ */
+typedef enum
+{
+ NRFX_USBD_EPOUT0 = NRF_USBD_EPOUT(0), /**< Endpoint OUT 0 */
+ NRFX_USBD_EPOUT1 = NRF_USBD_EPOUT(1), /**< Endpoint OUT 1 */
+ NRFX_USBD_EPOUT2 = NRF_USBD_EPOUT(2), /**< Endpoint OUT 2 */
+ NRFX_USBD_EPOUT3 = NRF_USBD_EPOUT(3), /**< Endpoint OUT 3 */
+ NRFX_USBD_EPOUT4 = NRF_USBD_EPOUT(4), /**< Endpoint OUT 4 */
+ NRFX_USBD_EPOUT5 = NRF_USBD_EPOUT(5), /**< Endpoint OUT 5 */
+ NRFX_USBD_EPOUT6 = NRF_USBD_EPOUT(6), /**< Endpoint OUT 6 */
+ NRFX_USBD_EPOUT7 = NRF_USBD_EPOUT(7), /**< Endpoint OUT 7 */
+ NRFX_USBD_EPOUT8 = NRF_USBD_EPOUT(8), /**< Endpoint OUT 8 */
+
+ NRFX_USBD_EPIN0 = NRF_USBD_EPIN(0), /**< Endpoint IN 0 */
+ NRFX_USBD_EPIN1 = NRF_USBD_EPIN(1), /**< Endpoint IN 1 */
+ NRFX_USBD_EPIN2 = NRF_USBD_EPIN(2), /**< Endpoint IN 2 */
+ NRFX_USBD_EPIN3 = NRF_USBD_EPIN(3), /**< Endpoint IN 3 */
+ NRFX_USBD_EPIN4 = NRF_USBD_EPIN(4), /**< Endpoint IN 4 */
+ NRFX_USBD_EPIN5 = NRF_USBD_EPIN(5), /**< Endpoint IN 5 */
+ NRFX_USBD_EPIN6 = NRF_USBD_EPIN(6), /**< Endpoint IN 6 */
+ NRFX_USBD_EPIN7 = NRF_USBD_EPIN(7), /**< Endpoint IN 7 */
+ NRFX_USBD_EPIN8 = NRF_USBD_EPIN(8), /**< Endpoint IN 8 */
+} nrfx_usbd_ep_t;
+
+/**
+ * @brief Events generated by the driver.
+ *
+ * Enumeration of possible events that may be generated by the driver.
+ */
+typedef enum
+{
+ NRFX_USBD_EVT_SOF, /**< Start Of Frame event on USB bus detected. */
+ NRFX_USBD_EVT_RESET, /**< Reset condition on USB bus detected. */
+ NRFX_USBD_EVT_SUSPEND, /**< This device should go to suspend mode now. */
+ NRFX_USBD_EVT_RESUME, /**< This device should resume from suspend now. */
+ NRFX_USBD_EVT_WUREQ, /**< Wakeup request - the USBD peripheral is ready to generate
+ WAKEUP signal after exiting low power mode. */
+ NRFX_USBD_EVT_SETUP, /**< Setup frame received and decoded. */
+ NRFX_USBD_EVT_EPTRANSFER, /**< For Rx (OUT: Host->Device):
+ * 1. The packet has been received but there is no buffer prepared for transfer already.
+ * 2. Whole transfer has been finished.
+ *
+ * For Tx (IN: Device->Host):
+ * The last packet from requested transfer has been transfered over USB bus and acknowledged.
+ */
+ NRFX_USBD_EVT_CNT /**< Number of defined events. */
+} nrfx_usbd_event_type_t;
+
+/**
+ * @brief Endpoint status codes.
+ *
+ * Status codes that may be returned by @ref nrfx_usbd_ep_status_get or, except for
+ * @ref NRFX_USBD_EP_BUSY, reported together with @ref NRFX_USBD_EVT_EPTRANSFER.
+ */
+typedef enum
+{
+ NRFX_USBD_EP_OK, /**< No error occured. */
+ NRFX_USBD_EP_WAITING, /**< Data received, no buffer prepared already - waiting for configured transfer. */
+ NRFX_USBD_EP_OVERLOAD, /**< Received number of bytes cannot fit given buffer.
+ * This error would also be returned when next_transfer function has been defined
+ * but currently received data cannot fit completely in current buffer.
+ * No data split from single endpoint transmission is supported.
+ *
+ * When this error is reported - data is left inside endpoint buffer.
+ * Clear endpoint or prepare new buffer and read it.
+ */
+ NRFX_USBD_EP_ABORTED, /**< EP0 transfer can be aborted when new setup comes.
+ * Any other transfer can be aborted by USB reset or driver stopping.
+ */
+ NRFX_USBD_EP_BUSY, /**< A transfer is in progress. */
+} nrfx_usbd_ep_status_t;
+
+/**
+ * @brief Event structure.
+ *
+ * Structure passed to event handler.
+ */
+typedef struct
+{
+ nrfx_usbd_event_type_t type;
+ union
+ {
+ struct {
+ uint16_t framecnt; /**< Current value of frame counter. */
+ } sof; /**< Data available for @ref NRFX_USBD_EVT_SOF. */
+ struct {
+ nrfx_usbd_ep_t ep; /**< Endpoint number. */
+ } isocrc;
+ struct {
+ nrfx_usbd_ep_t ep; /**< Endpoint number. */
+ nrfx_usbd_ep_status_t status; /**< Status for the endpoint. */
+ } eptransfer;
+ } data;
+} nrfx_usbd_evt_t;
+
+/**
+ * @brief USBD event callback function type.
+ *
+ * @param[in] p_event Event information structure.
+ */
+typedef void (*nrfx_usbd_event_handler_t)(nrfx_usbd_evt_t const * p_event);
+
+/**
+ * @brief Universal data pointer.
+ *
+ * Universal data pointer that can be used for any type of transfer.
+ */
+typedef union
+{
+ void const * tx; //!< Constant TX buffer pointer.
+ void * rx; //!< Writable RX buffer pointer.
+ uint32_t addr; //!< Numeric value used internally by the driver.
+} nrfx_usbd_data_ptr_t;
+
+/**
+ * @brief Structure to be filled with information about the next transfer.
+ *
+ * This is used mainly for transfer feeders and consumers.
+ * It describes a single endpoint transfer and therefore the size of the buffer
+ * can never be higher than the endpoint size.
+ */
+typedef struct
+{
+ nrfx_usbd_data_ptr_t p_data; //!< Union with available data pointers used by the driver.
+ size_t size; //!< Size of the requested transfer.
+} nrfx_usbd_ep_transfer_t;
+
+/**
+ * @brief Flags for the current transfer.
+ *
+ * Flags configured for the transfer that can be merged using the bitwise 'or' operator (|).
+ */
+typedef enum
+{
+ NRFX_USBD_TRANSFER_ZLP_FLAG = 1U << 0, //!< Add a zero-length packet.
+} nrfx_usbd_transfer_flags_t;
+
+/**
+ * @brief Total transfer configuration.
+ *
+ * This structure is used to configure total transfer information.
+ * It is used by internal built-in feeders and consumers.
+ */
+typedef struct
+{
+ nrfx_usbd_data_ptr_t p_data; //!< Union with available data pointers used by the driver.
+ size_t size; //!< Total size of the requested transfer.
+ uint32_t flags; //!< Transfer flags.
+ /**< Use the @ref nrfx_usbd_transfer_flags_t values. */
+} nrfx_usbd_transfer_t;
+
+/**
+ * @brief Auxiliary macro for declaring IN transfer description with optional flags.
+ *
+ * The base macro for creating transfers with any configuration option.
+ *
+ * @param name Instance name.
+ * @param tx_buff Buffer to transfer.
+ * @param tx_size Transfer size.
+ * @param tx_flags Flags for the transfer (see @ref nrfx_usbd_transfer_flags_t).
+ *
+ * @return Configured variable with total transfer description.
+ */
+#define NRFX_USBD_TRANSFER_IN(name, tx_buff, tx_size, tx_flags) \
+ const nrfx_usbd_transfer_t name = { \
+ .p_data = { .tx = (tx_buff) }, \
+ .size = (tx_size), \
+ .flags = (tx_flags) \
+ }
+
+/**
+ * @brief Helper macro for declaring OUT transfer item (@ref nrfx_usbd_transfer_t).
+ *
+ * @param name Instance name.
+ * @param rx_buff Buffer to transfer.
+ * @param rx_size Transfer size.
+ * */
+#define NRFX_USBD_TRANSFER_OUT(name, rx_buff, rx_size) \
+ const nrfx_usbd_transfer_t name = { \
+ .p_data = { .rx = (rx_buff) }, \
+ .size = (rx_size), \
+ .flags = 0 \
+ }
+
+/**
+ * @brief USBD transfer feeder.
+ *
+ * Pointer for a transfer feeder.
+ * Transfer feeder is a feedback function used to prepare a single
+ * TX (Device->Host) endpoint transfer.
+ *
+ * The transfers provided by the feeder must be simple:
+ * - The size of the transfer provided by this function is limited to a single endpoint buffer.
+ * Bigger transfers are not handled automatically in this case.
+ * - Flash transfers are not automatically supported- you must copy them to the RAM buffer before.
+ *
+ * @note
+ * This function may use @ref nrfx_usbd_feeder_buffer_get to gain a temporary buffer
+ * that can be used to prepare transfer.
+ *
+ * @param[out] p_next Structure with the data for the next transfer to be filled.
+ * Required only if the function returns true.
+ * @param[in,out] p_context Context variable configured with the transfer.
+ * @param[in] ep_size The endpoint size.
+ *
+ * @retval false The current transfer is the last one - you do not need to call
+ * the function again.
+ * @retval true There is more data to be prepared and when the current transfer
+ * finishes, the feeder function is expected to be called again.
+ */
+typedef bool (*nrfx_usbd_feeder_t)(nrfx_usbd_ep_transfer_t * p_next,
+ void * p_context,
+ size_t ep_size);
+
+/**
+ * @brief USBD transfer consumer.
+ *
+ * Pointer for a transfer consumer.
+ * Transfer consumer is a feedback function used to prepare a single
+ * RX (Host->Device) endpoint transfer.
+ *
+ * The transfer must provide a buffer big enough to fit the whole data from the endpoint.
+ * Otherwise, the NRFX_USBD_EP_OVERLOAD event is generated.
+ *
+ * @param[out] p_next Structure with the data for the next transfer to be filled.
+ * Required only if the function returns true.
+ * @param[in,out] p_context Context variable configured with the transfer.
+ * @param[in] ep_size The endpoint size.
+ * @param[in] data_size Number of received bytes in the endpoint buffer.
+ *
+ * @retval false Current transfer is the last one - you do not need to call
+ * the function again.
+ * @retval true There is more data to be prepared and when current transfer
+ * finishes, the feeder function is expected to be called again.
+ */
+typedef bool (*nrfx_usbd_consumer_t)(nrfx_usbd_ep_transfer_t * p_next,
+ void * p_context,
+ size_t ep_size,
+ size_t data_size);
+
+/**
+ * @brief Universal transfer handler.
+ *
+ * Union with feeder and consumer function pointer.
+ */
+typedef union
+{
+ nrfx_usbd_feeder_t feeder; //!< Feeder function pointer.
+ nrfx_usbd_consumer_t consumer; //!< Consumer function pointer.
+} nrfx_usbd_handler_t;
+
+/**
+ * @brief USBD transfer descriptor.
+ *
+ * Universal structure that may hold the setup for callback configuration for
+ * IN or OUT type of the transfer.
+ */
+typedef struct
+{
+ nrfx_usbd_handler_t handler; //!< Handler for the current transfer, function pointer.
+ void * p_context; //!< Context for the transfer handler.
+} nrfx_usbd_handler_desc_t;
+
+/**
+ * @brief Setup packet structure.
+ *
+ * Structure that contains interpreted SETUP packet as described in USB specification.
+ */
+typedef struct
+{
+ uint8_t bmRequestType; //!< byte 0
+ uint8_t bmRequest; //!< byte 1
+ uint16_t wValue; //!< byte 2, 3
+ uint16_t wIndex; //!< byte 4, 5
+ uint16_t wLength; //!< byte 6, 7
+} nrfx_usbd_setup_t;
+
+/**
+ * @brief Driver initialization.
+ *
+ * @param[in] event_handler Event handler provided by the user. Cannot be null.
+ *
+ * @retval NRFX_SUCCESS Initialization successful.
+ * @retval NRFX_ERROR_INVALID_STATE Driver was already initialized.
+ */
+nrfx_err_t nrfx_usbd_init(nrfx_usbd_event_handler_t event_handler);
+
+/**
+ * @brief Driver deinitialization.
+ */
+void nrfx_usbd_uninit(void);
+
+/**
+ * @brief Enable the USBD port.
+ *
+ * After calling this function USBD peripheral would be enabled.
+ * The USB LDO would be enabled.
+ * Enabled USBD peripheral would request HFCLK.
+ * This function does not enable external oscillator, so if it is not enabled by other part of the
+ * program after enabling USBD driver HFINT would be used for the USBD peripheral.
+ * It is perfectly fine until USBD is started. See @ref nrfx_usbd_start.
+ *
+ * In normal situation this function should be called in reaction to USBDETECTED
+ * event from POWER peripheral.
+ *
+ * Interrupts and USB pins pull-up would stay disabled until @ref nrfx_usbd_start
+ * function is called.
+ */
+void nrfx_usbd_enable(void);
+
+/**
+ * @brief Disable the USBD port.
+ *
+ * After calling this function USBD peripheral would be disabled.
+ * No events would be detected or processed by the driver.
+ * Clock for the peripheral would be disconnected.
+ */
+void nrfx_usbd_disable(void);
+
+/**
+ * @brief Start USB functionality.
+ *
+ * After calling this function USBD peripheral should be fully functional
+ * and all new incoming events / interrupts would be processed by the driver.
+ *
+ * Also only after calling this function host sees new connected device.
+ *
+ * Call this function when USBD power LDO regulator is ready - on USBPWRRDY event
+ * from POWER peripheral.
+ *
+ * Before USBD interrupts are enabled, external HFXO is requested.
+ *
+ * @param enable_sof The flag that is used to enable SOF processing.
+ * If it is false, SOF interrupt is left disabled and will not be generated.
+ * This improves power saving if SOF is not required.
+ *
+ * @note If the isochronous endpoints are going to be used,
+ * it is required to enable the SOF.
+ * In other case any isochronous endpoint would stay busy
+ * after first transmission.
+ */
+void nrfx_usbd_start(bool enable_sof);
+
+/**
+ * @brief Stop USB functionality.
+ *
+ * This function disables USBD pull-up and interrupts.
+ *
+ * The HFXO request is released in this function.
+ *
+ * @note
+ * This function can also be used to logically disconnect USB from the HOST that
+ * would force it to enumerate device after calling @ref nrfx_usbd_start.
+ */
+void nrfx_usbd_stop(void);
+
+/**
+ * @brief Check if driver is initialized.
+ *
+ * @retval false Driver is not initialized.
+ * @retval true Driver is initialized.
+ */
+bool nrfx_usbd_is_initialized(void);
+
+/**
+ * @brief Check if driver is enabled.
+ *
+ * @retval false Driver is disabled.
+ * @retval true Driver is enabled.
+ */
+bool nrfx_usbd_is_enabled(void);
+
+/**
+ * @brief Check if driver is started.
+ *
+ * @retval false Driver is not started.
+ * @retval true Driver is started (fully functional).
+ * @note The USBD peripheral interrupt state is checked.
+ */
+bool nrfx_usbd_is_started(void);
+
+/**
+ * @brief Suspend USBD operation.
+ *
+ * The USBD peripheral is forced to go into the low power mode.
+ * The function has to be called in the reaction to @ref NRFX_USBD_EVT_SUSPEND event
+ * when the firmware is ready.
+ *
+ * After successful call of this function most of the USBD registers would be unavailable.
+ *
+ * @note Check returned value for the feedback if suspending was successful.
+ *
+ * @retval true USBD peripheral successfully suspended.
+ * @retval false USBD peripheral was not suspended due to resume detection.
+ */
+bool nrfx_usbd_suspend(void);
+
+/**
+ * @brief Start wake up procedure.
+ *
+ * The USBD peripheral is forced to quit the low power mode.
+ * After calling this function all the USBD registers would be available.
+ *
+ * The hardware starts measuring time when wake up is possible.
+ * This may take 0-5 ms depending on how long the SUSPEND state was kept on the USB line.
+
+ * When NRFX_USBD_EVT_WUREQ event is generated it means that Wake Up signaling has just been
+ * started on the USB lines.
+ *
+ * @note Do not expect only @ref NRFX_USBD_EVT_WUREQ event.
+ * There always may appear @ref NRFX_USBD_EVT_RESUME event.
+ * @note NRFX_USBD_EVT_WUREQ event means that Remote WakeUp signal
+ * has just begun to be generated.
+ * This may take up to 20 ms for the bus to become active.
+ *
+ * @retval true WakeUp procedure started.
+ * @retval false No WakeUp procedure started - bus is already active.
+ */
+bool nrfx_usbd_wakeup_req(void);
+
+/**
+ * @brief Check if USBD is in SUSPEND mode.
+ *
+ * @note This is the information about peripheral itself, not about the bus state.
+ *
+ * @retval true USBD peripheral is suspended.
+ * @retval false USBD peripheral is active.
+ */
+bool nrfx_usbd_suspend_check(void);
+
+/**
+ * @brief Enable only interrupts that should be processed in SUSPEND mode.
+ *
+ * Auxiliary function to help with SUSPEND mode integration.
+ * It enables only the interrupts that can be properly processed without stable HFCLK.
+ *
+ * Normally all the interrupts are enabled.
+ * Use this function to suspend interrupt processing that may require stable HFCLK until the
+ * clock is enabled.
+ *
+ * @sa nrfx_usbd_active_irq_config
+ */
+void nrfx_usbd_suspend_irq_config(void);
+
+/**
+ * @brief Default active interrupt configuration.
+ *
+ * Default interrupt configuration.
+ * Use in a pair with @ref nrfx_usbd_active_irq_config.
+ *
+ * @sa nrfx_usbd_suspend_irq_config
+ */
+void nrfx_usbd_active_irq_config(void);
+
+/**
+ * @brief Check the bus state.
+ *
+ * This function checks if the bus state is suspended.
+ *
+ * @note The value returned by this function changes on SUSPEND and RESUME event processing.
+ *
+ * @retval true USBD bus is suspended.
+ * @retval false USBD bus is active.
+ */
+bool nrfx_usbd_bus_suspend_check(void);
+
+/**
+ * @brief Force the bus state to active
+ */
+void nrfx_usbd_force_bus_wakeup(void);
+
+/**
+ * @brief Configure packet size that should be supported by the endpoint.
+ *
+ * The real endpoint buffer size is always the same.
+ * This value sets max packet size that would be transmitted over the endpoint.
+ * This is required by the driver.
+ *
+ * @param[in] ep Endpoint number.
+ * @param[in] size Required maximum packet size.
+ *
+ * @note Endpoint size is always set to @ref NRFX_USBD_EPSIZE or @ref NRFX_USBD_ISOSIZE / 2
+ * when @ref nrfx_usbd_ep_enable function is called.
+ */
+void nrfx_usbd_ep_max_packet_size_set(nrfx_usbd_ep_t ep, uint16_t size);
+
+/**
+ * @brief Get configured endpoint packet size.
+ *
+ * Function to get configured endpoint size on the buffer.
+ *
+ * @param[in] ep Endpoint number.
+ *
+ * @return Maximum pocket size configured on selected endpoint.
+ */
+uint16_t nrfx_usbd_ep_max_packet_size_get(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Check if the selected endpoint is enabled.
+ *
+ * @param[in] ep Endpoint number to check.
+ *
+ * @retval true Endpoint is enabled.
+ * @retval false Endpoint is disabled.
+ */
+bool nrfx_usbd_ep_enable_check(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Enable selected endpoint.
+ *
+ * This function enables endpoint itself and its interrupts.
+ *
+ * @param[in] ep Endpoint number to enable.
+ *
+ * @note
+ * Max packet size is set to endpoint default maximum value.
+ *
+ * @sa nrfx_usbd_ep_max_packet_size_set
+ */
+void nrfx_usbd_ep_enable(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Disable selected endpoint.
+ *
+ * This function disables endpoint itself and its interrupts.
+ *
+ * @param[in] ep Endpoint number to disable.
+ */
+void nrfx_usbd_ep_disable(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Disable all endpoints except for EP0.
+ *
+ * Disable all endpoints that can be disabled in USB device while it is still active.
+ */
+void nrfx_usbd_ep_default_config(void);
+
+/**
+ * @brief Start sending data over endpoint.
+ *
+ * Function initializes endpoint transmission.
+ * This is asynchronous function - it finishes immediately after configuration
+ * for transmission is prepared.
+ *
+ * @note Data buffer pointed by p_data have to be kept active till
+ * @ref NRFX_USBD_EVT_EPTRANSFER event is generated.
+ *
+ * @param[in] ep Endpoint number.
+ * For IN endpoint sending would be initiated.
+ * For OUT endpoint receiving would be initiated.
+ * @param[in] p_transfer Transfer parameters.
+ *
+ * @retval NRFX_SUCCESS Transfer queued or started.
+ * @retval NRFX_ERROR_BUSY Selected endpoint is pending.
+ * @retval NRFX_ERROR_INVALID_ADDR Unexpected transfer on EPIN0 or EPOUT0.
+ */
+nrfx_err_t nrfx_usbd_ep_transfer(nrfx_usbd_ep_t ep,
+ nrfx_usbd_transfer_t const * p_transfer);
+
+/**
+ * @brief Start sending data over the endpoint using the transfer handler function.
+ *
+ * This function initializes an endpoint transmission.
+ * Just before data is transmitted, the transfer handler
+ * is called and it prepares a data chunk.
+ *
+ * @param[in] ep Endpoint number.
+ * For an IN endpoint, sending is initiated.
+ * For an OUT endpoint, receiving is initiated.
+ * @param[in] p_handler Transfer handler - feeder for IN direction and consumer for
+ * OUT direction.
+ *
+ * @retval NRFX_SUCCESS Transfer queued or started.
+ * @retval NRFX_ERROR_BUSY Selected endpoint is pending.
+ * @retval NRFX_ERROR_INVALID_ADDR Unexpected transfer on EPIN0 or EPOUT0.
+ */
+nrfx_err_t nrfx_usbd_ep_handled_transfer(nrfx_usbd_ep_t ep,
+ nrfx_usbd_handler_desc_t const * p_handler);
+
+/**
+ * @brief Get the temporary buffer to be used by the feeder.
+ *
+ * This buffer is used for TX transfers and it can be reused automatically
+ * when the transfer is finished.
+ * Use it for transfer preparation.
+ *
+ * May be used inside the feeder configured in @ref nrfx_usbd_ep_handled_transfer.
+ *
+ * @return Pointer to the buffer that can be used temporarily.
+ *
+ * @sa NRFX_USBD_FEEDER_BUFFER_SIZE
+ */
+void * nrfx_usbd_feeder_buffer_get(void);
+
+/**
+ * @brief Get the information about last finished or current transfer.
+ *
+ * Function returns the status of the last buffer set for transfer on selected endpoint.
+ * The status considers last buffer set by @ref nrfx_usbd_ep_transfer function or
+ * by transfer callback function.
+ *
+ * @param[in] ep Endpoint number.
+ * @param[out] p_size Information about the current/last transfer size.
+ *
+ * @return Endpoint status.
+ *
+ * @sa nrfx_usbd_ep_status_t
+ */
+nrfx_usbd_ep_status_t nrfx_usbd_ep_status_get(nrfx_usbd_ep_t ep, size_t * p_size);
+
+/**
+ * @brief Get number of received bytes.
+ *
+ * Get the number of received bytes.
+ * The function behavior is undefined when called on IN endpoint.
+ *
+ * @param[in] ep Endpoint number.
+ *
+ * @return Number of received bytes.
+ */
+size_t nrfx_usbd_epout_size_get(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Check if endpoint buffer is ready or is under USB IP control.
+ *
+ * Function to test if endpoint is busy.
+ * Endpoint that is busy cannot be accessed by MCU.
+ * It means that:
+ * - OUT (TX) endpoint: Last uploaded data is still in endpoint and is waiting
+ * to be received by the host.
+ * - IN (RX) endpoint: Endpoint is ready to receive data from the host
+ * and the endpoint does not have any data.
+ * When endpoint is not busy:
+ * - OUT (TX) endpoint: New data can be uploaded.
+ * - IN (RX) endpoint: New data can be downloaded using @ref nrfx_usbd_ep_transfer
+ * function.
+ *
+ * @param[in] ep Endpoint number.
+ *
+ * @retval false Endpoint is not busy.
+ * @retval true Endpoint is busy.
+ */
+bool nrfx_usbd_ep_is_busy(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Stall endpoint
+ *
+ * Stall endpoit to send error information during next transfer request from
+ * the host.
+ *
+ * @note To stall endpoint it is safer to use @ref nrfx_usbd_setup_stall
+ * @note Stalled endpoint would not be cleared when DMA transfer finishes.
+ *
+ * @param[in] ep Endpoint number to stall.
+ */
+void nrfx_usbd_ep_stall(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Clear stall flag on endpoint.
+ *
+ * This function clears endpoint that is stalled.
+ * @note
+ * If it is OUT endpoint (receiving) it would be also prepared for reception.
+ * It means that busy flag would be set.
+ * @note
+ * In endpoint (transmitting) would not be cleared - it gives possibility to
+ * write new data before transmitting.
+ *
+ * @param[in] ep Endpoint number.
+ */
+void nrfx_usbd_ep_stall_clear(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Check if endpoint is stalled.
+ *
+ * This function gets stall state of selected endpoint.
+ *
+ * @param[in] ep Endpoint number to check.
+ *
+ * @retval false Endpoint is not stalled.
+ * @retval true Endpoint is stalled.
+ */
+bool nrfx_usbd_ep_stall_check(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Clear current endpoint data toggle.
+ *
+ * @param[in] ep Endpoint number to clear.
+ */
+void nrfx_usbd_ep_dtoggle_clear(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Get parsed setup data.
+ *
+ * Function fills the parsed setup data structure.
+ *
+ * @param[out] p_setup Pointer to data structure that would be filled by
+ * parsed data.
+ */
+void nrfx_usbd_setup_get(nrfx_usbd_setup_t * p_setup);
+
+/**
+ * @brief Clear the control endpoint for packet reception during DATA stage.
+ *
+ * This function may be called if any more data in control write transfer is expected.
+ * Clears only OUT endpoint to be able to take another OUT data token.
+ * It does not allow STATUS stage.
+ * @sa nrfx_usbd_setup_clear
+ */
+void nrfx_usbd_setup_data_clear(void);
+
+/**
+ * @brief Clear setup endpoint.
+ *
+ * This function acknowledges setup when SETUP command was received and processed.
+ * It has to be called if no data respond for the SETUP command is sent.
+ */
+void nrfx_usbd_setup_clear(void);
+
+/**
+ * @brief Stall setup endpoint.
+ *
+ * Mark an error on setup endpoint.
+ */
+void nrfx_usbd_setup_stall(void);
+
+/**
+ * @brief Abort pending transfer on selected endpoint.
+ *
+ * @param[in] ep Endpoint number.
+ */
+void nrfx_usbd_ep_abort(nrfx_usbd_ep_t ep);
+
+/**
+ * @brief Get the information about expected transfer SETUP data direction.
+ *
+ * Function returns the information about last expected transfer direction.
+ *
+ * @retval NRFX_USBD_EPOUT0 Expecting OUT (Host->Device) direction or no data.
+ * @retval NRFX_USBD_EPIN0 Expecting IN (Device->Host) direction.
+ */
+nrfx_usbd_ep_t nrfx_usbd_last_setup_dir_get(void);
+
+/**
+ * @brief Drop transfer on OUT endpoint.
+ *
+ * @param[in] ep OUT endpoint ID.
+ */
+void nrfx_usbd_transfer_out_drop(nrfx_usbd_ep_t ep);
+
+
+void nrfx_usbd_irq_handler(void);
+
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_USBD_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
index 8f82ebcdc2..ff00ff5b73 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_wdt.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
index 2b17f7d0e8..537f1ef6cb 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_common.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -117,6 +117,27 @@ extern "C" {
*/
#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
+/**@brief Macro for performing integer division, making sure the result is rounded up.
+ *
+ * @details A typical use case for this macro is to compute the number of objects
+ * with size @c b required to hold @c a number of bytes.
+ *
+ * @param a Numerator.
+ * @param b Denominator.
+ *
+ * @return Integer result of dividing @c a by @c b, rounded up.
+ */
+#define NRFX_CEIL_DIV(a, b) ((((a) - 1) / (b)) + 1)
+
+/**
+ * @brief Macro for getting the number of elements in an array.
+ *
+ * @param array Name of the array.
+ *
+ * @return Array element count.
+ */
+#define NRFX_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+
/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
* the limit of the specified peripheral.
*
@@ -152,6 +173,23 @@ do { \
} while (--remaining_attempts); \
} while(0)
+/**
+ * @brief Macro for getting the interrupt number assigned to a specific
+ * peripheral.
+ *
+ * In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID
+ * of this peripheral, and there is a direct relationship between this ID and
+ * the peripheral base address, i.e. the address of a fixed block of 0x1000
+ * bytes of address space assigned to this peripheral.
+ * See the chapter "Peripheral interface" (sections "Peripheral ID" and
+ * "Interrupts") in the product specification of a given SoC.
+ *
+ * @param[in] base_addr Peripheral base address or pointer.
+ *
+ * @return Interrupt number associated with the specified peripheral.
+ */
+#define NRFX_IRQ_NUMBER_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12)
+
/**
* @brief IRQ handler type.
*/
@@ -233,8 +271,7 @@ __STATIC_INLINE bool nrfx_is_in_ram(void const * p_object)
__STATIC_INLINE IRQn_Type nrfx_get_irq_number(void const * p_reg)
{
- uint8_t irq_number = (uint8_t)(((uint32_t)p_reg) >> 12u);
- return (IRQn_Type)irq_number;
+ return (IRQn_Type)NRFX_IRQ_NUMBER_GET(p_reg);
}
__STATIC_INLINE uint32_t nrfx_bitpos_to_event(uint32_t bit)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
index f2fed763b8..31062ce890 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/nrfx_errors.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
index 96dc9824cb..4f74a7af8f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_adc.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -84,11 +84,16 @@ nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config,
void nrfx_adc_uninit(void)
{
- m_cb.p_head = NULL;
NRFX_IRQ_DISABLE(ADC_IRQn);
nrf_adc_int_disable(NRF_ADC_INT_END_MASK);
nrf_adc_task_trigger(NRF_ADC_TASK_STOP);
+ // Disable all channels. This must be done after the interrupt is disabled
+ // because adc_sample_process() dereferences this pointer when it needs to
+ // switch back to the first channel in the list (when the number of samples
+ // to read is bigger than the number of enabled channels).
+ m_cb.p_head = NULL;
+
m_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
}
@@ -140,6 +145,13 @@ void nrfx_adc_channel_disable(nrfx_adc_channel_t * const p_channel)
NRFX_LOG_INFO("Disabled.");
}
+void nrfx_adc_all_channels_disable(void)
+{
+ NRFX_ASSERT(!nrfx_adc_is_busy());
+
+ m_cb.p_head = NULL;
+}
+
void nrfx_adc_sample(void)
{
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
@@ -203,6 +215,10 @@ static bool adc_sample_process()
bool task_trigger = false;
if (m_cb.p_current_conv->p_next == NULL)
{
+ // Make sure the list of channels has not been somehow removed
+ // (it is when all channels are disabled).
+ NRFX_ASSERT(m_cb.p_head);
+
m_cb.p_current_conv = m_cb.p_head;
}
else
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
index 8bda4a912d..22a238f32d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
index 618ec77470..b52af85015 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_comp.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
index b5e18fe5db..00ac66db57 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
index 28b412556b..76a12ad480 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -45,6 +45,14 @@
(event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : \
"UNKNOWN EVENT")))
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_194) && \
+ (defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52840_XXAA))
+// Enable workaround for nRF52832 and nRF52840 anomaly 194 (STOP task does not
+// switch off all resources).
+#define USE_WORKAROUND_FOR_ANOMALY_194 1
+#endif
+
// Control block - driver instance local data.
typedef struct
{
@@ -321,6 +329,11 @@ void nrfx_i2s_stop(void)
nrf_i2s_int_disable(NRF_I2S, NRF_I2S_INT_RXPTRUPD_MASK |
NRF_I2S_INT_TXPTRUPD_MASK);
nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP);
+
+#if USE_WORKAROUND_FOR_ANOMALY_194
+ *((volatile uint32_t *)0x40025038) = 1;
+ *((volatile uint32_t *)0x4002503C) = 1;
+#endif
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
index d508789027..7e60acc113 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_lpcomp.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
new file mode 100644
index 0000000000..53ccb50777
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
@@ -0,0 +1,884 @@
+/*
+ * Copyright (c) 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <nrfx.h>
+
+#if NRFX_CHECK(NRFX_NFCT_ENABLED)
+
+#include <nrfx_nfct.h>
+
+#define NRFX_LOG_MODULE NFCT
+#include <nrfx_log.h>
+
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA)
+#define USE_TIMER_WORKAROUND
+#endif
+
+#ifdef USE_TIMER_WORKAROUND
+#include <nrfx_timer.h>
+
+typedef struct
+{
+ const nrfx_timer_t timer; /**< Timer instance that supports the correct NFC field detection. */
+#ifdef NRF52840_XXAA
+ bool fieldevents_filter_active; /**< Flag that indicates that the field events are ignored. */
+ bool is_hfclk_on; /**< HFCLK has started - one of the NFC activation conditions. */
+ bool is_delayed; /**< Required time delay has passed - one of the NFC activation conditions. */
+#else
+ uint32_t field_state_cnt; /**< Counter of the FIELDLOST events. */
+#endif // NRF52840_XXAA
+} nrfx_nfct_timer_workaround_t;
+
+#ifdef NRF52840_XXAA
+ #define NRFX_NFCT_ACTIVATE_DELAY 1000 /**< Minimal delay in us between NFC field detection and activation of NFCT. */
+ #define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_ACTIVATE_DELAY
+#else
+ #define NRFX_NFCT_FIELDLOST_THR 7
+ #define NRFX_NFCT_FIELD_TIMER_PERIOD 100 /**< Field polling period in us. */
+ #define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_FIELD_TIMER_PERIOD
+#endif // NRF52840_XXAA
+#define NRFX_NFCT_TIMER_INSTANCE 4 /**< Timer instance used for various workarounds for the NFCT HW issues.*/
+
+static nrfx_nfct_timer_workaround_t m_timer_workaround =
+{
+ .timer = NRFX_TIMER_INSTANCE(NRFX_NFCT_TIMER_INSTANCE),
+};
+#endif // USE_TIMER_WORKAROUND
+
+#define NRFX_NFCT_FRAMEDELAYMAX_52840S (0xFFFFUL) /**< Bit mask of the FRAMEDELAYMAX field for the first sample of 52840.*/
+#define NRFX_NFCT_FWT_MAX_DIFF 1u /**< The maximal difference between the requested FWT and HW-limited FWT settings.*/
+
+/* Mask of all possible interrupts that are relevant for data reception. */
+#define NRFX_NFCT_RX_INT_MASK (NRF_NFCT_INT_RXFRAMESTART_MASK | \
+ NRF_NFCT_INT_RXFRAMEEND_MASK | \
+ NRF_NFCT_INT_RXERROR_MASK)
+
+/* Mask of all possible interrupts that are relevant for data transmission. */
+#define NRFX_NFCT_TX_INT_MASK (NRF_NFCT_INT_TXFRAMESTART_MASK | \
+ NRF_NFCT_INT_TXFRAMEEND_MASK)
+
+
+/* Mask of all possible errors from the @ref NRF_NFCT_EVENT_RXERROR event. */
+#define NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK (NRF_NFCT_RX_FRAME_STATUS_CRC_MASK | \
+ NRF_NFCT_RX_FRAME_STATUS_PARITY_MASK | \
+ NRF_NFCT_RX_FRAME_STATUS_OVERRUN_MASK)
+
+/* Mask of all possible errors from the @ref NRF_NFCT_EVENT_ERROR event. */
+#if defined (NRF52832_XXAA) || defined(NRF52832_XXAB)
+#define NRFX_NFCT_ERROR_STATUS_ALL_MASK (NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK | \
+ NRF_NFCT_ERROR_NFCFIELDTOOSTRONG_MASK | \
+ NRF_NFCT_ERROR_NFCFIELDTOOWEAK_MASK)
+#else
+#define NRFX_NFCT_ERROR_STATUS_ALL_MASK (NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK)
+#endif
+
+/* Macros for conversion of bits to bytes. */
+#define NRFX_NFCT_BYTES_TO_BITS(_bytes) ((_bytes) << 3)
+#define NRFX_NFCT_BITS_TO_BYTES(_bits) ((_bits) >> 3)
+
+/* Macro for checking whether the NFCT interrupt is active. */
+#define NRFX_NFCT_EVT_ACTIVE(_name) (nrf_nfct_event_check(NRFX_CONCAT_2(NRF_NFCT_EVENT_, _name)) && \
+ nrf_nfct_int_enable_check(NRFX_CONCAT_3(NRF_NFCT_INT_, _name, _MASK)))
+
+/* Macro for callback execution. */
+#define NRFX_NFCT_CB_HANDLE(_cb, _evt) \
+ if (_cb != NULL) \
+ { \
+ _cb(&_evt); \
+ }
+
+typedef enum
+{
+ NRFX_NFC_FIELD_STATE_NONE, /**< Initial value that indicates no NFCT field events. */
+ NRFX_NFC_FIELD_STATE_OFF, /**< The NFCT FIELDLOST event has been set. */
+ NRFX_NFC_FIELD_STATE_ON, /**< The NFCT FIELDDETECTED event has been set. */
+ NRFX_NFC_FIELD_STATE_UNKNOWN /**< Both NFCT field events have been set - ambiguous state. */
+} nrfx_nfct_field_state_t;
+
+#ifdef NRF52840_XXAA
+/**
+ * @brief Internal auxiliary function for checking whether the program is running on the NRF52840 chip.
+ *
+ * @retval true It is NRF52480 chip.
+ * @retval false It is an other chip.
+ */
+static inline bool nrfx_nfct_type_52840_check(void)
+{
+ return ((((*(uint32_t *)0xF0000FE0) & 0xFF) == 0x08) &&
+ (((*(uint32_t *)0xF0000FE4) & 0x0F) == 0x0));
+}
+
+/**
+ * @brief Internal auxiliary function for checking whether the program is running on the first sample of
+ * the nRF52840 chip.
+ *
+ * @retval true It is the nRF52480 chip and it is the first sample version.
+ * @retval false It is an other chip.
+ */
+static inline bool nrfx_nfct_type_52840_sample_check(void)
+{
+ return ( nrfx_nfct_type_52840_check() &&
+ ( ((*(uint32_t *)0xF0000FE8) & 0xF0) == 0x00 ) &&
+ ( ((*(uint32_t *)0xF0000FEC) & 0xF0) == 0x00 ) );
+}
+
+/**
+ * @brief Internal auxiliary function for checking whether the program is running on the final version of
+ * the nRF52840 chip.
+ *
+ * @retval true It is the nRF52480 chip and it is the final version.
+ * @retval false It is an other chip.
+ */
+static inline bool nrfx_nfct_type_52840_final_check(void)
+{
+ return ( nrfx_nfct_type_52840_check() &&
+ ( ( ((*(uint32_t *)0xF0000FE8) & 0xF0) != 0x00 ) ||
+ ( ((*(uint32_t *)0xF0000FEC) & 0xF0) != 0x00 ) ));
+}
+
+typedef struct
+{
+ bool eng_a; /**< Engineering sample A of the NRF52840 chip. */
+ bool eng_bc; /**< Engineering sample B, C of the NRF52840 chip, or its final version. */
+} nrfx_nfct_nrf52840_ver_t;
+
+static nrfx_nfct_nrf52840_ver_t m_nrf52840;
+#endif // NRF52840_XXAA
+
+/**@brief NFCT control block. */
+typedef struct
+{
+ nrfx_nfct_config_t config;
+ nrfx_drv_state_t state;
+ volatile bool field_on;
+} nrfx_nfct_control_block_t;
+
+static nrfx_nfct_control_block_t m_nfct_cb;
+
+/**
+ * @brief Common part of the setup used for the NFCT initialization and reinitialization.
+ */
+static void nrfx_nfct_hw_init_setup(void)
+{
+#ifdef NRF52840_XXAA
+ if (m_nrf52840.eng_a)
+ {
+ /* Begin: Bugfix for FTPAN-98 */
+ *(volatile uint32_t *) 0x4000568C = 0x00038148;
+ /* End: Bugfix for FTPAN-98 */
+ /* Begin: Bugfix for FTPAN-144 */
+ *(volatile uint32_t *) 0x4000561c = 0x01;
+ *(volatile uint32_t *) 0x4000562c = 0x3F;
+ *(volatile uint32_t *) 0x4000563c = 0x0;
+ /* End: Bugfix for FTPAN-144 */
+ }
+#endif // NRF52840_XXAA
+
+ //Enable necessary interrupts.
+ nrf_nfct_int_enable(NRF_NFCT_INT_FIELDDETECTED_MASK | NRF_NFCT_INT_ERROR_MASK |
+ NRF_NFCT_INT_SELECTED_MASK);
+#if !defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+ nrf_nfct_int_enable(NRF_NFCT_INT_FIELDLOST_MASK);
+#endif //!defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+
+ // Use Window Grid frame delay mode.
+ nrf_nfct_frame_delay_mode_set(NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID);
+
+ /* Begin: Bugfix for FTPAN-25 (IC-9929) */
+ /* Workaround for wrong SENSRES values require using SDD00001, but here SDD00100 is used
+ because it is required to operate with Windows Phone */
+ nrf_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_SENSRES_BIT_FRAME_SDD_00100);
+ /* End: Bugfix for FTPAN-25 (IC-9929) */
+}
+
+/**@brief Function for evaluating and handling the NFC field events.
+ *
+ * @param[in] field_state Current field state.
+ */
+static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field_state)
+{
+ nrfx_nfct_evt_t nfct_evt;
+
+#ifdef NRF52840_XXAA
+ if((!m_nrf52840.eng_a) && (m_timer_workaround.fieldevents_filter_active))
+ {
+ return;
+ }
+#endif // NRF52840_XXAA
+
+ if (field_state == NRFX_NFC_FIELD_STATE_UNKNOWN)
+ {
+ /* Probe NFC field */
+ field_state = (nrfx_nfct_field_check()) ? NRFX_NFC_FIELD_STATE_ON : NRFX_NFC_FIELD_STATE_OFF;
+ }
+
+ /* Field event service */
+ switch (field_state)
+ {
+ case NRFX_NFC_FIELD_STATE_ON:
+ if (!m_nfct_cb.field_on)
+ {
+#ifdef NRF52840_XXAA
+ /* Begin: Bugfix for FTPAN-190 */
+ if (!m_nrf52840.eng_a)
+ {
+ m_timer_workaround.is_hfclk_on = false;
+ m_timer_workaround.is_delayed = false;
+ m_timer_workaround.fieldevents_filter_active = true;
+
+ nrfx_timer_clear(&m_timer_workaround.timer);
+ nrfx_timer_enable(&m_timer_workaround.timer);
+ }
+ /* END: Bugfix for FTPAN-190 */
+#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+ nrfx_timer_clear(&m_timer_workaround.timer);
+ nrfx_timer_enable(&m_timer_workaround.timer);
+ m_timer_workaround.field_state_cnt = 0;
+#endif // NRF52840_XXAA
+
+ m_nfct_cb.field_on = true;
+ nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_DETECTED;
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ }
+ break;
+
+ case NRFX_NFC_FIELD_STATE_OFF:
+ nrfx_nfct_state_force(NRFX_NFCT_STATE_SENSING);
+#ifdef NRF52840_XXAA
+ /* Begin: Bugfix for FTPAN-116 (IC-12886) */
+ if (m_nrf52840.eng_a)
+ {
+ *(volatile uint32_t *)0x40005010 = 1;
+ }
+ /* END: Bugfix for FTPAN-116 (IC-12886) */
+#endif // NRF52840_XXAA
+ nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
+ m_nfct_cb.field_on = false;
+ nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_LOST;
+
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ break;
+
+ default:
+ /* No implementation required */
+ break;
+ }
+}
+
+#ifdef USE_TIMER_WORKAROUND
+
+#ifdef NRF52840_XXAA
+static void nrfx_nfct_activate_check(void)
+{
+ static bool is_field_validation_pending = false;
+
+ if (is_field_validation_pending)
+ {
+ is_field_validation_pending = false;
+ m_timer_workaround.fieldevents_filter_active = false;
+
+ // Check the field status and take action if field is lost.
+ nrfx_nfct_field_event_handler(NRFX_NFC_FIELD_STATE_UNKNOWN);
+ return;
+ }
+
+ if ((m_timer_workaround.is_hfclk_on) && (m_timer_workaround.is_delayed))
+ {
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_ACTIVATE);
+ is_field_validation_pending = true;
+
+ // Start the timer second time to validate whether the tag has locked to the field.
+ nrfx_timer_clear(&m_timer_workaround.timer);
+ nrfx_timer_enable(&m_timer_workaround.timer);
+ }
+}
+#endif // NRF52840_XXAA
+
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+static inline void nrfx_nfct_reset(void)
+{
+ uint32_t fdm;
+ uint8_t nfcid1[NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE];
+ nrf_nfct_sensres_nfcid1_size_t nfcid1_size;
+ nrf_nfct_selres_protocol_t protocol;
+
+ // Save parameter settings before the reset of the NFCT peripheral.
+ fdm = nrf_nfct_frame_delay_max_get();
+ nfcid1_size = nrf_nfct_nfcid1_get(nfcid1);
+ protocol = nrf_nfct_selsres_protocol_get();
+
+ // Reset the NFCT peripheral.
+ *(volatile uint32_t *)0x40005FFC = 0;
+ *(volatile uint32_t *)0x40005FFC;
+ *(volatile uint32_t *)0x40005FFC = 1;
+
+ // Restore parameter settings after the reset of the NFCT peripheral.
+ nrf_nfct_frame_delay_max_set(fdm);
+ nrf_nfct_nfcid1_set(nfcid1, nfcid1_size);
+ nrf_nfct_selres_protocol_set(protocol);
+
+ // Restore general HW configuration.
+ nrfx_nfct_hw_init_setup();
+ NRFX_LOG_INFO("Reinitialize");
+}
+
+static void nrfx_nfct_field_poll(void)
+{
+ if (!nrfx_nfct_field_check())
+ {
+ if (++m_timer_workaround.field_state_cnt > NRFX_NFCT_FIELDLOST_THR)
+ {
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_FIELD_LOST,
+ };
+
+ nrfx_timer_disable(&m_timer_workaround.timer);
+ m_nfct_cb.field_on = false;
+
+ /* Begin: Bugfix for FTPAN-116 */
+ // resume the NFCT to initialized state
+ nrfx_nfct_reset();
+ /* End: Bugfix for FTPAN-116 */
+
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ }
+ return;
+ }
+
+ m_timer_workaround.field_state_cnt = 0;
+}
+#endif // defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+
+static void nrfx_nfct_field_timer_handler(nrf_timer_event_t event_type, void * p_context)
+{
+ (void)p_context;
+
+ if (event_type != NRF_TIMER_EVENT_COMPARE0)
+ {
+ return;
+ }
+
+#ifdef NRF52840_XXAA
+ m_timer_workaround.is_delayed = true;
+
+ nrfx_timer_disable(&m_timer_workaround.timer);
+ nrfx_nfct_activate_check();
+#else
+ nrfx_nfct_field_poll();
+#endif //NRF52840_XXAA
+}
+
+static inline nrfx_err_t nrfx_nfct_field_timer_config(void)
+{
+ nrfx_err_t err_code;
+ nrfx_timer_config_t timer_cfg =
+ {
+ .frequency = NRF_TIMER_FREQ_1MHz,
+ .mode = NRF_TIMER_MODE_TIMER,
+ .bit_width = NRF_TIMER_BIT_WIDTH_16,
+ .interrupt_priority = NRFX_NFCT_CONFIG_IRQ_PRIORITY
+ };
+
+ err_code = nrfx_timer_init(&m_timer_workaround.timer, &timer_cfg, nrfx_nfct_field_timer_handler);
+ if (err_code != NRFX_SUCCESS)
+ {
+ return err_code;
+ }
+
+ nrfx_timer_extended_compare(&m_timer_workaround.timer,
+ NRF_TIMER_CC_CHANNEL0,
+ nrfx_timer_us_to_ticks(&m_timer_workaround.timer, NRFX_NFCT_TIMER_PERIOD),
+ NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK,
+ true);
+ return err_code;
+}
+
+#endif // USE_TIMER_WORKAROUND
+
+static inline nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_size_to_sensres_size(uint8_t nfcid1_size)
+{
+ switch (nfcid1_size)
+ {
+ case NRFX_NFCT_NFCID1_SINGLE_SIZE:
+ return NRF_NFCT_SENSRES_NFCID1_SIZE_SINGLE;
+
+ case NRFX_NFCT_NFCID1_DOUBLE_SIZE:
+ return NRF_NFCT_SENSRES_NFCID1_SIZE_DOUBLE;
+
+ case NRFX_NFCT_NFCID1_TRIPLE_SIZE:
+ return NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE;
+
+ default:
+ return NRF_NFCT_SENSRES_NFCID1_SIZE_DOUBLE;
+ }
+}
+
+static inline void nrfx_nfct_rxtx_int_enable(uint32_t rxtx_int_mask)
+{
+ nrf_nfct_int_enable(rxtx_int_mask & m_nfct_cb.config.rxtx_int_mask);
+}
+
+nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config)
+{
+ NRFX_ASSERT(p_config);
+
+ nrfx_err_t err_code = NRFX_SUCCESS;
+
+ if (m_nfct_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
+ {
+ return NRFX_ERROR_INVALID_STATE;
+ }
+
+#ifdef NRF52840_XXAA
+ m_nrf52840.eng_a = nrfx_nfct_type_52840_sample_check();
+ m_nrf52840.eng_bc = nrfx_nfct_type_52840_final_check();
+#endif // NRF52840_XXAA
+
+ m_nfct_cb.config = *p_config;
+ nrfx_nfct_hw_init_setup();
+
+#ifdef USE_TIMER_WORKAROUND
+ /* Initialize Timer module as the workaround for NFCT HW issues. */
+ #ifdef NRF52840_XXAA
+ if (!m_nrf52840.eng_a)
+ #endif // NRF52840_XXAA
+ {
+ err_code = nrfx_nfct_field_timer_config();
+ }
+#endif // USE_TIMER_WORKAROUND
+
+ if (err_code == NRFX_SUCCESS)
+ {
+ uint8_t default_nfcid1[NRFX_NFCT_NFCID1_DEFAULT_LEN];
+ err_code = nrfx_nfct_nfcid1_default_bytes_get(default_nfcid1, sizeof(default_nfcid1));
+ NRFX_ASSERT(err_code == NRFX_SUCCESS);
+ nrf_nfct_nfcid1_set(default_nfcid1, NRF_NFCT_SENSRES_NFCID1_SIZE_DEFAULT);
+ }
+ else
+ {
+ return err_code;
+ }
+
+ m_nfct_cb.state = NRFX_DRV_STATE_INITIALIZED;
+
+ NRFX_LOG_INFO("Initialized");
+ return err_code;
+}
+
+void nrfx_nfct_uninit(void)
+{
+ nrfx_nfct_disable();
+
+#ifdef USE_TIMER_WORKAROUND
+ /* Initialize Timer module as the workaround for NFCT HW issues. */
+ #ifdef NRF52840_XXAA
+ if (!m_nrf52840.eng_a)
+ #endif // NRF52840_XXAA
+ {
+ nrfx_timer_uninit(&m_timer_workaround.timer);
+ }
+#endif // USE_TIMER_WORKAROUND
+
+ m_nfct_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
+}
+
+void nrfx_nfct_enable(void)
+{
+ nrf_nfct_error_status_clear(NRFX_NFCT_ERROR_STATUS_ALL_MASK);
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_SENSE);
+
+ NRFX_IRQ_PENDING_CLEAR(NFCT_IRQn);
+ NRFX_IRQ_PRIORITY_SET(NFCT_IRQn, NRFX_NFCT_CONFIG_IRQ_PRIORITY);
+ NRFX_IRQ_ENABLE(NFCT_IRQn);
+
+ NRFX_LOG_INFO("Start");
+}
+
+void nrfx_nfct_disable(void)
+{
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_DISABLE);
+
+ NRFX_LOG_INFO("Stop");
+}
+
+bool nrfx_nfct_field_check(void)
+{
+ uint32_t const field_state = nrf_nfct_field_status_get();
+
+ if (((field_state & NRF_NFCT_FIELD_STATE_PRESENT_MASK) == 0) &&
+ ((field_state & NRF_NFCT_FIELD_STATE_LOCK_MASK) == 0))
+ {
+ // Field is not active
+ return false;
+ }
+
+ return true;
+}
+
+void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_tx_data)
+{
+ NRFX_ASSERT(p_tx_data);
+
+ nrf_nfct_rxtx_buffer_set((uint8_t *) p_tx_data->p_data, p_tx_data->data_size);
+
+ nrfx_nfct_rxtx_int_enable(NRFX_NFCT_RX_INT_MASK);
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_ENABLERXDATA);
+}
+
+nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
+ nrf_nfct_frame_delay_mode_t delay_mode)
+{
+ NRFX_ASSERT(p_tx_data);
+ NRFX_ASSERT(p_tx_data->p_data);
+
+ if (p_tx_data->data_size == 0)
+ {
+ return NRFX_ERROR_INVALID_LENGTH;
+ }
+
+ nrf_nfct_rxtx_buffer_set((uint8_t *) p_tx_data->p_data, p_tx_data->data_size);
+ nrf_nfct_tx_bits_set(NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size));
+ nrf_nfct_frame_delay_mode_set((nrf_nfct_frame_delay_mode_t) delay_mode);
+
+ nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK);
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_STARTTX);
+
+ NRFX_LOG_INFO("Tx start");
+ return NRFX_SUCCESS;
+}
+
+void nrfx_nfct_state_force(nrfx_nfct_state_t state)
+{
+#ifdef NRF52840_XXAA
+ if ((m_nrf52840.eng_bc) && (state == NRFX_NFCT_STATE_ACTIVATED))
+ {
+ m_timer_workaround.is_hfclk_on = true;
+ nrfx_nfct_activate_check();
+ }
+#endif
+ {
+ nrf_nfct_task_trigger((nrf_nfct_task_t) state);
+ }
+}
+
+void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state)
+{
+ if (sub_state == NRFX_NFCT_ACTIVE_STATE_DEFAULT)
+ {
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+ if (((*(uint32_t volatile *)(0x40005420)) & 0x1UL) == (1UL))
+#else
+ if (nrf_nfct_sleep_state_get() == NRF_NFCT_SLEEP_STATE_SLEEP_A)
+#endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+ {
+ // Default state is SLEEP_A
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_GOSLEEP);
+ }
+ else
+ {
+ // Default state is IDLE
+ nrf_nfct_task_trigger(NRF_NFCT_TASK_GOIDLE);
+ }
+ }
+ else
+ {
+ nrf_nfct_task_trigger((nrf_nfct_task_t) sub_state);
+ }
+
+ /* Disable TX/RX here (will be enabled at SELECTED) */
+ nrf_nfct_int_disable(NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
+}
+
+nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param)
+{
+ NRFX_ASSERT(p_param);
+
+ switch (p_param->id)
+ {
+ case NRFX_NFCT_PARAM_ID_FDT:
+ {
+ uint32_t delay = p_param->data.fdt;
+ uint32_t delay_thr = NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk;
+
+#ifdef NRF52840_XXAA
+ delay_thr = (m_nrf52840.eng_a) ? NRFX_NFCT_FRAMEDELAYMAX_52840S : delay_thr;
+#endif // NRF52840_XXAA
+
+ // Delay validation.
+ if (delay > (delay_thr + NRFX_NFCT_FWT_MAX_DIFF))
+ {
+ return NRFX_ERROR_INVALID_PARAM;
+ }
+
+ delay = (delay > delay_thr) ? delay_thr : delay;
+ nrf_nfct_frame_delay_max_set(delay);
+ break;
+ }
+
+ case NRFX_NFCT_PARAM_ID_SEL_RES:
+ if (p_param->data.sel_res_protocol > NRF_NFCT_SELRES_PROTOCOL_NFCDEP_T4AT)
+ {
+ return NRFX_ERROR_INVALID_PARAM;
+ }
+
+ nrf_nfct_selres_protocol_set((nrf_nfct_selres_protocol_t) p_param->data.sel_res_protocol);
+ break;
+
+ case NRFX_NFCT_PARAM_ID_NFCID1:
+ {
+ nrf_nfct_sensres_nfcid1_size_t id_size_mask;
+
+ id_size_mask = nrf_nfct_nfcid1_size_to_sensres_size(p_param->data.nfcid1.id_size);
+ nrf_nfct_nfcid1_set(p_param->data.nfcid1.p_id, id_size_mask);
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return NRFX_SUCCESS;
+}
+
+nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
+ uint32_t nfcid1_buff_len)
+{
+ if ((nfcid1_buff_len != NRFX_NFCT_NFCID1_SINGLE_SIZE) &&
+ (nfcid1_buff_len != NRFX_NFCT_NFCID1_DOUBLE_SIZE) &&
+ (nfcid1_buff_len != NRFX_NFCT_NFCID1_TRIPLE_SIZE))
+ {
+ return NRFX_ERROR_INVALID_LENGTH;
+ }
+
+ uint32_t nfc_tag_header0 = NRF_FICR->NFC.TAGHEADER0;
+ uint32_t nfc_tag_header1 = NRF_FICR->NFC.TAGHEADER1;
+ uint32_t nfc_tag_header2 = NRF_FICR->NFC.TAGHEADER2;
+
+ p_nfcid1_buff[0] = (uint8_t) (nfc_tag_header0 >> 0);
+ p_nfcid1_buff[1] = (uint8_t) (nfc_tag_header0 >> 8);
+ p_nfcid1_buff[2] = (uint8_t) (nfc_tag_header0 >> 16);
+ p_nfcid1_buff[3] = (uint8_t) (nfc_tag_header1 >> 0);
+
+ if (nfcid1_buff_len != NRFX_NFCT_NFCID1_SINGLE_SIZE)
+ {
+ p_nfcid1_buff[4] = (uint8_t) (nfc_tag_header1 >> 8);
+ p_nfcid1_buff[5] = (uint8_t) (nfc_tag_header1 >> 16);
+ p_nfcid1_buff[6] = (uint8_t) (nfc_tag_header1 >> 24);
+
+ if (nfcid1_buff_len == NRFX_NFCT_NFCID1_TRIPLE_SIZE)
+ {
+ p_nfcid1_buff[7] = (uint8_t) (nfc_tag_header2 >> 0);
+ p_nfcid1_buff[8] = (uint8_t) (nfc_tag_header2 >> 8);
+ p_nfcid1_buff[9] = (uint8_t) (nfc_tag_header2 >> 16);
+ }
+ /* Begin: Bugfix for FTPAN-181. */
+ /* Workaround for wrong value in NFCID1. Value 0x88 cannot be used as byte 3
+ of a double-size NFCID1, according to the NFC Forum Digital Protocol specification. */
+ else if (p_nfcid1_buff[3] == 0x88)
+ {
+ p_nfcid1_buff[3] |= 0x11;
+ }
+ /* End: Bugfix for FTPAN-181 */
+ }
+
+ return NRFX_SUCCESS;
+}
+
+void nrfx_nfct_autocolres_enable(void)
+{
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+ (*(uint32_t *)(0x4000559C)) &= (~(0x1UL));
+#else
+ nrf_nfct_autocolres_enable();
+#endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+}
+
+void nrfx_nfct_autocolres_disable(void)
+{
+#if defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+ (*(uint32_t *)(0x4000559C)) |= (0x1UL);
+#else
+ nrf_nfct_autocolres_disable();
+#endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB)
+}
+
+void nrfx_nfct_irq_handler(void)
+{
+ nrfx_nfct_field_state_t current_field = NRFX_NFC_FIELD_STATE_NONE;
+
+ if (NRFX_NFCT_EVT_ACTIVE(FIELDDETECTED))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_FIELDDETECTED);
+ current_field = NRFX_NFC_FIELD_STATE_ON;
+
+ NRFX_LOG_DEBUG("Field detected");
+ }
+
+#if !defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+ if (NRFX_NFCT_EVT_ACTIVE(FIELDLOST))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_FIELDLOST);
+ current_field = (current_field == NRFX_NFC_FIELD_STATE_NONE) ?
+ NRFX_NFC_FIELD_STATE_OFF : NRFX_NFC_FIELD_STATE_UNKNOWN;
+
+ NRFX_LOG_DEBUG("Field lost");
+ }
+#endif //!defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+
+ /* Perform actions if any FIELD event is active */
+ if (current_field != NRFX_NFC_FIELD_STATE_NONE)
+ {
+ nrfx_nfct_field_event_handler(current_field);
+ }
+
+ if (NRFX_NFCT_EVT_ACTIVE(RXFRAMEEND))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_RXFRAMEEND);
+
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_RX_FRAMEEND
+ };
+
+ /* Take into account only the number of whole bytes. */
+ nfct_evt.params.rx_frameend.rx_status = 0;
+ nfct_evt.params.rx_frameend.rx_data.p_data = nrf_nfct_rxtx_buffer_get();
+ nfct_evt.params.rx_frameend.rx_data.data_size = NRFX_NFCT_BITS_TO_BYTES(nrf_nfct_rx_bits_get(true));
+
+ if (NRFX_NFCT_EVT_ACTIVE(RXERROR))
+ {
+ nfct_evt.params.rx_frameend.rx_status =
+ (nrf_nfct_rx_frame_status_get() & NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK);
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_RXERROR);
+
+ NRFX_LOG_DEBUG("Rx error (0x%x)", (unsigned int) nfct_evt.params.rx_frameend.rx_status);
+
+ /* Clear rx frame status */
+ nrf_nfct_rx_frame_status_clear(NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK);
+ }
+
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+
+ /* Clear TXFRAMESTART EVENT so it can be checked in hal_nfc_send */
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMESTART);
+
+ NRFX_LOG_DEBUG("Rx fend");
+ }
+
+ if (NRFX_NFCT_EVT_ACTIVE(TXFRAMEEND))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMEEND);
+
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_TX_FRAMEEND
+ };
+
+ /* Disable TX END event to ignore frame transmission other than READ response */
+ nrf_nfct_int_disable(NRFX_NFCT_TX_INT_MASK);
+
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+
+ NRFX_LOG_DEBUG("Tx fend");
+ }
+
+ if (NRFX_NFCT_EVT_ACTIVE(SELECTED))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_SELECTED);
+ /* Clear also RX END and RXERROR events because SW does not take care of
+ commands that were received before selecting the tag. */
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_RXFRAMEEND);
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_RXERROR);
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMESTART);
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMEEND);
+
+ /* At this point any previous error status can be ignored. */
+ nrf_nfct_rx_frame_status_clear(NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK);
+ nrf_nfct_error_status_clear(NRFX_NFCT_ERROR_STATUS_ALL_MASK);
+
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_SELECTED
+ };
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+
+ NRFX_LOG_DEBUG("Selected");
+ }
+
+ if (NRFX_NFCT_EVT_ACTIVE(ERROR))
+ {
+ uint32_t err_status = nrf_nfct_error_status_get();
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_ERROR);
+
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_ERROR
+ };
+
+ /* Clear FRAMEDELAYTIMEOUT error (expected HW behaviour) when SLP_REQ command was received. */
+ if (err_status & NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK)
+ {
+ nrf_nfct_error_status_clear(NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK);
+
+ nfct_evt.params.error.reason = NRFX_NFCT_ERROR_FRAMEDELAYTIMEOUT;
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ }
+
+ /* Report any other error. */
+ err_status &= ~NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK;
+ if (err_status)
+ {
+ NRFX_LOG_DEBUG("Error (0x%x)", (unsigned int) err_status);
+ }
+
+ /* Clear error status. */
+ nrf_nfct_error_status_clear(NRFX_NFCT_ERROR_STATUS_ALL_MASK);
+ }
+
+ if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART))
+ {
+ nrf_nfct_event_clear(NRF_NFCT_EVENT_TXFRAMESTART);
+
+ if (m_nfct_cb.config.cb != NULL)
+ {
+ nrfx_nfct_evt_t nfct_evt;
+
+ nfct_evt.evt_id = NRFX_NFCT_EVT_TX_FRAMESTART;
+ nfct_evt.params.tx_framestart.tx_data.p_data = nrf_nfct_rxtx_buffer_get();
+ nfct_evt.params.tx_framestart.tx_data.data_size = NRFX_NFCT_BITS_TO_BYTES(nrf_nfct_tx_bits_get());
+
+ m_nfct_cb.config.cb(&nfct_evt);
+ }
+ }
+}
+
+#endif // NRFX_CHECK(NRFX_NFCT_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
index c3eaf16393..98eda0530c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
index ccecdc4f14..194ce60f2e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -37,6 +37,7 @@
#if NRFX_CHECK(NRFX_CLOCK_ENABLED)
extern bool nrfx_clock_irq_enabled;
+extern void nrfx_clock_irq_handler(void);
#endif
/**
@@ -294,4 +295,22 @@ void nrfx_power_irq_handler(void)
#endif
}
+#if NRFX_CHECK(NRFX_CLOCK_ENABLED)
+/*
+ * If both POWER and CLOCK drivers are used, a common IRQ handler function must
+ * be used that calls the handlers in these two drivers. This is because these
+ * two peripherals share one interrupt.
+ * This function is located here, not in a separate nrfx_power_clock.c file,
+ * so that it does not end up as the only symbol in a separate object when
+ * a library with nrfx is created. In such case, forcing a linker to use this
+ * function instead of another one defined as weak will require additional
+ * actions, and might be even impossible.
+ */
+void nrfx_power_clock_irq_handler(void)
+{
+ nrfx_power_irq_handler();
+ nrfx_clock_irq_handler();
+}
+#endif
+
#endif // NRFX_CHECK(NRFX_POWER_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power_clock.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power_clock.c
deleted file mode 100644
index 1be9ade0d5..0000000000
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_power_clock.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/**
- * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <nrfx.h>
-#include <nrfx_power.h>
-#include <nrfx_clock.h>
-
-
-#if NRFX_CHECK(NRFX_POWER_ENABLED) && NRFX_CHECK(NRFX_CLOCK_ENABLED)
-void nrfx_power_clock_irq_handler(void)
-{
- nrfx_power_irq_handler();
- nrfx_clock_irq_handler();
-}
-#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
index 546aae7cf5..4dbffc9857 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_ppi.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -35,7 +35,7 @@
#include <nrfx_ppi.h>
-#define NRFX_LOG_MODULE_NAME PPI
+#define NRFX_LOG_MODULE PPI
#include <nrfx_log.h>
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
index d00ee50850..e57e488796 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
index e49c94d9fe..a86ff780be 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -107,12 +107,15 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
m_qdec_event_handler = event_handler;
nrf_qdec_sampleper_set(p_config->sampleper);
- nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL);
+ if (p_config->pselled != NRF_QDEC_LED_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL);
+ nrf_qdec_ledpre_set(p_config->ledpre);
+ nrf_qdec_ledpol_set(p_config->ledpol);
+ }
nrf_qdec_pio_assign(p_config->psela, p_config->pselb, p_config->pselled);
- nrf_qdec_ledpre_set(p_config->ledpre);
- nrf_qdec_ledpol_set(p_config->ledpol);
nrf_qdec_shorts_enable(NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK);
if (p_config->dbfen)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
index 146cdd034c..8eae4d75b8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qspi.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -254,13 +254,13 @@ void nrfx_qspi_uninit(void)
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
- nrf_qspi_disable(NRF_QSPI);
-
nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE);
// Workaround for nRF52840 anomaly 122: Current consumption is too high.
*(volatile uint32_t *)0x40029054ul = 1ul;
+ nrf_qspi_disable(NRF_QSPI);
+
NRFX_IRQ_DISABLE(QSPI_IRQn);
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
index 3b33edaf04..5fc9d429f9 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rng.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
index 5546c10eb6..8acb4dbd9f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
index 99d29f6bbd..b9d3da6a66 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
index e7fe76151a..318fecb0bc 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -83,6 +83,10 @@
SPIM2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len))
+#if defined(NRF52840_XXAA) && (NRFX_CHECK(NRFX_SPIM3_ENABLED))
+// Enable workaround for nRF52840 anomaly 195 (SPIM3 continues to draw current after disable).
+#define USE_WORKAROUND_FOR_ANOMALY_195
+#endif
// Control block - driver instance local data.
typedef struct
@@ -171,14 +175,13 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
}
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
-
- // Currently, only SPIM3 in nRF52840 supports the extended features. Other instances must be checked.
+ // Currently, only SPIM3 in nRF52840 supports the extended features.
+ // Other instances must be checked.
if ((p_instance->drv_inst_idx != NRFX_SPIM3_INST_IDX) &&
- ((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) ||
- (p_config->frequency == NRF_SPIM_FREQ_16M) ||
- (p_config->frequency == NRF_SPIM_FREQ_32M) ||
- (p_config->rx_delay != 0x00) ||
- (p_config->use_hw_ss)))
+ ((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) ||
+ (p_config->frequency == NRF_SPIM_FREQ_16M) ||
+ (p_config->frequency == NRF_SPIM_FREQ_32M) ||
+ (p_config->use_hw_ss)))
{
err_code = NRFX_ERROR_NOT_SUPPORTED;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
@@ -261,8 +264,13 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
{
miso_pin = NRF_SPIM_PIN_NOT_CONNECTED;
}
- m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin;
+ p_cb->miso_pin = p_config->miso_pin;
// - Slave Select (optional) - output with initial value 1 (inactive).
+
+ // 'p_cb->ss_pin' variable is used during transfers to check if SS pin should be toggled,
+ // so this field needs to be initialized even if the pin is not used.
+ p_cb->ss_pin = p_config->ss_pin;
+
if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
{
if (p_config->ss_active_high)
@@ -277,7 +285,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
if (p_config->use_hw_ss)
{
- m_cb[p_instance->drv_inst_idx].use_hw_ss = p_config->use_hw_ss;
+ p_cb->use_hw_ss = p_config->use_hw_ss;
nrf_spim_csn_configure(p_spim,
p_config->ss_pin,
(p_config->ss_active_high == true ?
@@ -285,8 +293,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
p_config->ss_duration);
}
#endif
- m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
- m_cb[p_instance->drv_inst_idx].ss_active_high = p_config->ss_active_high;
+ p_cb->ss_active_high = p_config->ss_active_high;
}
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
@@ -361,6 +368,13 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance)
}
nrf_spim_disable(p_spim);
+#ifdef USE_WORKAROUND_FOR_ANOMALY_195
+ if (p_spim == NRF_SPIM3)
+ {
+ *(volatile uint32_t *)0x4002F004 = 1;
+ }
+#endif
+
#if NRFX_CHECK(NRFX_PRS_ENABLED)
nrfx_prs_release(p_instance->p_reg);
#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
index 416135b60f..b8cbde9a77 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2013 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_swi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_swi.c
index 5d8b4d24e6..e59a9c9dff 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_swi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_swi.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
index 6998182a42..6854baffd5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_systick.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
index d9d2d569b5..b49e9585f3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
index d5f0a1c9a5..89d3a77bde 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -73,7 +73,7 @@
NRF_GPIO_PIN_S0D1, \
NRF_GPIO_PIN_NOSENSE)
-#define HW_TIMEOUT 10000
+#define HW_TIMEOUT 100000
// Control block - driver instance local data.
typedef struct
@@ -84,13 +84,13 @@ typedef struct
nrfx_twi_xfer_desc_t xfer_desc;
uint32_t flags;
uint8_t * p_curr_buf;
- uint8_t curr_length;
+ size_t curr_length;
bool curr_no_stop;
nrfx_drv_state_t state;
bool error;
volatile bool busy;
bool repeated;
- uint8_t bytes_transferred;
+ size_t bytes_transferred;
bool hold_bus_uninit;
} twi_control_block_t;
@@ -245,8 +245,8 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance)
static bool twi_send_byte(NRF_TWI_Type * p_twi,
uint8_t const * p_data,
- uint8_t length,
- uint8_t * p_bytes_transferred,
+ size_t length,
+ size_t * p_bytes_transferred,
bool no_stop)
{
if (*p_bytes_transferred < length)
@@ -271,8 +271,8 @@ static bool twi_send_byte(NRF_TWI_Type * p_twi,
static void twi_receive_byte(NRF_TWI_Type * p_twi,
uint8_t * p_data,
- uint8_t length,
- uint8_t * p_bytes_transferred)
+ size_t length,
+ size_t * p_bytes_transferred)
{
if (*p_bytes_transferred < length)
{
@@ -295,9 +295,9 @@ static void twi_receive_byte(NRF_TWI_Type * p_twi,
static bool twi_transfer(NRF_TWI_Type * p_twi,
bool * p_error,
- uint8_t * p_bytes_transferred,
+ size_t * p_bytes_transferred,
uint8_t * p_data,
- uint8_t length,
+ size_t length,
bool no_stop)
{
bool do_stop_check = ((*p_error) || ((*p_bytes_transferred) == length));
@@ -367,7 +367,7 @@ static bool twi_transfer(NRF_TWI_Type * p_twi,
static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
NRF_TWI_Type * p_twi,
uint8_t const * p_data,
- uint8_t length,
+ size_t length,
bool no_stop)
{
nrfx_err_t ret_code = NRFX_SUCCESS;
@@ -435,7 +435,7 @@ static nrfx_err_t twi_tx_start_transfer(twi_control_block_t * p_cb,
static nrfx_err_t twi_rx_start_transfer(twi_control_block_t * p_cb,
NRF_TWI_Type * p_twi,
uint8_t const * p_data,
- uint8_t length)
+ size_t length)
{
nrfx_err_t ret_code = NRFX_SUCCESS;
volatile int32_t hw_timeout;
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
index fdfaca6e6a..8126bef63c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -373,6 +373,7 @@ __STATIC_INLINE nrfx_err_t twim_xfer(twim_control_block_t * p_cb,
nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STARTRX_MASK |
NRF_TWIM_SHORT_LASTRX_STOP_MASK);
p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+ nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
break;
case NRFX_TWIM_XFER_TX:
nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
index 47baa1c895..6f0c037025 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
index 43a25151c3..203fe38825 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uart.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
index bc4fcbe97b..39d0c2835b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -488,6 +488,14 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance)
void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance)
{
+ uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+
+ // Short between ENDRX event and STARTRX task must be disabled before
+ // aborting transmission.
+ if (p_cb->rx_secondary_buffer_length != 0)
+ {
+ nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
+ }
nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
NRFX_LOG_INFO("RX transaction aborted.");
}
@@ -520,7 +528,7 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
// will not be equal to the buffer length. Interrupted transfer is ignored.
if (amount == p_cb->rx_buffer_length)
{
- if (p_cb->rx_secondary_buffer_length)
+ if (p_cb->rx_secondary_buffer_length != 0)
{
uint8_t * p_data = p_cb->p_rx_buffer;
nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
@@ -540,9 +548,13 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO))
{
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO);
- if (p_cb->rx_buffer_length)
+
+ if (p_cb->rx_buffer_length != 0)
{
p_cb->rx_buffer_length = 0;
+ // In case of using double-buffered reception both variables storing buffer length
+ // have to be cleared to prevent incorrect behaviour of the driver.
+ p_cb->rx_secondary_buffer_length = 0;
rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer);
}
}
@@ -550,7 +562,7 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX))
{
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX);
- if (p_cb->tx_buffer_length)
+ if (p_cb->tx_buffer_length != 0)
{
tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
new file mode 100644
index 0000000000..5663e02f70
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
@@ -0,0 +1,2352 @@
+/*
+ * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <nrfx.h>
+
+#if NRFX_CHECK(NRFX_USBD_ENABLED)
+
+#include <nrfx_usbd.h>
+#include "nrfx_usbd_errata.h"
+#include <nrfx_systick.h> /* Marker to delete when not required anymore: >> NRFX_USBD_ERRATA_ENABLE << */
+#include <string.h>
+
+#define NRFX_LOG_MODULE USBD
+#include <nrfx_log.h>
+
+#ifndef NRFX_USBD_EARLY_DMA_PROCESS
+/* Try to process DMA request when endpoint transmission has been detected
+ * and just after last EasyDMA has been processed.
+ * It speeds up the transmission a little (about 10% measured)
+ * with a cost of more CPU power used.
+ */
+#define NRFX_USBD_EARLY_DMA_PROCESS 1
+#endif
+
+#ifndef NRFX_USBD_PROTO1_FIX_DEBUG
+/* Debug information when events are fixed*/
+#define NRFX_USBD_PROTO1_FIX_DEBUG 1
+#endif
+
+#define NRFX_USBD_LOG_PROTO1_FIX_PRINTF(...) \
+ do{ \
+ if (NRFX_USBD_PROTO1_FIX_DEBUG){ NRFX_LOG_DEBUG(__VA_ARGS__); }\
+ } while (0)
+
+#ifndef NRFX_USBD_STARTED_EV_ENABLE
+#define NRFX_USBD_STARTED_EV_ENABLE 0
+#endif
+
+#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
+#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+#ifndef NRFX_USBD_ISO_DEBUG
+/* Also generate information about ISOCHRONOUS events and transfers.
+ * Turn this off if no ISOCHRONOUS transfers are going to be debugged and this
+ * option generates a lot of useless messages. */
+#define NRFX_USBD_ISO_DEBUG 1
+#endif
+
+#ifndef NRFX_USBD_FAILED_TRANSFERS_DEBUG
+/* Also generate debug information for failed transfers.
+ * It might be useful but may generate a lot of useless debug messages
+ * in some library usages (for example when transfer is generated and the
+ * result is used to check whatever endpoint was busy. */
+#define NRFX_USBD_FAILED_TRANSFERS_DEBUG 1
+#endif
+
+#ifndef NRFX_USBD_DMAREQ_PROCESS_DEBUG
+/* Generate additional messages that mark the status inside
+ * @ref usbd_dmareq_process.
+ * It is useful to debug library internals but may generate a lot of
+ * useless debug messages. */
+#define NRFX_USBD_DMAREQ_PROCESS_DEBUG 1
+#endif
+
+
+/**
+ * @defgroup nrfx_usbd_int USB Device driver internal part
+ * @internal
+ * @ingroup nrfx_usbd
+ *
+ * This part contains auxiliary internal macros, variables and functions.
+ * @{
+ */
+
+/**
+ * @brief Assert endpoint number validity.
+ *
+ * Internal macro to be used during program creation in debug mode.
+ * Generates assertion if endpoint number is not valid.
+ *
+ * @param ep Endpoint number to validity check.
+ */
+#define NRFX_USBD_ASSERT_EP_VALID(ep) NRFX_ASSERT( \
+ ((NRF_USBD_EPIN_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPIN_CNT )) \
+ || \
+ (NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRF_USBD_EPOUT_CNT))) \
+);
+
+/**
+ * @brief Lowest position of bit for IN endpoint.
+ *
+ * The first bit position corresponding to IN endpoint.
+ * @sa ep2bit bit2ep
+ */
+#define NRFX_USBD_EPIN_BITPOS_0 0
+
+/**
+ * @brief Lowest position of bit for OUT endpoint.
+ *
+ * The first bit position corresponding to OUT endpoint
+ * @sa ep2bit bit2ep
+ */
+#define NRFX_USBD_EPOUT_BITPOS_0 16
+
+/**
+ * @brief Input endpoint bits mask.
+ */
+#define NRFX_USBD_EPIN_BIT_MASK (0xFFFFU << NRFX_USBD_EPIN_BITPOS_0)
+
+/**
+ * @brief Output endpoint bits mask.
+ */
+#define NRFX_USBD_EPOUT_BIT_MASK (0xFFFFU << NRFX_USBD_EPOUT_BITPOS_0)
+
+/**
+ * @brief Isochronous endpoint bit mask
+ */
+#define USBD_EPISO_BIT_MASK \
+ ((1U << NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT8)) | \
+ (1U << NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN8)))
+
+/**
+ * @brief Auxiliary macro to change EP number into bit position.
+ *
+ * This macro is used by @ref ep2bit function but also for statically check
+ * the bitpos values integrity during compilation.
+ *
+ * @param[in] ep Endpoint number.
+ * @return Endpoint bit position.
+ */
+#define NRFX_USBD_EP_BITPOS(ep) \
+ ((NRF_USBD_EPIN_CHECK(ep) ? NRFX_USBD_EPIN_BITPOS_0 : NRFX_USBD_EPOUT_BITPOS_0) \
+ + NRF_USBD_EP_NR_GET(ep))
+
+/**
+ * @brief Helper macro for creating an endpoint transfer event.
+ *
+ * @param[in] name Name of the created transfer event variable.
+ * @param[in] endpoint Endpoint number.
+ * @param[in] ep_stat Endpoint state to report.
+ *
+ * @return Initialized event constant variable.
+ */
+#define NRFX_USBD_EP_TRANSFER_EVENT(name, endpont, ep_stat) \
+ const nrfx_usbd_evt_t name = { \
+ NRFX_USBD_EVT_EPTRANSFER, \
+ .data = { \
+ .eptransfer = { \
+ .ep = endpont, \
+ .status = ep_stat \
+ } \
+ } \
+ }
+
+/* Check it the bit positions values match defined DATAEPSTATUS bit positions */
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN1) == USBD_EPDATASTATUS_EPIN1_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN2) == USBD_EPDATASTATUS_EPIN2_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN3) == USBD_EPDATASTATUS_EPIN3_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN4) == USBD_EPDATASTATUS_EPIN4_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN5) == USBD_EPDATASTATUS_EPIN5_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN6) == USBD_EPDATASTATUS_EPIN6_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPIN7) == USBD_EPDATASTATUS_EPIN7_Pos );
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT1) == USBD_EPDATASTATUS_EPOUT1_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT2) == USBD_EPDATASTATUS_EPOUT2_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT3) == USBD_EPDATASTATUS_EPOUT3_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT4) == USBD_EPDATASTATUS_EPOUT4_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT5) == USBD_EPDATASTATUS_EPOUT5_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT6) == USBD_EPDATASTATUS_EPOUT6_Pos);
+NRFX_STATIC_ASSERT(NRFX_USBD_EP_BITPOS(NRFX_USBD_EPOUT7) == USBD_EPDATASTATUS_EPOUT7_Pos);
+
+
+/**
+ * @brief Current driver state.
+ */
+static nrfx_drv_state_t m_drv_state = NRFX_DRV_STATE_UNINITIALIZED;
+
+/**
+ * @brief Event handler for the driver.
+ *
+ * Event handler that would be called on events.
+ *
+ * @note Currently it cannot be null if any interrupt is activated.
+ */
+static nrfx_usbd_event_handler_t m_event_handler;
+
+/**
+ * @brief Detected state of the bus.
+ *
+ * Internal state changed in interrupts handling when
+ * RESUME or SUSPEND event is processed.
+ *
+ * Values:
+ * - true - bus suspended
+ * - false - ongoing normal communication on the bus
+ *
+ * @note This is only the bus state and does not mean that the peripheral is in suspend state.
+ */
+static volatile bool m_bus_suspend;
+
+/**
+ * @brief Internal constant that contains interrupts disabled in suspend state.
+ *
+ * Internal constant used in @ref nrfx_usbd_suspend_irq_config and @ref nrfx_usbd_active_irq_config
+ * functions.
+ */
+static const uint32_t m_irq_disabled_in_suspend =
+ NRF_USBD_INT_ENDEPIN0_MASK |
+ NRF_USBD_INT_EP0DATADONE_MASK |
+ NRF_USBD_INT_ENDEPOUT0_MASK |
+ NRF_USBD_INT_EP0SETUP_MASK |
+ NRF_USBD_INT_DATAEP_MASK;
+
+/**
+ * @brief Direction of last received Setup transfer.
+ *
+ * This variable is used to redirect internal setup data event
+ * into selected endpoint (IN or OUT).
+ */
+static nrfx_usbd_ep_t m_last_setup_dir;
+
+/**
+ * @brief Mark endpoint readiness for DMA transfer.
+ *
+ * Bits in this variable are cleared and set in interrupts.
+ * 1 means that endpoint is ready for DMA transfer.
+ * 0 means that DMA transfer cannot be performed on selected endpoint.
+ */
+static uint32_t m_ep_ready;
+
+/**
+ * @brief Mark endpoint with prepared data to transfer by DMA.
+ *
+ * This variable can be from any place in the code (interrupt or main thread).
+ * It would be cleared only from USBD interrupt.
+ *
+ * Mask prepared USBD data for transmission.
+ * It is cleared when no more data to transmit left.
+ */
+static uint32_t m_ep_dma_waiting;
+
+/**
+ * @brief Current EasyDMA state.
+ *
+ * Single flag, updated only inside interrupts, that marks current EasyDMA state.
+ * In USBD there is only one DMA channel working in background, and new transfer
+ * cannot be started when there is ongoing transfer on any other channel.
+ */
+static bool m_dma_pending;
+
+/**
+ * @brief Simulated data EP status bits required for errata 104.
+ *
+ * Marker to delete when not required anymore: >> NRFX_USBD_ERRATA_ENABLE <<.
+ */
+static uint32_t m_simulated_dataepstatus;
+
+/**
+ * @brief The structure that would hold transfer configuration to every endpoint
+ *
+ * The structure that holds all the data required by the endpoint to proceed
+ * with LIST functionality and generate quick callback directly when data
+ * buffer is ready.
+ */
+typedef struct
+{
+ nrfx_usbd_handler_t handler; //!< Handler for current transfer, function pointer.
+ void * p_context; //!< Context for transfer handler.
+ size_t transfer_cnt; //!< Number of transferred bytes in the current transfer.
+ uint16_t max_packet_size; //!< Configured endpoint size.
+ nrfx_usbd_ep_status_t status; //!< NRFX_SUCCESS or error code, never NRFX_ERROR_BUSY - this one is calculated.
+} usbd_ep_state_t;
+
+/**
+ * @brief The array of transfer configurations for the endpoints.
+ *
+ * The status of the transfer on each endpoint.
+ */
+static struct
+{
+ usbd_ep_state_t ep_out[NRF_USBD_EPOUT_CNT]; //!< Status for OUT endpoints.
+ usbd_ep_state_t ep_in [NRF_USBD_EPIN_CNT ]; //!< Status for IN endpoints.
+} m_ep_state;
+
+/**
+ * @brief Status variables for integrated feeders.
+ *
+ * Current status for integrated feeders (IN transfers).
+ * Integrated feeders are used for default transfers:
+ * 1. Simple RAM transfer.
+ * 2. Simple flash transfer.
+ * 3. RAM transfer with automatic ZLP.
+ * 4. Flash transfer with automatic ZLP.
+ */
+nrfx_usbd_transfer_t m_ep_feeder_state[NRF_USBD_EPIN_CNT];
+
+/**
+ * @brief Status variables for integrated consumers.
+ *
+ * Current status for integrated consumers.
+ * Currently one type of transfer is supported:
+ * 1. Transfer to RAM.
+ *
+ * Transfer is finished automatically when received data block is smaller
+ * than the endpoint buffer or all the required data is received.
+ */
+nrfx_usbd_transfer_t m_ep_consumer_state[NRF_USBD_EPOUT_CNT];
+
+
+/**
+ * @brief Buffer used to send data directly from FLASH.
+ *
+ * This is internal buffer that would be used to emulate the possibility
+ * to transfer data directly from FLASH.
+ * We do not have to care about the source of data when calling transfer functions.
+ *
+ * We do not need more buffers that one, because only one transfer can be pending
+ * at once.
+ */
+static uint32_t m_tx_buffer[NRFX_CEIL_DIV(
+ NRFX_USBD_FEEDER_BUFFER_SIZE, sizeof(uint32_t))];
+
+/* Early declaration. Documentation above definition. */
+static void usbd_dmareq_process(void);
+
+
+/**
+ * @brief Change endpoint number to endpoint event code.
+ *
+ * @param ep Endpoint number.
+ *
+ * @return Connected endpoint event code.
+ *
+ * Marker to delete when not required anymore: >> NRFX_USBD_ERRATA_ENABLE <<.
+ */
+static inline nrf_usbd_event_t nrfx_usbd_ep_to_endevent(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+
+ static const nrf_usbd_event_t epin_endev[] =
+ {
+ NRF_USBD_EVENT_ENDEPIN0,
+ NRF_USBD_EVENT_ENDEPIN1,
+ NRF_USBD_EVENT_ENDEPIN2,
+ NRF_USBD_EVENT_ENDEPIN3,
+ NRF_USBD_EVENT_ENDEPIN4,
+ NRF_USBD_EVENT_ENDEPIN5,
+ NRF_USBD_EVENT_ENDEPIN6,
+ NRF_USBD_EVENT_ENDEPIN7,
+ NRF_USBD_EVENT_ENDISOIN0
+ };
+ static const nrf_usbd_event_t epout_endev[] =
+ {
+ NRF_USBD_EVENT_ENDEPOUT0,
+ NRF_USBD_EVENT_ENDEPOUT1,
+ NRF_USBD_EVENT_ENDEPOUT2,
+ NRF_USBD_EVENT_ENDEPOUT3,
+ NRF_USBD_EVENT_ENDEPOUT4,
+ NRF_USBD_EVENT_ENDEPOUT5,
+ NRF_USBD_EVENT_ENDEPOUT6,
+ NRF_USBD_EVENT_ENDEPOUT7,
+ NRF_USBD_EVENT_ENDISOOUT0
+ };
+
+ return (NRF_USBD_EPIN_CHECK(ep) ? epin_endev : epout_endev)[NRF_USBD_EP_NR_GET(ep)];
+}
+
+
+/**
+ * @brief Get interrupt mask for selected endpoint.
+ *
+ * @param[in] ep Endpoint number.
+ *
+ * @return Interrupt mask related to the EasyDMA transfer end for the
+ * chosen endpoint.
+ */
+static inline uint32_t nrfx_usbd_ep_to_int(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+
+ static const uint8_t epin_bitpos[] =
+ {
+ USBD_INTEN_ENDEPIN0_Pos,
+ USBD_INTEN_ENDEPIN1_Pos,
+ USBD_INTEN_ENDEPIN2_Pos,
+ USBD_INTEN_ENDEPIN3_Pos,
+ USBD_INTEN_ENDEPIN4_Pos,
+ USBD_INTEN_ENDEPIN5_Pos,
+ USBD_INTEN_ENDEPIN6_Pos,
+ USBD_INTEN_ENDEPIN7_Pos,
+ USBD_INTEN_ENDISOIN_Pos
+ };
+ static const uint8_t epout_bitpos[] =
+ {
+ USBD_INTEN_ENDEPOUT0_Pos,
+ USBD_INTEN_ENDEPOUT1_Pos,
+ USBD_INTEN_ENDEPOUT2_Pos,
+ USBD_INTEN_ENDEPOUT3_Pos,
+ USBD_INTEN_ENDEPOUT4_Pos,
+ USBD_INTEN_ENDEPOUT5_Pos,
+ USBD_INTEN_ENDEPOUT6_Pos,
+ USBD_INTEN_ENDEPOUT7_Pos,
+ USBD_INTEN_ENDISOOUT_Pos
+ };
+
+ return 1UL << (NRF_USBD_EPIN_CHECK(ep) ? epin_bitpos : epout_bitpos)[NRF_USBD_EP_NR_GET(ep)];
+}
+
+/**
+ * @name Integrated feeders and consumers
+ *
+ * Internal, default functions for transfer processing.
+ * @{
+ */
+
+/**
+ * @brief Integrated consumer to RAM buffer.
+ *
+ * @param p_next See @ref nrfx_usbd_consumer_t documentation.
+ * @param p_context See @ref nrfx_usbd_consumer_t documentation.
+ * @param ep_size See @ref nrfx_usbd_consumer_t documentation.
+ * @param data_size See @ref nrfx_usbd_consumer_t documentation.
+ *
+ * @retval true Continue transfer.
+ * @retval false This was the last transfer.
+ */
+bool nrfx_usbd_consumer(
+ nrfx_usbd_ep_transfer_t * p_next,
+ void * p_context,
+ size_t ep_size,
+ size_t data_size)
+{
+ nrfx_usbd_transfer_t * p_transfer = p_context;
+ NRFX_ASSERT(ep_size >= data_size);
+ NRFX_ASSERT((p_transfer->p_data.rx == NULL) ||
+ nrfx_is_in_ram(p_transfer->p_data.rx));
+
+ size_t size = p_transfer->size;
+ if (size < data_size)
+ {
+ NRFX_LOG_DEBUG("consumer: buffer too small: r: %u, l: %u", data_size, size);
+ /* Buffer size to small */
+ p_next->size = 0;
+ p_next->p_data = p_transfer->p_data;
+ }
+ else
+ {
+ p_next->size = data_size;
+ p_next->p_data = p_transfer->p_data;
+ size -= data_size;
+ p_transfer->size = size;
+ p_transfer->p_data.addr += data_size;
+ }
+ return (ep_size == data_size) && (size != 0);
+}
+
+/**
+ * @brief Integrated feeder from RAM source.
+ *
+ * @param[out] p_next See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in,out] p_context See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in] ep_size See @ref nrfx_usbd_feeder_t documentation.
+ *
+ * @retval true Continue transfer.
+ * @retval false This was the last transfer.
+ */
+bool nrfx_usbd_feeder_ram(
+ nrfx_usbd_ep_transfer_t * p_next,
+ void * p_context,
+ size_t ep_size)
+{
+ nrfx_usbd_transfer_t * p_transfer = p_context;
+ NRFX_ASSERT(nrfx_is_in_ram(p_transfer->p_data.tx));
+
+ size_t tx_size = p_transfer->size;
+ if (tx_size > ep_size)
+ {
+ tx_size = ep_size;
+ }
+
+ p_next->p_data = p_transfer->p_data;
+ p_next->size = tx_size;
+
+ p_transfer->size -= tx_size;
+ p_transfer->p_data.addr += tx_size;
+
+ return (p_transfer->size != 0);
+}
+
+/**
+ * @brief Integrated feeder from RAM source with ZLP.
+ *
+ * @param[out] p_next See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in,out] p_context See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in] ep_size See @ref nrfx_usbd_feeder_t documentation.
+ *
+ * @retval true Continue transfer.
+ * @retval false This was the last transfer.
+ */
+bool nrfx_usbd_feeder_ram_zlp(
+ nrfx_usbd_ep_transfer_t * p_next,
+ void * p_context,
+ size_t ep_size)
+{
+ nrfx_usbd_transfer_t * p_transfer = p_context;
+ NRFX_ASSERT(nrfx_is_in_ram(p_transfer->p_data.tx));
+
+ size_t tx_size = p_transfer->size;
+ if (tx_size > ep_size)
+ {
+ tx_size = ep_size;
+ }
+
+ p_next->p_data.tx = (tx_size == 0) ? NULL : p_transfer->p_data.tx;
+ p_next->size = tx_size;
+
+ p_transfer->size -= tx_size;
+ p_transfer->p_data.addr += tx_size;
+
+ return (tx_size != 0);
+}
+
+/**
+ * @brief Integrated feeder from a flash source.
+ *
+ * @param[out] p_next See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in,out] p_context See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in] ep_size See @ref nrfx_usbd_feeder_t documentation.
+ *
+ * @retval true Continue transfer.
+ * @retval false This was the last transfer.
+ */
+bool nrfx_usbd_feeder_flash(nrfx_usbd_ep_transfer_t * p_next, void * p_context, size_t ep_size)
+{
+ nrfx_usbd_transfer_t * p_transfer = p_context;
+ NRFX_ASSERT(!nrfx_is_in_ram(p_transfer->p_data.tx));
+
+ size_t tx_size = p_transfer->size;
+ void * p_buffer = nrfx_usbd_feeder_buffer_get();
+
+ if (tx_size > ep_size)
+ {
+ tx_size = ep_size;
+ }
+
+ NRFX_ASSERT(tx_size <= NRFX_USBD_FEEDER_BUFFER_SIZE);
+ memcpy(p_buffer, (p_transfer->p_data.tx), tx_size);
+
+ p_next->p_data.tx = p_buffer;
+ p_next->size = tx_size;
+
+ p_transfer->size -= tx_size;
+ p_transfer->p_data.addr += tx_size;
+
+ return (p_transfer->size != 0);
+}
+
+/**
+ * @brief Integrated feeder from a flash source with ZLP.
+ *
+ * @param[out] p_next See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in,out] p_context See @ref nrfx_usbd_feeder_t documentation.
+ * @param[in] ep_size See @ref nrfx_usbd_feeder_t documentation.
+ *
+ * @retval true Continue transfer.
+ * @retval false This was the last transfer.
+ */
+bool nrfx_usbd_feeder_flash_zlp(nrfx_usbd_ep_transfer_t * p_next, void * p_context, size_t ep_size)
+{
+ nrfx_usbd_transfer_t * p_transfer = p_context;
+ NRFX_ASSERT(!nrfx_is_in_ram(p_transfer->p_data.tx));
+
+ size_t tx_size = p_transfer->size;
+ void * p_buffer = nrfx_usbd_feeder_buffer_get();
+
+ if (tx_size > ep_size)
+ {
+ tx_size = ep_size;
+ }
+
+ NRFX_ASSERT(tx_size <= NRFX_USBD_FEEDER_BUFFER_SIZE);
+
+ if (tx_size != 0)
+ {
+ memcpy(p_buffer, (p_transfer->p_data.tx), tx_size);
+ p_next->p_data.tx = p_buffer;
+ }
+ else
+ {
+ p_next->p_data.tx = NULL;
+ }
+ p_next->size = tx_size;
+
+ p_transfer->size -= tx_size;
+ p_transfer->p_data.addr += tx_size;
+
+ return (tx_size != 0);
+}
+
+/** @} */
+
+/**
+ * @brief Change Driver endpoint number to HAL endpoint number.
+ *
+ * @param ep Driver endpoint identifier.
+ *
+ * @return Endpoint identifier in HAL.
+ *
+ * @sa nrfx_usbd_ep_from_hal
+ */
+static inline uint8_t ep_to_hal(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+ return (uint8_t)ep;
+}
+
+/**
+ * @brief Generate start task number for selected endpoint index.
+ *
+ * @param ep Endpoint number.
+ *
+ * @return Task for starting EasyDMA transfer on selected endpoint.
+ */
+static inline nrf_usbd_task_t task_start_ep(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+ return (nrf_usbd_task_t)(
+ (NRF_USBD_EPIN_CHECK(ep) ? NRF_USBD_TASK_STARTEPIN0 : NRF_USBD_TASK_STARTEPOUT0) +
+ (NRF_USBD_EP_NR_GET(ep) * sizeof(uint32_t)));
+}
+
+/**
+ * @brief Access selected endpoint state structure.
+ *
+ * Function used to change or just read the state of selected endpoint.
+ * It is used for internal transmission state.
+ *
+ * @param ep Endpoint number.
+ */
+static inline usbd_ep_state_t* ep_state_access(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+ return ((NRF_USBD_EPIN_CHECK(ep) ? m_ep_state.ep_in : m_ep_state.ep_out) +
+ NRF_USBD_EP_NR_GET(ep));
+}
+
+/**
+ * @brief Change endpoint number to bit position.
+ *
+ * Bit positions are defined the same way as they are placed in DATAEPSTATUS register,
+ * but bits for endpoint 0 are included.
+ *
+ * @param ep Endpoint number.
+ *
+ * @return Bit position related to the given endpoint number.
+ *
+ * @sa bit2ep
+ */
+static inline uint8_t ep2bit(nrfx_usbd_ep_t ep)
+{
+ NRFX_USBD_ASSERT_EP_VALID(ep);
+ return NRFX_USBD_EP_BITPOS(ep);
+}
+
+/**
+ * @brief Change bit position to endpoint number.
+ *
+ * @param bitpos Bit position.
+ *
+ * @return Endpoint number corresponding to given bit position.
+ *
+ * @sa ep2bit
+ */
+static inline nrfx_usbd_ep_t bit2ep(uint8_t bitpos)
+{
+ NRFX_STATIC_ASSERT(NRFX_USBD_EPOUT_BITPOS_0 > NRFX_USBD_EPIN_BITPOS_0);
+ return (nrfx_usbd_ep_t)((bitpos >= NRFX_USBD_EPOUT_BITPOS_0) ?
+ NRF_USBD_EPOUT(bitpos - NRFX_USBD_EPOUT_BITPOS_0) : NRF_USBD_EPIN(bitpos));
+}
+
+/**
+ * @brief Mark that EasyDMA is working.
+ *
+ * Internal function to set the flag informing about EasyDMA transfer pending.
+ * This function is called always just after the EasyDMA transfer is started.
+ */
+static inline void usbd_dma_pending_set(void)
+{
+ if (nrfx_usbd_errata_199())
+ {
+ *((volatile uint32_t *)0x40027C1C) = 0x00000082;
+ }
+ m_dma_pending = true;
+}
+
+/**
+ * @brief Mark that EasyDMA is free.
+ *
+ * Internal function to clear the flag informing about EasyDMA transfer pending.
+ * This function is called always just after the finished EasyDMA transfer is detected.
+ */
+static inline void usbd_dma_pending_clear(void)
+{
+ if (nrfx_usbd_errata_199())
+ {
+ *((volatile uint32_t *)0x40027C1C) = 0x00000000;
+ }
+ m_dma_pending = false;
+}
+
+/**
+ * @brief Start selected EasyDMA transmission.
+ *
+ * This is internal auxiliary function.
+ * No checking is made if EasyDMA is ready for new transmission.
+ *
+ * @param[in] ep Number of endpoint for transmission.
+ * If it is OUT endpoint transmission would be directed from endpoint to RAM.
+ * If it is in endpoint transmission would be directed from RAM to endpoint.
+ */
+static inline void usbd_dma_start(nrfx_usbd_ep_t ep)
+{
+ nrf_usbd_task_trigger(task_start_ep(ep));
+}
+
+void nrfx_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config)
+{
+ NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a());
+ nrf_usbd_isoinconfig_set(config);
+}
+
+nrf_usbd_isoinconfig_t nrfx_usbd_isoinconfig_get(void)
+{
+ NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a());
+ return nrf_usbd_isoinconfig_get();
+}
+
+/**
+ * @brief Abort pending transfer on selected endpoint.
+ *
+ * @param ep Endpoint number.
+ *
+ * @note
+ * This function locks interrupts that may be costly.
+ * It is good idea to test if the endpoint is still busy before calling this function:
+ * @code
+ (m_ep_dma_waiting & (1U << ep2bit(ep)))
+ * @endcode
+ * This function would check it again, but it makes it inside critical section.
+ */
+static inline void usbd_ep_abort(nrfx_usbd_ep_t ep)
+{
+ NRFX_CRITICAL_SECTION_ENTER();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+
+ if (NRF_USBD_EPOUT_CHECK(ep))
+ {
+ /* Host -> Device */
+ if ((~m_ep_dma_waiting) & (1U << ep2bit(ep)))
+ {
+ /* If the bit in m_ep_dma_waiting in cleared - nothing would be
+ * processed inside transfer processing */
+ nrfx_usbd_transfer_out_drop(ep);
+ }
+ else
+ {
+ p_state->handler.consumer = NULL;
+ m_ep_dma_waiting &= ~(1U << ep2bit(ep));
+ m_ep_ready &= ~(1U << ep2bit(ep));
+ }
+ /* Aborted */
+ p_state->status = NRFX_USBD_EP_ABORTED;
+ }
+ else
+ {
+ if(!NRF_USBD_EPISO_CHECK(ep))
+ {
+ /* Workaround: Disarm the endpoint if there is any data buffered. */
+ if(ep != NRFX_USBD_EPIN0)
+ {
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7B6 + (2u * (NRF_USBD_EP_NR_GET(ep) - 1));
+ uint8_t temp = *((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ temp |= (1U << 1);
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) |= temp;
+ (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ }
+ else
+ {
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7B4;
+ uint8_t temp = *((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ temp |= (1U << 2);
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) |= temp;
+ (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ }
+ }
+ if ((m_ep_dma_waiting | (~m_ep_ready)) & (1U << ep2bit(ep)))
+ {
+ /* Device -> Host */
+ m_ep_dma_waiting &= ~(1U << ep2bit(ep));
+ m_ep_ready |= 1U << ep2bit(ep) ;
+
+ p_state->handler.feeder = NULL;
+ p_state->status = NRFX_USBD_EP_ABORTED;
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_ABORTED);
+ m_event_handler(&evt);
+ }
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+}
+
+void nrfx_usbd_ep_abort(nrfx_usbd_ep_t ep)
+{
+ usbd_ep_abort(ep);
+}
+
+
+/**
+ * @brief Abort all pending endpoints.
+ *
+ * Function aborts all pending endpoint transfers.
+ */
+static void usbd_ep_abort_all(void)
+{
+ uint32_t ep_waiting = m_ep_dma_waiting | (m_ep_ready & NRFX_USBD_EPOUT_BIT_MASK);
+ while (0 != ep_waiting)
+ {
+ uint8_t bitpos = __CLZ(__RBIT(ep_waiting));
+ if (!NRF_USBD_EPISO_CHECK(bit2ep(bitpos)))
+ {
+ usbd_ep_abort(bit2ep(bitpos));
+ }
+ ep_waiting &= ~(1U << bitpos);
+ }
+
+ m_ep_ready = (((1U << NRF_USBD_EPIN_CNT) - 1U) << NRFX_USBD_EPIN_BITPOS_0);
+}
+
+/**
+ * @brief Force the USBD interrupt into pending state.
+ *
+ * This function is used to force USBD interrupt to be processed right now.
+ * It makes it possible to process all EasyDMA access on one thread priority level.
+ */
+static inline void usbd_int_rise(void)
+{
+ NRFX_IRQ_PENDING_SET(USBD_IRQn);
+}
+
+/**
+ * @name USBD interrupt runtimes.
+ *
+ * Interrupt runtimes that would be vectorized using @ref m_isr.
+ * @{
+ */
+
+static void ev_usbreset_handler(void)
+{
+ m_bus_suspend = false;
+ m_last_setup_dir = NRFX_USBD_EPOUT0;
+
+ const nrfx_usbd_evt_t evt = {
+ .type = NRFX_USBD_EVT_RESET
+ };
+
+ m_event_handler(&evt);
+}
+
+static void ev_started_handler(void)
+{
+#if NRFX_USBD_STARTED_EV_ENABLE
+ // Handler not used by the stack.
+ // May be used for debugging.
+#endif
+}
+
+/**
+ * @brief Handler for EasyDMA event without endpoint clearing.
+ *
+ * This handler would be called when EasyDMA transfer for endpoints that does not require clearing.
+ * All in endpoints are cleared automatically when new EasyDMA transfer is initialized.
+ * For endpoint 0 see @ref nrf_usbd_ep0out_dma_handler.
+ *
+ * @param[in] ep Endpoint number.
+ */
+static inline void nrf_usbd_ep0in_dma_handler(void)
+{
+ const nrfx_usbd_ep_t ep = NRFX_USBD_EPIN0;
+ NRFX_LOG_DEBUG("USB event: DMA ready IN0");
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Clear transfer information just in case */
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else if (p_state->handler.feeder == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Handler for EasyDMA event without endpoint clearing.
+ *
+ * This handler would be called when EasyDMA transfer for endpoints that does not require clearing.
+ * All in endpoints are cleared automatically when new EasyDMA transfer is initialized.
+ * For endpoint 0 see @ref nrf_usbd_ep0out_dma_handler.
+ *
+ * @param[in] ep Endpoint number.
+ */
+static inline void nrf_usbd_epin_dma_handler(nrfx_usbd_ep_t ep)
+{
+ NRFX_LOG_DEBUG("USB event: DMA ready IN: %x", ep);
+ NRFX_ASSERT(NRF_USBD_EPIN_CHECK(ep));
+ NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep));
+ NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) > 0);
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Clear transfer information just in case */
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else if (p_state->handler.feeder == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Handler for EasyDMA event from in isochronous endpoint.
+ */
+static inline void nrf_usbd_epiniso_dma_handler(nrfx_usbd_ep_t ep)
+{
+ if (NRFX_USBD_ISO_DEBUG)
+ {
+ NRFX_LOG_DEBUG("USB event: DMA ready ISOIN: %x", ep);
+ }
+ NRFX_ASSERT(NRF_USBD_EPIN_CHECK(ep));
+ NRFX_ASSERT(NRF_USBD_EPISO_CHECK(ep));
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Clear transfer information just in case */
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else if (p_state->handler.feeder == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ /* Send event to the user - for an ISO IN endpoint, the whole transfer is finished in this moment */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OK);
+ m_event_handler(&evt);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+/**
+ * @brief Handler for EasyDMA event for OUT endpoint 0.
+ *
+ * EP0 OUT have to be cleared automatically in special way - only in the middle of the transfer.
+ * It cannot be cleared when required transfer is finished because it means the same that accepting the comment.
+ */
+static inline void nrf_usbd_ep0out_dma_handler(void)
+{
+ const nrfx_usbd_ep_t ep = NRFX_USBD_EPOUT0;
+ NRFX_LOG_DEBUG("USB event: DMA ready OUT0");
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Clear transfer information just in case */
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else if (p_state->handler.consumer == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ /* Send event to the user - for an OUT endpoint, the whole transfer is finished in this moment */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OK);
+ m_event_handler(&evt);
+ }
+ else
+ {
+ nrfx_usbd_setup_data_clear();
+ }
+}
+
+/**
+ * @brief Handler for EasyDMA event from endpoinpoint that requires clearing.
+ *
+ * This handler would be called when EasyDMA transfer for OUT endpoint has been finished.
+ *
+ * @param[in] ep Endpoint number.
+ */
+static inline void nrf_usbd_epout_dma_handler(nrfx_usbd_ep_t ep)
+{
+ NRFX_LOG_DEBUG("DMA ready OUT: %x", ep);
+ NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep));
+ NRFX_ASSERT(!NRF_USBD_EPISO_CHECK(ep));
+ NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) > 0);
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Clear transfer information just in case */
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ }
+ else if (p_state->handler.consumer == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ /* Send event to the user - for an OUT endpoint, the whole transfer is finished in this moment */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OK);
+ m_event_handler(&evt);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+#if NRFX_USBD_EARLY_DMA_PROCESS
+ /* Speed up */
+ usbd_dmareq_process();
+#endif
+}
+
+/**
+ * @brief Handler for EasyDMA event from out isochronous endpoint.
+ */
+static inline void nrf_usbd_epoutiso_dma_handler(nrfx_usbd_ep_t ep)
+{
+ if (NRFX_USBD_ISO_DEBUG)
+ {
+ NRFX_LOG_DEBUG("DMA ready ISOOUT: %x", ep);
+ }
+ NRFX_ASSERT(NRF_USBD_EPISO_CHECK(ep));
+ usbd_dma_pending_clear();
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ if (NRFX_USBD_EP_ABORTED == p_state->status)
+ {
+ /* Nothing to do - just ignore */
+ }
+ else if (p_state->handler.consumer == NULL)
+ {
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << ep2bit(ep))));
+ /* Send event to the user - for an OUT endpoint, the whole transfer is finished in this moment */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OK);
+ m_event_handler(&evt);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+}
+
+
+static void ev_dma_epin0_handler(void) { nrf_usbd_ep0in_dma_handler(); }
+static void ev_dma_epin1_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN1 ); }
+static void ev_dma_epin2_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN2 ); }
+static void ev_dma_epin3_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN3 ); }
+static void ev_dma_epin4_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN4 ); }
+static void ev_dma_epin5_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN5 ); }
+static void ev_dma_epin6_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN6 ); }
+static void ev_dma_epin7_handler(void) { nrf_usbd_epin_dma_handler(NRFX_USBD_EPIN7 ); }
+static void ev_dma_epin8_handler(void) { nrf_usbd_epiniso_dma_handler(NRFX_USBD_EPIN8 ); }
+
+static void ev_dma_epout0_handler(void) { nrf_usbd_ep0out_dma_handler(); }
+static void ev_dma_epout1_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT1); }
+static void ev_dma_epout2_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT2); }
+static void ev_dma_epout3_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT3); }
+static void ev_dma_epout4_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT4); }
+static void ev_dma_epout5_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT5); }
+static void ev_dma_epout6_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT6); }
+static void ev_dma_epout7_handler(void) { nrf_usbd_epout_dma_handler(NRFX_USBD_EPOUT7); }
+static void ev_dma_epout8_handler(void) { nrf_usbd_epoutiso_dma_handler(NRFX_USBD_EPOUT8); }
+
+static void ev_sof_handler(void)
+{
+ nrfx_usbd_evt_t evt = {
+ NRFX_USBD_EVT_SOF,
+ .data = { .sof = { .framecnt = nrf_usbd_framecntr_get() }}
+ };
+
+ /* Process isochronous endpoints */
+ uint32_t iso_ready_mask = (1U << ep2bit(NRFX_USBD_EPIN8));
+ if (nrf_usbd_episoout_size_get(NRFX_USBD_EPOUT8) != NRF_USBD_EPISOOUT_NO_DATA)
+ {
+ iso_ready_mask |= (1U << ep2bit(NRFX_USBD_EPOUT8));
+ }
+ m_ep_ready |= iso_ready_mask;
+
+ m_event_handler(&evt);
+}
+
+/**
+ * @brief React on data transfer finished.
+ *
+ * Auxiliary internal function.
+ * @param ep Endpoint number.
+ * @param bitpos Bit position for selected endpoint number.
+ */
+static void usbd_ep_data_handler(nrfx_usbd_ep_t ep, uint8_t bitpos)
+{
+ NRFX_LOG_DEBUG("USBD event: EndpointData: %x", ep);
+ /* Mark endpoint ready for next DMA access */
+ m_ep_ready |= (1U << bitpos);
+
+ if (NRF_USBD_EPIN_CHECK(ep))
+ {
+ /* IN endpoint (Device -> Host) */
+ if (0 == (m_ep_dma_waiting & (1U << bitpos)))
+ {
+ NRFX_LOG_DEBUG("USBD event: EndpointData: In finished");
+ /* No more data to be send - transmission finished */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OK);
+ m_event_handler(&evt);
+ }
+ }
+ else
+ {
+ /* OUT endpoint (Host -> Device) */
+ if (0 == (m_ep_dma_waiting & (1U << bitpos)))
+ {
+ NRFX_LOG_DEBUG("USBD event: EndpointData: Out waiting");
+ /* No buffer prepared - send event to the application */
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_WAITING);
+ m_event_handler(&evt);
+ }
+ }
+}
+
+static void ev_setup_data_handler(void)
+{
+ usbd_ep_data_handler(m_last_setup_dir, ep2bit(m_last_setup_dir));
+}
+
+static void ev_setup_handler(void)
+{
+ NRFX_LOG_DEBUG("USBD event: Setup (rt:%.2x r:%.2x v:%.4x i:%.4x l:%u )",
+ nrf_usbd_setup_bmrequesttype_get(),
+ nrf_usbd_setup_brequest_get(),
+ nrf_usbd_setup_wvalue_get(),
+ nrf_usbd_setup_windex_get(),
+ nrf_usbd_setup_wlength_get());
+ uint8_t bmRequestType = nrf_usbd_setup_bmrequesttype_get();
+
+ if ((m_ep_dma_waiting | ((~m_ep_ready) & NRFX_USBD_EPIN_BIT_MASK))
+ & (1U <<ep2bit(m_last_setup_dir)))
+ {
+ NRFX_LOG_DEBUG("USBD drv: Trying to abort last transfer on EP0");
+ usbd_ep_abort(m_last_setup_dir);
+ }
+
+ m_last_setup_dir =
+ ((bmRequestType & USBD_BMREQUESTTYPE_DIRECTION_Msk) ==
+ (USBD_BMREQUESTTYPE_DIRECTION_HostToDevice << USBD_BMREQUESTTYPE_DIRECTION_Pos)) ?
+ NRFX_USBD_EPOUT0 : NRFX_USBD_EPIN0;
+
+ (void)(NRFX_ATOMIC_FETCH_AND(
+ &m_ep_dma_waiting,
+ ~((1U << ep2bit(NRFX_USBD_EPOUT0)) | (1U << ep2bit(NRFX_USBD_EPIN0)))));
+ m_ep_ready |= 1U << ep2bit(NRFX_USBD_EPIN0);
+
+
+ const nrfx_usbd_evt_t evt = {
+ .type = NRFX_USBD_EVT_SETUP
+ };
+ m_event_handler(&evt);
+}
+
+static void ev_usbevent_handler(void)
+{
+ uint32_t event = nrf_usbd_eventcause_get_and_clear();
+
+ if (event & NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK)
+ {
+ NRFX_LOG_DEBUG("USBD event: ISOOUTCRC");
+ /* Currently no support */
+ }
+ if (event & NRF_USBD_EVENTCAUSE_SUSPEND_MASK)
+ {
+ NRFX_LOG_DEBUG("USBD event: SUSPEND");
+ m_bus_suspend = true;
+ const nrfx_usbd_evt_t evt = {
+ .type = NRFX_USBD_EVT_SUSPEND
+ };
+ m_event_handler(&evt);
+ }
+ if (event & NRF_USBD_EVENTCAUSE_RESUME_MASK)
+ {
+ NRFX_LOG_DEBUG("USBD event: RESUME");
+ m_bus_suspend = false;
+ const nrfx_usbd_evt_t evt = {
+ .type = NRFX_USBD_EVT_RESUME
+ };
+ m_event_handler(&evt);
+ }
+ if (event & NRF_USBD_EVENTCAUSE_WUREQ_MASK)
+ {
+ NRFX_LOG_DEBUG("USBD event: WUREQ (%s)", m_bus_suspend ? "In Suspend" : "Active");
+ if (m_bus_suspend)
+ {
+ NRFX_ASSERT(!nrf_usbd_lowpower_check());
+ m_bus_suspend = false;
+
+ nrf_usbd_dpdmvalue_set(NRF_USBD_DPDMVALUE_RESUME);
+ nrf_usbd_task_trigger(NRF_USBD_TASK_DRIVEDPDM);
+
+ const nrfx_usbd_evt_t evt = {
+ .type = NRFX_USBD_EVT_WUREQ
+ };
+ m_event_handler(&evt);
+ }
+ }
+}
+
+static void ev_epdata_handler(void)
+{
+ /* Get all endpoints that have acknowledged transfer */
+ uint32_t dataepstatus = nrf_usbd_epdatastatus_get_and_clear();
+ if (nrfx_usbd_errata_104())
+ {
+ dataepstatus |= (m_simulated_dataepstatus &
+ ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0)));
+ m_simulated_dataepstatus &=
+ ((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0));
+ }
+ NRFX_LOG_DEBUG("USBD event: EndpointEPStatus: %x", dataepstatus);
+
+ /* All finished endpoint have to be marked as busy */
+ while (dataepstatus)
+ {
+ uint8_t bitpos = __CLZ(__RBIT(dataepstatus));
+ nrfx_usbd_ep_t ep = bit2ep(bitpos);
+ dataepstatus &= ~(1UL << bitpos);
+
+ (void)(usbd_ep_data_handler(ep, bitpos));
+ }
+ if (NRFX_USBD_EARLY_DMA_PROCESS)
+ {
+ /* Speed up */
+ usbd_dmareq_process();
+ }
+}
+
+/**
+ * @brief Function to select the endpoint to start.
+ *
+ * Function that realizes algorithm to schedule right channel for EasyDMA transfer.
+ * It gets a variable with flags for the endpoints currently requiring transfer.
+ *
+ * @param[in] req Bit flags for channels currently requiring transfer.
+ * Bits 0...8 used for IN endpoints.
+ * Bits 16...24 used for OUT endpoints.
+ * @note
+ * This function would be never called with 0 as a @c req argument.
+ * @return The bit number of the endpoint that should be processed now.
+ */
+static uint8_t usbd_dma_scheduler_algorithm(uint32_t req)
+{
+ /* Only prioritized scheduling mode is supported. */
+ return __CLZ(__RBIT(req));
+}
+
+/**
+ * @brief Get the size of isochronous endpoint.
+ *
+ * The size of isochronous endpoint is configurable.
+ * This function returns the size of isochronous buffer taking into account
+ * current configuration.
+ *
+ * @param[in] ep Endpoint number.
+ *
+ * @return The size of endpoint buffer.
+ */
+static inline size_t usbd_ep_iso_capacity(nrfx_usbd_ep_t ep)
+{
+ (void)ep;
+ nrf_usbd_isosplit_t split = nrf_usbd_isosplit_get();
+ if (NRF_USBD_ISOSPLIT_HALF == split)
+ {
+ return NRFX_USBD_ISOSIZE / 2;
+ }
+ return NRFX_USBD_ISOSIZE;
+}
+
+/**
+ * @brief Process all DMA requests.
+ *
+ * Function that have to be called from USBD interrupt handler.
+ * It have to be called when all the interrupts connected with endpoints transfer
+ * and DMA transfer are already handled.
+ */
+static void usbd_dmareq_process(void)
+{
+ if (!m_dma_pending)
+ {
+ uint32_t req;
+ while (0 != (req = m_ep_dma_waiting & m_ep_ready))
+ {
+ uint8_t pos;
+ if (NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST && ((req & USBD_EPISO_BIT_MASK) != 0))
+ {
+ pos = usbd_dma_scheduler_algorithm(req & USBD_EPISO_BIT_MASK);
+ }
+ else
+ {
+ pos = usbd_dma_scheduler_algorithm(req);
+ }
+ nrfx_usbd_ep_t ep = bit2ep(pos);
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+
+ nrfx_usbd_ep_transfer_t transfer;
+ bool continue_transfer;
+
+ NRFX_STATIC_ASSERT(offsetof(usbd_ep_state_t, handler.feeder) ==
+ offsetof(usbd_ep_state_t, handler.consumer));
+ NRFX_ASSERT((p_state->handler.feeder) != NULL);
+
+ if (NRF_USBD_EPIN_CHECK(ep))
+ {
+ /* Device -> Host */
+ continue_transfer = p_state->handler.feeder(
+ &transfer,
+ p_state->p_context,
+ p_state->max_packet_size);
+
+ if (!continue_transfer)
+ {
+ p_state->handler.feeder = NULL;
+ }
+ }
+ else
+ {
+ /* Host -> Device */
+ const size_t rx_size = nrfx_usbd_epout_size_get(ep);
+ continue_transfer = p_state->handler.consumer(
+ &transfer,
+ p_state->p_context,
+ p_state->max_packet_size,
+ rx_size);
+
+ if (transfer.p_data.rx == NULL)
+ {
+ /* Dropping transfer - allow processing */
+ NRFX_ASSERT(transfer.size == 0);
+ }
+ else if (transfer.size < rx_size)
+ {
+ NRFX_LOG_DEBUG("Endpoint %x overload (r: %u, e: %u)", ep, rx_size, transfer.size);
+ p_state->status = NRFX_USBD_EP_OVERLOAD;
+ (void)(NRFX_ATOMIC_FETCH_AND(&m_ep_dma_waiting, ~(1U << pos)));
+ NRFX_USBD_EP_TRANSFER_EVENT(evt, ep, NRFX_USBD_EP_OVERLOAD);
+ m_event_handler(&evt);
+ /* This endpoint will not be transmitted now, repeat the loop */
+ continue;
+ }
+ else
+ {
+ /* Nothing to do - only check integrity if assertions are enabled */
+ NRFX_ASSERT(transfer.size == rx_size);
+ }
+
+ if (!continue_transfer)
+ {
+ p_state->handler.consumer = NULL;
+ }
+ }
+
+ usbd_dma_pending_set();
+ m_ep_ready &= ~(1U << pos);
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG(
+ "USB DMA process: Starting transfer on EP: %x, size: %u",
+ ep,
+ transfer.size);
+ }
+ /* Update number of currently transferred bytes */
+ p_state->transfer_cnt += transfer.size;
+ /* Start transfer to the endpoint buffer */
+ nrf_usbd_ep_easydma_set(ep, transfer.p_data.addr, (uint32_t)transfer.size);
+
+ if (nrfx_usbd_errata_104())
+ {
+ uint32_t cnt_end = (uint32_t)(-1);
+ do
+ {
+ uint32_t cnt = (uint32_t)(-1);
+ do
+ {
+ nrf_usbd_event_clear(NRF_USBD_EVENT_STARTED);
+ usbd_dma_start(ep);
+ nrfx_systick_delay_us(2);
+ ++cnt;
+ }while (!nrf_usbd_event_check(NRF_USBD_EVENT_STARTED));
+ if (cnt)
+ {
+ NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" DMA restarted: %u times", cnt);
+ }
+
+ nrfx_systick_delay_us(30);
+ while (0 == (0x20 & *((volatile uint32_t *)(NRF_USBD_BASE + 0x474))))
+ {
+ nrfx_systick_delay_us(2);
+ }
+ nrfx_systick_delay_us(1);
+
+ ++cnt_end;
+ } while (!nrf_usbd_event_check(nrfx_usbd_ep_to_endevent(ep)));
+ if (cnt_end)
+ {
+ NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" DMA fully restarted: %u times", cnt_end);
+ }
+ }
+ else
+ {
+ usbd_dma_start(ep);
+ /* There is a lot of USBD registers that cannot be accessed during EasyDMA transfer.
+ * This is quick fix to maintain stability of the stack.
+ * It cost some performance but makes stack stable. */
+ while (!nrf_usbd_event_check(nrfx_usbd_ep_to_endevent(ep)))
+ {
+ /* Empty */
+ }
+ }
+
+ if (NRFX_USBD_DMAREQ_PROCESS_DEBUG)
+ {
+ NRFX_LOG_DEBUG("USB DMA process - finishing");
+ }
+ /* Transfer started - exit the loop */
+ break;
+ }
+ }
+ else
+ {
+ if (NRFX_USBD_DMAREQ_PROCESS_DEBUG)
+ {
+ NRFX_LOG_DEBUG("USB DMA process - EasyDMA busy");
+ }
+ }
+}
+/** @} */
+
+/**
+ * @brief USBD interrupt service routines.
+ *
+ */
+static const nrfx_irq_handler_t m_isr[] =
+{
+ [USBD_INTEN_USBRESET_Pos ] = ev_usbreset_handler,
+ [USBD_INTEN_STARTED_Pos ] = ev_started_handler,
+ [USBD_INTEN_ENDEPIN0_Pos ] = ev_dma_epin0_handler,
+ [USBD_INTEN_ENDEPIN1_Pos ] = ev_dma_epin1_handler,
+ [USBD_INTEN_ENDEPIN2_Pos ] = ev_dma_epin2_handler,
+ [USBD_INTEN_ENDEPIN3_Pos ] = ev_dma_epin3_handler,
+ [USBD_INTEN_ENDEPIN4_Pos ] = ev_dma_epin4_handler,
+ [USBD_INTEN_ENDEPIN5_Pos ] = ev_dma_epin5_handler,
+ [USBD_INTEN_ENDEPIN6_Pos ] = ev_dma_epin6_handler,
+ [USBD_INTEN_ENDEPIN7_Pos ] = ev_dma_epin7_handler,
+ [USBD_INTEN_EP0DATADONE_Pos] = ev_setup_data_handler,
+ [USBD_INTEN_ENDISOIN_Pos ] = ev_dma_epin8_handler,
+ [USBD_INTEN_ENDEPOUT0_Pos ] = ev_dma_epout0_handler,
+ [USBD_INTEN_ENDEPOUT1_Pos ] = ev_dma_epout1_handler,
+ [USBD_INTEN_ENDEPOUT2_Pos ] = ev_dma_epout2_handler,
+ [USBD_INTEN_ENDEPOUT3_Pos ] = ev_dma_epout3_handler,
+ [USBD_INTEN_ENDEPOUT4_Pos ] = ev_dma_epout4_handler,
+ [USBD_INTEN_ENDEPOUT5_Pos ] = ev_dma_epout5_handler,
+ [USBD_INTEN_ENDEPOUT6_Pos ] = ev_dma_epout6_handler,
+ [USBD_INTEN_ENDEPOUT7_Pos ] = ev_dma_epout7_handler,
+ [USBD_INTEN_ENDISOOUT_Pos ] = ev_dma_epout8_handler,
+ [USBD_INTEN_SOF_Pos ] = ev_sof_handler,
+ [USBD_INTEN_USBEVENT_Pos ] = ev_usbevent_handler,
+ [USBD_INTEN_EP0SETUP_Pos ] = ev_setup_handler,
+ [USBD_INTEN_EPDATA_Pos ] = ev_epdata_handler
+};
+
+/**
+ * @name Interrupt handlers
+ *
+ * @{
+ */
+void nrfx_usbd_irq_handler(void)
+{
+ const uint32_t enabled = nrf_usbd_int_enable_get();
+ uint32_t to_process = enabled;
+ uint32_t active = 0;
+
+ /* Check all enabled interrupts */
+ while (to_process)
+ {
+ uint8_t event_nr = __CLZ(__RBIT(to_process));
+ if (nrf_usbd_event_get_and_clear((nrf_usbd_event_t)nrfx_bitpos_to_event(event_nr)))
+ {
+ active |= 1UL << event_nr;
+ }
+ to_process &= ~(1UL << event_nr);
+ }
+
+ if (nrfx_usbd_errata_104())
+ {
+ /* Event correcting */
+ if ((!m_dma_pending) && (0 != (active & (USBD_INTEN_SOF_Msk))))
+ {
+ uint8_t usbi, uoi, uii;
+ /* Testing */
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
+ uii = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ if (0 != uii)
+ {
+ uii &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ }
+
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
+ uoi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ if (0 != uoi)
+ {
+ uoi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ }
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
+ usbi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ if (0 != usbi)
+ {
+ usbi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ }
+ /* Processing */
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AC;
+ uii &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ if (0 != uii)
+ {
+ uint8_t rb;
+ m_simulated_dataepstatus |= ((uint32_t)uii) << NRFX_USBD_EPIN_BITPOS_0;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uii;
+ rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uii: 0x%.2x (0x%.2x)", uii, rb);
+ (void)rb;
+ }
+
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AD;
+ uoi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ if (0 != uoi)
+ {
+ uint8_t rb;
+ m_simulated_dataepstatus |= ((uint32_t)uoi) << NRFX_USBD_EPOUT_BITPOS_0;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uoi;
+ rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uoi: 0x%.2u (0x%.2x)", uoi, rb);
+ (void)rb;
+ }
+
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AE;
+ usbi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ if (0 != usbi)
+ {
+ uint8_t rb;
+ if (usbi & 0x01)
+ {
+ active |= USBD_INTEN_EP0SETUP_Msk;
+ }
+ if (usbi & 0x10)
+ {
+ active |= USBD_INTEN_USBRESET_Msk;
+ }
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = usbi;
+ rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
+ NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" usbi: 0x%.2u (0x%.2x)", usbi, rb);
+ (void)rb;
+ }
+
+ if (0 != (m_simulated_dataepstatus &
+ ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0))))
+ {
+ active |= enabled & NRF_USBD_INT_DATAEP_MASK;
+ }
+ if (0 != (m_simulated_dataepstatus &
+ ((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0))))
+ {
+ if (0 != (enabled & NRF_USBD_INT_EP0DATADONE_MASK))
+ {
+ m_simulated_dataepstatus &=
+ ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0));
+ active |= NRF_USBD_INT_EP0DATADONE_MASK;
+ }
+ }
+ }
+ }
+
+ /* Process the active interrupts */
+ bool setup_active = 0 != (active & NRF_USBD_INT_EP0SETUP_MASK);
+ active &= ~NRF_USBD_INT_EP0SETUP_MASK;
+
+ while (active)
+ {
+ uint8_t event_nr = __CLZ(__RBIT(active));
+ m_isr[event_nr]();
+ active &= ~(1UL << event_nr);
+ }
+ usbd_dmareq_process();
+
+ if (setup_active)
+ {
+ m_isr[USBD_INTEN_EP0SETUP_Pos]();
+ }
+}
+
+/** @} */
+/** @} */
+
+nrfx_err_t nrfx_usbd_init(nrfx_usbd_event_handler_t event_handler)
+{
+ NRFX_ASSERT((nrfx_usbd_errata_type_52840_eng_a() ||
+ nrfx_usbd_errata_type_52840_eng_b() ||
+ nrfx_usbd_errata_type_52840_eng_c() ||
+ nrfx_usbd_errata_type_52840_eng_d())
+ );
+
+ NRFX_ASSERT(event_handler);
+
+ if (m_drv_state != NRFX_DRV_STATE_UNINITIALIZED)
+ {
+ return NRFX_ERROR_INVALID_STATE;
+ }
+
+ m_event_handler = event_handler;
+ m_drv_state = NRFX_DRV_STATE_INITIALIZED;
+
+ uint8_t n;
+ for (n = 0; n < NRF_USBD_EPIN_CNT; ++n)
+ {
+ nrfx_usbd_ep_t ep = NRFX_USBD_EPIN(n);
+ nrfx_usbd_ep_max_packet_size_set(ep, NRF_USBD_EPISO_CHECK(ep) ?
+ (NRFX_USBD_ISOSIZE / 2) : NRFX_USBD_EPSIZE);
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ p_state->status = NRFX_USBD_EP_OK;
+ p_state->handler.feeder = NULL;
+ p_state->transfer_cnt = 0;
+ }
+ for (n = 0; n < NRF_USBD_EPOUT_CNT; ++n)
+ {
+ nrfx_usbd_ep_t ep = NRFX_USBD_EPOUT(n);
+ nrfx_usbd_ep_max_packet_size_set(ep, NRF_USBD_EPISO_CHECK(ep) ?
+ (NRFX_USBD_ISOSIZE / 2) : NRFX_USBD_EPSIZE);
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ p_state->status = NRFX_USBD_EP_OK;
+ p_state->handler.consumer = NULL;
+ p_state->transfer_cnt = 0;
+ }
+
+ return NRFX_SUCCESS;
+}
+
+void nrfx_usbd_uninit(void)
+{
+ NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_INITIALIZED);
+
+ m_event_handler = NULL;
+ m_drv_state = NRFX_DRV_STATE_UNINITIALIZED;
+ return;
+}
+
+void nrfx_usbd_enable(void)
+{
+ NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_INITIALIZED);
+
+ /* Prepare for READY event receiving */
+ nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
+
+ if (nrfx_usbd_errata_187())
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+
+ if (nrfx_usbd_errata_171())
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+
+ /* Enable the peripheral */
+ nrf_usbd_enable();
+ /* Waiting for peripheral to enable, this should take a few us */
+ while (0 == (NRF_USBD_EVENTCAUSE_READY_MASK & nrf_usbd_eventcause_get()))
+ {
+ /* Empty loop */
+ }
+ nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
+
+ if (nrfx_usbd_errata_171())
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ }
+
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+
+ if (nrfx_usbd_errata_166())
+ {
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7E3;
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = 0x40;
+ __ISB();
+ __DSB();
+ }
+
+ nrf_usbd_isosplit_set(NRF_USBD_ISOSPLIT_HALF);
+
+ if (NRFX_USBD_CONFIG_ISO_IN_ZLP)
+ {
+ nrfx_usbd_isoinconfig_set(NRF_USBD_ISOINCONFIG_ZERODATA);
+ }
+ else
+ {
+ nrfx_usbd_isoinconfig_set(NRF_USBD_ISOINCONFIG_NORESP);
+ }
+
+ m_ep_ready = (((1U << NRF_USBD_EPIN_CNT) - 1U) << NRFX_USBD_EPIN_BITPOS_0);
+ m_ep_dma_waiting = 0;
+ usbd_dma_pending_clear();
+ m_last_setup_dir = NRFX_USBD_EPOUT0;
+
+ m_drv_state = NRFX_DRV_STATE_POWERED_ON;
+
+ if (nrfx_usbd_errata_187())
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+}
+
+void nrfx_usbd_disable(void)
+{
+ NRFX_ASSERT(m_drv_state != NRFX_DRV_STATE_UNINITIALIZED);
+
+ /* Stop just in case */
+ nrfx_usbd_stop();
+
+ /* Disable all parts */
+ nrf_usbd_int_disable(nrf_usbd_int_enable_get());
+ nrf_usbd_disable();
+ usbd_dma_pending_clear();
+ m_drv_state = NRFX_DRV_STATE_INITIALIZED;
+}
+
+void nrfx_usbd_start(bool enable_sof)
+{
+ NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_POWERED_ON);
+ m_bus_suspend = false;
+
+ uint32_t ints_to_enable =
+ NRF_USBD_INT_USBRESET_MASK |
+ NRF_USBD_INT_STARTED_MASK |
+ NRF_USBD_INT_ENDEPIN0_MASK |
+ NRF_USBD_INT_EP0DATADONE_MASK |
+ NRF_USBD_INT_ENDEPOUT0_MASK |
+ NRF_USBD_INT_USBEVENT_MASK |
+ NRF_USBD_INT_EP0SETUP_MASK |
+ NRF_USBD_INT_DATAEP_MASK;
+
+ if (enable_sof || nrfx_usbd_errata_104())
+ {
+ ints_to_enable |= NRF_USBD_INT_SOF_MASK;
+ }
+
+ /* Enable all required interrupts */
+ nrf_usbd_int_enable(ints_to_enable);
+
+ /* Enable interrupt globally */
+ NRFX_IRQ_PRIORITY_SET(USBD_IRQn, NRFX_USBD_CONFIG_IRQ_PRIORITY);
+ NRFX_IRQ_ENABLE(USBD_IRQn);
+
+ /* Enable pullups */
+ nrf_usbd_pullup_enable();
+}
+
+void nrfx_usbd_stop(void)
+{
+ NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_POWERED_ON);
+
+ if (NRFX_IRQ_IS_ENABLED(USBD_IRQn))
+ {
+ /* Abort transfers */
+ usbd_ep_abort_all();
+
+ /* Disable pullups */
+ nrf_usbd_pullup_disable();
+
+ /* Disable interrupt globally */
+ NRFX_IRQ_DISABLE(USBD_IRQn);
+
+ /* Disable all interrupts */
+ nrf_usbd_int_disable(~0U);
+ }
+}
+
+bool nrfx_usbd_is_initialized(void)
+{
+ return (m_drv_state >= NRFX_DRV_STATE_INITIALIZED);
+}
+
+bool nrfx_usbd_is_enabled(void)
+{
+ return (m_drv_state >= NRFX_DRV_STATE_POWERED_ON);
+}
+
+bool nrfx_usbd_is_started(void)
+{
+ return (nrfx_usbd_is_enabled() && NRFX_IRQ_IS_ENABLED(USBD_IRQn));
+}
+
+bool nrfx_usbd_suspend(void)
+{
+ bool suspended = false;
+
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (m_bus_suspend)
+ {
+ usbd_ep_abort_all();
+
+ if (!(nrf_usbd_eventcause_get() & NRF_USBD_EVENTCAUSE_RESUME_MASK))
+ {
+ nrf_usbd_lowpower_enable();
+ if (nrf_usbd_eventcause_get() & NRF_USBD_EVENTCAUSE_RESUME_MASK)
+ {
+ nrf_usbd_lowpower_disable();
+ }
+ else
+ {
+ suspended = true;
+
+ if (nrfx_usbd_errata_171())
+ {
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ }
+ }
+ }
+ }
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+
+ return suspended;
+}
+
+bool nrfx_usbd_wakeup_req(void)
+{
+ bool started = false;
+
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (m_bus_suspend && nrf_usbd_lowpower_check())
+ {
+ nrf_usbd_lowpower_disable();
+ started = true;
+
+ if (nrfx_usbd_errata_171())
+ {
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ }
+
+ }
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+
+ return started;
+}
+
+bool nrfx_usbd_suspend_check(void)
+{
+ return nrf_usbd_lowpower_check();
+}
+
+void nrfx_usbd_suspend_irq_config(void)
+{
+ nrf_usbd_int_disable(m_irq_disabled_in_suspend);
+}
+
+void nrfx_usbd_active_irq_config(void)
+{
+ nrf_usbd_int_enable(m_irq_disabled_in_suspend);
+}
+
+bool nrfx_usbd_bus_suspend_check(void)
+{
+ return m_bus_suspend;
+}
+
+void nrfx_usbd_force_bus_wakeup(void)
+{
+ m_bus_suspend = false;
+}
+
+void nrfx_usbd_ep_max_packet_size_set(nrfx_usbd_ep_t ep, uint16_t size)
+{
+ /* Only power of 2 size allowed */
+ NRFX_ASSERT((size != 0) && (size & (size - 1)) == 0);
+ /* Packet size cannot be higher than maximum buffer size */
+ NRFX_ASSERT((NRF_USBD_EPISO_CHECK(ep) && (size <= usbd_ep_iso_capacity(ep))) ||
+ (!NRF_USBD_EPISO_CHECK(ep) && (size <= NRFX_USBD_EPSIZE)));
+
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ p_state->max_packet_size = size;
+}
+
+uint16_t nrfx_usbd_ep_max_packet_size_get(nrfx_usbd_ep_t ep)
+{
+ usbd_ep_state_t const * p_state = ep_state_access(ep);
+ return p_state->max_packet_size;
+}
+
+bool nrfx_usbd_ep_enable_check(nrfx_usbd_ep_t ep)
+{
+ return nrf_usbd_ep_enable_check(ep_to_hal(ep));
+}
+
+void nrfx_usbd_ep_enable(nrfx_usbd_ep_t ep)
+{
+ nrf_usbd_int_enable(nrfx_usbd_ep_to_int(ep));
+
+ if (nrf_usbd_ep_enable_check(ep))
+ {
+ return;
+ }
+ nrf_usbd_ep_enable(ep_to_hal(ep));
+ if ((NRF_USBD_EP_NR_GET(ep) != 0) &&
+ NRF_USBD_EPOUT_CHECK(ep) &&
+ !NRF_USBD_EPISO_CHECK(ep))
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ nrfx_usbd_transfer_out_drop(ep);
+ m_ep_dma_waiting &= ~(1U << ep2bit(ep));
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+}
+
+void nrfx_usbd_ep_disable(nrfx_usbd_ep_t ep)
+{
+ usbd_ep_abort(ep);
+ nrf_usbd_ep_disable(ep_to_hal(ep));
+ nrf_usbd_int_disable(nrfx_usbd_ep_to_int(ep));
+}
+
+void nrfx_usbd_ep_default_config(void)
+{
+ nrf_usbd_int_disable(
+ NRF_USBD_INT_ENDEPIN1_MASK |
+ NRF_USBD_INT_ENDEPIN2_MASK |
+ NRF_USBD_INT_ENDEPIN3_MASK |
+ NRF_USBD_INT_ENDEPIN4_MASK |
+ NRF_USBD_INT_ENDEPIN5_MASK |
+ NRF_USBD_INT_ENDEPIN6_MASK |
+ NRF_USBD_INT_ENDEPIN7_MASK |
+ NRF_USBD_INT_ENDISOIN0_MASK |
+ NRF_USBD_INT_ENDEPOUT1_MASK |
+ NRF_USBD_INT_ENDEPOUT2_MASK |
+ NRF_USBD_INT_ENDEPOUT3_MASK |
+ NRF_USBD_INT_ENDEPOUT4_MASK |
+ NRF_USBD_INT_ENDEPOUT5_MASK |
+ NRF_USBD_INT_ENDEPOUT6_MASK |
+ NRF_USBD_INT_ENDEPOUT7_MASK |
+ NRF_USBD_INT_ENDISOOUT0_MASK
+ );
+ nrf_usbd_int_enable(NRF_USBD_INT_ENDEPIN0_MASK | NRF_USBD_INT_ENDEPOUT0_MASK);
+ nrf_usbd_ep_all_disable();
+}
+
+nrfx_err_t nrfx_usbd_ep_transfer(
+ nrfx_usbd_ep_t ep,
+ nrfx_usbd_transfer_t const * p_transfer)
+{
+ nrfx_err_t ret;
+ const uint8_t ep_bitpos = ep2bit(ep);
+ NRFX_ASSERT(NULL != p_transfer);
+
+ NRFX_CRITICAL_SECTION_ENTER();
+ /* Setup data transaction can go only in one direction at a time */
+ if ((NRF_USBD_EP_NR_GET(ep) == 0) && (ep != m_last_setup_dir))
+ {
+ ret = NRFX_ERROR_INVALID_ADDR;
+ if (NRFX_USBD_FAILED_TRANSFERS_DEBUG &&
+ (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep))))
+ {
+ NRFX_LOG_DEBUG("Transfer failed: Invalid EPr\n");
+ }
+ }
+ else if ((m_ep_dma_waiting | ((~m_ep_ready) & NRFX_USBD_EPIN_BIT_MASK)) & (1U << ep_bitpos))
+ {
+ /* IN (Device -> Host) transfer has to be transmitted out to allow new transmission */
+ ret = NRFX_ERROR_BUSY;
+ if (NRFX_USBD_FAILED_TRANSFERS_DEBUG)
+ {
+ NRFX_LOG_DEBUG("Transfer failed: EP is busy");
+ }
+ }
+ else
+ {
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+ /* Prepare transfer context and handler description */
+ nrfx_usbd_transfer_t * p_context;
+ if (NRF_USBD_EPIN_CHECK(ep))
+ {
+ p_context = m_ep_feeder_state + NRF_USBD_EP_NR_GET(ep);
+ if (nrfx_is_in_ram(p_transfer->p_data.tx))
+ {
+ /* RAM */
+ if (0 == (p_transfer->flags & NRFX_USBD_TRANSFER_ZLP_FLAG))
+ {
+ p_state->handler.feeder = nrfx_usbd_feeder_ram;
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG(
+ "Transfer called on endpoint %x, size: %u, mode: "
+ "RAM",
+ ep,
+ p_transfer->size);
+ }
+ }
+ else
+ {
+ p_state->handler.feeder = nrfx_usbd_feeder_ram_zlp;
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG(
+ "Transfer called on endpoint %x, size: %u, mode: "
+ "RAM_ZLP",
+ ep,
+ p_transfer->size);
+ }
+ }
+ }
+ else
+ {
+ /* Flash */
+ if (0 == (p_transfer->flags & NRFX_USBD_TRANSFER_ZLP_FLAG))
+ {
+ p_state->handler.feeder = nrfx_usbd_feeder_flash;
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG(
+ "Transfer called on endpoint %x, size: %u, mode: "
+ "FLASH",
+ ep,
+ p_transfer->size);
+ }
+ }
+ else
+ {
+ p_state->handler.feeder = nrfx_usbd_feeder_flash_zlp;
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG(
+ "Transfer called on endpoint %x, size: %u, mode: "
+ "FLASH_ZLP",
+ ep,
+ p_transfer->size);
+ }
+ }
+ }
+ }
+ else
+ {
+ p_context = m_ep_consumer_state + NRF_USBD_EP_NR_GET(ep);
+ NRFX_ASSERT((p_transfer->p_data.rx == NULL) || (nrfx_is_in_ram(p_transfer->p_data.rx)));
+ p_state->handler.consumer = nrfx_usbd_consumer;
+ }
+ *p_context = *p_transfer;
+ p_state->p_context = p_context;
+
+ p_state->transfer_cnt = 0;
+ p_state->status = NRFX_USBD_EP_OK;
+ m_ep_dma_waiting |= 1U << ep_bitpos;
+ ret = NRFX_SUCCESS;
+ usbd_int_rise();
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ return ret;
+}
+
+nrfx_err_t nrfx_usbd_ep_handled_transfer(
+ nrfx_usbd_ep_t ep,
+ nrfx_usbd_handler_desc_t const * p_handler)
+{
+ nrfx_err_t ret;
+ const uint8_t ep_bitpos = ep2bit(ep);
+ NRFX_ASSERT(NULL != p_handler);
+
+ NRFX_CRITICAL_SECTION_ENTER();
+ /* Setup data transaction can go only in one direction at a time */
+ if ((NRF_USBD_EP_NR_GET(ep) == 0) && (ep != m_last_setup_dir))
+ {
+ ret = NRFX_ERROR_INVALID_ADDR;
+ if (NRFX_USBD_FAILED_TRANSFERS_DEBUG && (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep))))
+ {
+ NRFX_LOG_DEBUG("Transfer failed: Invalid EP");
+ }
+ }
+ else if ((m_ep_dma_waiting | ((~m_ep_ready) & NRFX_USBD_EPIN_BIT_MASK)) & (1U << ep_bitpos))
+ {
+ /* IN (Device -> Host) transfer has to be transmitted out to allow a new transmission */
+ ret = NRFX_ERROR_BUSY;
+ if (NRFX_USBD_FAILED_TRANSFERS_DEBUG && (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep))))
+ {
+ NRFX_LOG_DEBUG("Transfer failed: EP is busy");
+ }
+ }
+ else
+ {
+ /* Transfer can be configured now */
+ usbd_ep_state_t * p_state = ep_state_access(ep);
+
+ p_state->transfer_cnt = 0;
+ p_state->handler = p_handler->handler;
+ p_state->p_context = p_handler->p_context;
+ p_state->status = NRFX_USBD_EP_OK;
+ m_ep_dma_waiting |= 1U << ep_bitpos;
+
+ ret = NRFX_SUCCESS;
+ if (NRFX_USBD_ISO_DEBUG || (!NRF_USBD_EPISO_CHECK(ep)))
+ {
+ NRFX_LOG_DEBUG("Transfer called on endpoint %x, mode: Handler", ep);
+ }
+ usbd_int_rise();
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ return ret;
+}
+
+void * nrfx_usbd_feeder_buffer_get(void)
+{
+ return m_tx_buffer;
+}
+
+nrfx_usbd_ep_status_t nrfx_usbd_ep_status_get(nrfx_usbd_ep_t ep, size_t * p_size)
+{
+ nrfx_usbd_ep_status_t ret;
+
+ usbd_ep_state_t const * p_state = ep_state_access(ep);
+ NRFX_CRITICAL_SECTION_ENTER();
+ *p_size = p_state->transfer_cnt;
+ ret = (p_state->handler.consumer == NULL) ? p_state->status : NRFX_USBD_EP_BUSY;
+ NRFX_CRITICAL_SECTION_EXIT();
+ return ret;
+}
+
+size_t nrfx_usbd_epout_size_get(nrfx_usbd_ep_t ep)
+{
+ return nrf_usbd_epout_size_get(ep_to_hal(ep));
+}
+
+bool nrfx_usbd_ep_is_busy(nrfx_usbd_ep_t ep)
+{
+ return (0 != ((m_ep_dma_waiting | ((~m_ep_ready) & NRFX_USBD_EPIN_BIT_MASK)) & (1U << ep2bit(ep))));
+}
+
+void nrfx_usbd_ep_stall(nrfx_usbd_ep_t ep)
+{
+ NRFX_LOG_DEBUG("USB: EP %x stalled.", ep);
+ nrf_usbd_ep_stall(ep_to_hal(ep));
+}
+
+void nrfx_usbd_ep_stall_clear(nrfx_usbd_ep_t ep)
+{
+ if (NRF_USBD_EPOUT_CHECK(ep) && nrfx_usbd_ep_stall_check(ep))
+ {
+ nrfx_usbd_transfer_out_drop(ep);
+ }
+ nrf_usbd_ep_unstall(ep_to_hal(ep));
+}
+
+bool nrfx_usbd_ep_stall_check(nrfx_usbd_ep_t ep)
+{
+ return nrf_usbd_ep_is_stall(ep_to_hal(ep));
+}
+
+void nrfx_usbd_ep_dtoggle_clear(nrfx_usbd_ep_t ep)
+{
+ nrf_usbd_dtoggle_set(ep, NRF_USBD_DTOGGLE_DATA0);
+}
+
+void nrfx_usbd_setup_get(nrfx_usbd_setup_t * p_setup)
+{
+ memset(p_setup, 0, sizeof(nrfx_usbd_setup_t));
+ p_setup->bmRequestType = nrf_usbd_setup_bmrequesttype_get();
+ p_setup->bmRequest = nrf_usbd_setup_brequest_get();
+ p_setup->wValue = nrf_usbd_setup_wvalue_get();
+ p_setup->wIndex = nrf_usbd_setup_windex_get();
+ p_setup->wLength = nrf_usbd_setup_wlength_get();
+}
+
+void nrfx_usbd_setup_data_clear(void)
+{
+ if (nrfx_usbd_errata_104())
+ {
+ /* For this fix to work properly, it must be ensured that the task is
+ * executed twice one after another - blocking ISR. This is however a temporary
+ * solution to be used only before production version of the chip. */
+ uint32_t primask_copy = __get_PRIMASK();
+ __disable_irq();
+ nrf_usbd_task_trigger(NRF_USBD_TASK_EP0RCVOUT);
+ nrf_usbd_task_trigger(NRF_USBD_TASK_EP0RCVOUT);
+ __set_PRIMASK(primask_copy);
+ }
+ else
+ {
+ nrf_usbd_task_trigger(NRF_USBD_TASK_EP0RCVOUT);
+ }
+}
+
+void nrfx_usbd_setup_clear(void)
+{
+ NRFX_LOG_DEBUG(">> ep0status >>");
+ nrf_usbd_task_trigger(NRF_USBD_TASK_EP0STATUS);
+}
+
+void nrfx_usbd_setup_stall(void)
+{
+ NRFX_LOG_DEBUG("Setup stalled.");
+ nrf_usbd_task_trigger(NRF_USBD_TASK_EP0STALL);
+}
+
+nrfx_usbd_ep_t nrfx_usbd_last_setup_dir_get(void)
+{
+ return m_last_setup_dir;
+}
+
+void nrfx_usbd_transfer_out_drop(nrfx_usbd_ep_t ep)
+{
+ NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep));
+
+ if (nrfx_usbd_errata_200())
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ m_ep_ready &= ~(1U << ep2bit(ep));
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7C5 + (2u * NRF_USBD_EP_NR_GET(ep));
+ *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = 0;
+ (void)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+ else
+ {
+ NRFX_CRITICAL_SECTION_ENTER();
+ m_ep_ready &= ~(1U << ep2bit(ep));
+ if (!NRF_USBD_EPISO_CHECK(ep))
+ {
+ nrf_usbd_epout_clear(ep);
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+ }
+}
+
+#endif // NRFX_CHECK(NRFX_USBD_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
new file mode 100644
index 0000000000..b95d780b38
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_USBD_ERRATA_H__
+#define NRFX_USBD_ERRATA_H__
+
+#include <stdbool.h>
+
+#ifndef NRFX_USBD_ERRATA_ENABLE
+/**
+ * @brief The constant that informs if errata should be enabled at all.
+ *
+ * If this constant is set to 0, all the Errata bug fixes will be automatically disabled.
+ */
+#define NRFX_USBD_ERRATA_ENABLE 1
+#endif
+
+static inline bool nrfx_usbd_errata_type_52840(void)
+{
+ return (*(uint32_t *)0x10000130UL == 0x8UL);
+}
+
+static inline bool nrfx_usbd_errata_type_52840_eng_a(void)
+{
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x0UL));
+}
+
+static inline bool nrfx_usbd_errata_type_52840_eng_b(void)
+{
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x1UL));
+}
+
+static inline bool nrfx_usbd_errata_type_52840_eng_c(void)
+{
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x2UL));
+}
+
+static inline bool nrfx_usbd_errata_type_52840_eng_d(void)
+{
+ return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x3UL));
+}
+
+/* Errata: USBD: EPDATA event is not always generated. */
+static inline bool nrfx_usbd_errata_104(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
+}
+
+/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. */
+static inline bool nrfx_usbd_errata_154(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
+}
+
+/* Errata: ISO double buffering not functional. */
+static inline bool nrfx_usbd_errata_166(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && true);
+}
+
+/* Errata: USBD might not reach its active state. */
+static inline bool nrfx_usbd_errata_171(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && true);
+}
+
+/* Errata: USB cannot be enabled. */
+static inline bool nrfx_usbd_errata_187(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE &&
+ (nrfx_usbd_errata_type_52840_eng_b() ||
+ nrfx_usbd_errata_type_52840_eng_c() ||
+ nrfx_usbd_errata_type_52840_eng_d())
+ );
+}
+
+/* Errata: USBD cannot receive tasks during DMA. */
+static inline bool nrfx_usbd_errata_199(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && true);
+}
+
+/* Errata: SIZE.EPOUT not writable. */
+static inline bool nrfx_usbd_errata_200(void)
+{
+ return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a());
+}
+
+#endif // NRFX_USBD_ERRATA_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
index 0598041154..4896a9fe63 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_wdt.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -52,8 +52,8 @@ void nrfx_wdt_irq_handler(void)
{
if (nrf_wdt_int_enable_check(NRF_WDT_INT_TIMEOUT_MASK) == true)
{
- nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT);
m_wdt_event_handler();
+ nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT);
}
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
index 24cafeb5c8..c5e4ba5db3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
index 2ce29cc70b..b267988fe0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
index bcc5913bd2..97a8cdb384 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_adc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
new file mode 100644
index 0000000000..7546cb50d4
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
@@ -0,0 +1,497 @@
+/*
+ * Copyright (c) 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_CCM_H__
+#define NRF_CCM_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_ccm_hal AES CCM HAL
+ * @{
+ * @ingroup nrf_ccm
+ * @brief Hardware access layer for managing the AES CCM peripheral.
+ */
+
+/**
+ * @brief CCM tasks.
+ */
+typedef enum
+{
+ /*lint -save -e30*/
+ NRF_CCM_TASK_KSGEN = offsetof(NRF_CCM_Type, TASKS_KSGEN), ///< Start generation of key-stream.
+ NRF_CCM_TASK_CRYPT = offsetof(NRF_CCM_Type, TASKS_CRYPT), ///< Start encryption/decryption.
+ NRF_CCM_TASK_STOP = offsetof(NRF_CCM_Type, TASKS_STOP), ///< Stop encryption/decryption.
+#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__)
+ NRF_CCM_TASK_RATEOVERRIDE = offsetof(NRF_CCM_Type, TASKS_RATEOVERRIDE), ///< Override DATARATE setting in MODE register.
+#endif
+ /*lint -restore*/
+} nrf_ccm_task_t;
+
+/**
+ * @brief CCM events.
+ */
+typedef enum
+{
+ /*lint -save -e30*/
+ NRF_CCM_EVENT_ENDKSGEN = offsetof(NRF_CCM_Type, EVENTS_ENDKSGEN), ///< Keystream generation complete.
+ NRF_CCM_EVENT_ENDCRYPT = offsetof(NRF_CCM_Type, EVENTS_ENDCRYPT), ///< Encrypt/decrypt complete.
+ NRF_CCM_EVENT_ERROR = offsetof(NRF_CCM_Type, EVENTS_ERROR), ///< CCM error event.
+ /*lint -restore*/
+} nrf_ccm_event_t;
+
+/**
+ * @brief CCM interrupts.
+ */
+typedef enum
+{
+ NRF_CCM_INT_ENDKSGEN_MASK = CCM_INTENSET_ENDKSGEN_Msk, ///< Interrupt on ENDKSGEN event.
+ NRF_CCM_INT_ENDCRYPT_MASK = CCM_INTENSET_ENDCRYPT_Msk, ///< Interrupt on ENDCRYPT event.
+ NRF_CCM_INT_ERROR_MASK = CCM_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
+} nrf_ccm_int_mask_t;
+
+/**
+ * @brief CCM modes of operation.
+ */
+typedef enum
+{
+ NRF_CCM_MODE_ENCRYPTION = CCM_MODE_MODE_Encryption, ///< Encryption mode.
+ NRF_CCM_MODE_DECRYPTION = CCM_MODE_MODE_Decryption, ///< Decryption mode.
+} nrf_ccm_mode_t;
+
+#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief CCM data rates.
+ */
+typedef enum
+{
+ NRF_CCM_DATARATE_1M = CCM_MODE_DATARATE_1Mbit, ///< 1 Mbps.
+ NRF_CCM_DATARATE_2M = CCM_MODE_DATARATE_2Mbit, ///< 2 Mbps.
+#if defined(CCM_MODE_DATARATE_125Kbps) || defined(__NRFX_DOXYGEN__)
+ NRF_CCM_DATARATE_125K = CCM_MODE_DATARATE_125Kbps, ///< 125 Kbps.
+#endif
+#if defined(CCM_MODE_DATARATE_500Kbps) || defined(__NRFX_DOXYGEN__)
+ NRF_CCM_DATARATE_500K = CCM_MODE_DATARATE_500Kbps, ///< 500 Kbps.
+#endif
+} nrf_ccm_datarate_t;
+#endif // defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
+
+#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief CCM packet length options.
+ */
+typedef enum
+{
+ NRF_CCM_LENGTH_DEFAULT = CCM_MODE_LENGTH_Default, ///< Default length.
+ NRF_CCM_LENGTH_EXTENDED = CCM_MODE_LENGTH_Extended, ///< Extended length.
+} nrf_ccm_length_t;
+#endif // defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief CCM configuration.
+ */
+typedef struct {
+ nrf_ccm_mode_t mode;
+#if defined(CCM_MODE_DATARATE_Pos) || defined(__NRFX_DOXYGEN__)
+ nrf_ccm_datarate_t datarate;
+#endif
+#if defined(CCM_MODE_LENGTH_Pos) || defined(__NRFX_DOXYGEN__)
+ nrf_ccm_length_t length;
+#endif
+} nrf_ccm_config_t;
+
+/**
+ * @brief Function for activating a specific CCM task.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task Task to activate.
+ */
+__STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg,
+ nrf_ccm_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific CCM task register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_ccm_task_address_get(NRF_CCM_Type const * p_reg,
+ nrf_ccm_task_t task);
+
+/**
+ * @brief Function for clearing a specific CCM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg,
+ nrf_ccm_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific CCM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to check.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg,
+ nrf_ccm_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific CCM event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg,
+ nrf_ccm_event_t event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] ccm_int Interrupt to check.
+ *
+ * @retval true If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg,
+ nrf_ccm_int_mask_t ccm_int);
+
+/**
+ * @brief Function for enabling the CCM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_ccm_enable(NRF_CCM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the CCM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_ccm_disable(NRF_CCM_Type * p_reg);
+
+/**
+ * @brief Function for setting the CCM peripheral configuration.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_config Pointer to the structure with configuration to be set.
+ */
+__STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg,
+ nrf_ccm_config_t const * p_config);
+
+#if defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting the length of key-stream generated
+ * when the packet length is configured as extended.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] size Maximum length of the key-stream.
+ */
+__STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg,
+ uint8_t size);
+#endif // defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for getting the MIC check result.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @retval true If the MIC check passed.
+ * @retval false If the MIC check failed.
+ */
+__STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg);
+
+/**
+ * @brief Function for setting the pointer to the data structure
+ * holding the AES key and the CCM NONCE vector.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_data Pointer to the data structure.
+ */
+__STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data);
+
+/**
+ * @brief Function for getting the pointer to the data structure
+ * holding the AES key and the CCM NONCE vector.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Pointer to the data structure.
+ */
+__STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg);
+
+/**
+ * @brief Function for setting the input data pointer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_data Input data pointer.
+ */
+__STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data);
+
+/**
+ * @brief Function for getting the input data pointer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Input data pointer.
+ */
+__STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg);
+
+/**
+ * @brief Function for setting the output data pointer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_data Output data pointer.
+ */
+__STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data);
+
+/**
+ * @brief Function for getting the output data pointer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Output data pointer.
+ */
+__STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg);
+
+/**
+ * @brief Function for setting the pointer to the scratch area used for
+ * temporary storage.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] p_area Pointer to the scratch area.
+ */
+__STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_area);
+
+/**
+ * @brief Function for getting the pointer to the scratch area.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Pointer to the scratch area.
+ */
+__STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg);
+
+#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting the data rate override value.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] datarate Override value to be applied when the RATEOVERRIDE task
+ * is triggered.
+ */
+__STATIC_INLINE void nrf_ccm_datarate_override_set(NRF_CCM_Type * p_reg,
+ nrf_ccm_datarate_t datarate);
+#endif // defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) || defined(__NRFX_DOXYGEN__)
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_ccm_task_trigger(NRF_CCM_Type * p_reg,
+ nrf_ccm_task_t task)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_ccm_task_address_get(NRF_CCM_Type const * p_reg,
+ nrf_ccm_task_t task)
+{
+ return ((uint32_t)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg,
+ nrf_ccm_event_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg,
+ nrf_ccm_event_t event)
+{
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg,
+ nrf_ccm_event_t event)
+{
+ return ((uint32_t)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_ccm_int_disable(NRF_CCM_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENCLR = mask;
+}
+
+__STATIC_INLINE bool nrf_ccm_int_enable_check(NRF_CCM_Type const * p_reg,
+ nrf_ccm_int_mask_t ccm_int)
+{
+ return (bool)(p_reg->INTENSET & ccm_int);
+}
+
+__STATIC_INLINE void nrf_ccm_enable(NRF_CCM_Type * p_reg)
+{
+ p_reg->ENABLE = (CCM_ENABLE_ENABLE_Enabled << CCM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_ccm_disable(NRF_CCM_Type * p_reg)
+{
+ p_reg->ENABLE = (CCM_ENABLE_ENABLE_Disabled << CCM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_ccm_configure(NRF_CCM_Type * p_reg,
+ nrf_ccm_config_t const * p_config)
+{
+ p_reg->MODE = (((uint32_t)p_config->mode << CCM_MODE_MODE_Pos) |
+#if defined(CCM_MODE_DATARATE_Pos)
+ ((uint32_t)p_config->datarate << CCM_MODE_DATARATE_Pos) |
+#endif
+#if defined(CCM_MODE_LENGTH_Pos)
+ ((uint32_t)p_config->length << CCM_MODE_LENGTH_Pos) |
+#endif
+ 0);
+}
+
+#if defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
+__STATIC_INLINE void nrf_ccm_maxpacketsize_set(NRF_CCM_Type * p_reg,
+ uint8_t size)
+{
+ NRFX_ASSERT((size >= 0x1B) && (size <= 0xFB));
+
+ p_reg->MAXPACKETSIZE = size;
+}
+#endif // defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
+
+__STATIC_INLINE bool nrf_ccm_micstatus_get(NRF_CCM_Type const * p_reg)
+{
+ return (bool)(p_reg->MICSTATUS);
+}
+
+__STATIC_INLINE void nrf_ccm_cnfptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data)
+{
+ p_reg->CNFPTR = (uint32_t)p_data;
+}
+
+__STATIC_INLINE uint32_t * nrf_ccm_cnfptr_get(NRF_CCM_Type const * p_reg)
+{
+ return (uint32_t *)(p_reg->CNFPTR);
+}
+
+__STATIC_INLINE void nrf_ccm_inptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data)
+{
+ p_reg->INPTR = (uint32_t)p_data;
+}
+
+__STATIC_INLINE uint32_t * nrf_ccm_inptr_get(NRF_CCM_Type const * p_reg)
+{
+ return (uint32_t *)(p_reg->INPTR);
+}
+
+__STATIC_INLINE void nrf_ccm_outptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_data)
+{
+ p_reg->OUTPTR = (uint32_t)p_data;
+}
+
+__STATIC_INLINE uint32_t * nrf_ccm_outptr_get(NRF_CCM_Type const * p_reg)
+{
+ return (uint32_t *)(p_reg->OUTPTR);
+}
+
+__STATIC_INLINE void nrf_ccm_scratchptr_set(NRF_CCM_Type * p_reg,
+ uint32_t const * p_area)
+{
+ p_reg->SCRATCHPTR = (uint32_t)p_area;
+}
+
+__STATIC_INLINE uint32_t * nrf_ccm_stratchptr_get(NRF_CCM_Type const * p_reg)
+{
+ return (uint32_t *)(p_reg->SCRATCHPTR);
+}
+
+#if defined(CCM_RATEOVERRIDE_RATEOVERRIDE_Pos)
+__STATIC_INLINE void nrf_ccm_datarate_override_set(NRF_CCM_Type * p_reg,
+ nrf_ccm_datarate_t datarate)
+{
+ p_reg->RATEOVERRIDE = ((uint32_t)datarate << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos);
+}
+#endif
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_CCM_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
index 3140f445c2..33455e8a95 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -51,15 +51,37 @@ extern "C" {
#define NRF_CLOCK_TASK_TRIGGER (1UL)
#define NRF_CLOCK_EVENT_CLEAR (0UL)
+#if defined(NRF52810_XXAA) || \
+ defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
+ defined(NRF52840_XXAA)
+// Enable support for external LFCLK sources. Read more in the Product Specification.
+#define NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES
+#endif
+
/**
* @brief Low-frequency clock sources.
* @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
*/
typedef enum
{
- NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
- NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
- NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */
+ NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
+ NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
+ NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesizer from HFCLK system clock. */
+#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
+ /**
+ * External 32 kHz low swing signal. Used only with the LFCLKSRC register.
+ * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting.
+ */
+ NRF_CLOCK_LFCLK_Xtal_Low_Swing = (CLOCK_LFCLKSRC_SRC_Xtal |
+ (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)),
+ /**
+ * External 32 kHz full swing signal. Used only with the LFCLKSRC register.
+ * For the others @ref NRF_CLOCK_LFCLK_Xtal is returned for this setting.
+ */
+ NRF_CLOCK_LFCLK_Xtal_Full_Swing = (CLOCK_LFCLKSRC_SRC_Xtal |
+ (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) |
+ (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)),
+#endif // defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
} nrf_clock_lfclk_t;
/**
@@ -321,14 +343,12 @@ __STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event)
__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source)
{
- NRF_CLOCK->LFCLKSRC =
- (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
+ NRF_CLOCK->LFCLKSRC = (uint32_t)(source);
}
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void)
{
- return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC &
- CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos);
+ return (nrf_clock_lfclk_t)(NRF_CLOCK->LFCLKSRC);
}
__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
index 3c75be6e5d..7663491327 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.c b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.c
index 9458f21e69..b83935e724 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.c
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
index c0d1b4df30..25e7200ec5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -39,7 +39,7 @@ extern "C" {
#endif
/**
- * @defgroup nrf_ecb_hal AES ECB encryption HAL
+ * @defgroup nrf_ecb_drv AES ECB encryption driver
* @{
* @ingroup nrf_ecb
* @brief Driver for the AES Electronic Code Book (ECB) peripheral.
@@ -80,6 +80,205 @@ void nrf_ecb_set_key(const uint8_t * key);
/** @} */
+/**
+ * @defgroup nrf_ecb_hal AES ECB encryption HAL
+ * @{
+ * @ingroup nrf_ecb
+ * @brief Hardware access layer for managing the AES Electronic Codebook (ECB) peripheral.
+ */
+
+/**
+ * @brief ECB tasks.
+ */
+typedef enum
+{
+ /*lint -save -e30 -esym(628,__INTADDR__)*/
+ NRF_ECB_TASK_STARTECB = offsetof(NRF_ECB_Type, TASKS_STARTECB), /**< Task for starting ECB block encryption. */
+ NRF_ECB_TASK_STOPECB = offsetof(NRF_ECB_Type, TASKS_STOPECB), /**< Task for stopping ECB block encryption. */
+ /*lint -restore*/
+} nrf_ecb_task_t;
+
+/**
+ * @brief ECB events.
+ */
+typedef enum
+{
+ /*lint -save -e30*/
+ NRF_ECB_EVENT_ENDECB = offsetof(NRF_ECB_Type, EVENTS_ENDECB), /**< ECB block encrypt complete. */
+ NRF_ECB_EVENT_ERRORECB = offsetof(NRF_ECB_Type, EVENTS_ERRORECB), /**< ECB block encrypt aborted because of a STOPECB task or due to an error. */
+ /*lint -restore*/
+} nrf_ecb_event_t;
+
+/**
+ * @brief ECB interrupts.
+ */
+typedef enum
+{
+ NRF_ECB_INT_ENDECB_MASK = ECB_INTENSET_ENDECB_Msk, ///< Interrupt on ENDECB event.
+ NRF_ECB_INT_ERRORECB_MASK = ECB_INTENSET_ERRORECB_Msk, ///< Interrupt on ERRORECB event.
+} nrf_ecb_int_mask_t;
+
+
+/**
+ * @brief Function for activating a specific ECB task.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] task Task to activate.
+ */
+__STATIC_INLINE void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific ECB task register.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg,
+ nrf_ecb_task_t task);
+
+/**
+ * @brief Function for clearing a specific ECB event.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific ECB event.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] event Event to check.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific ECB event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_ecb_event_address_get(NRF_ECB_Type const * p_reg,
+ nrf_ecb_event_t event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] ecb_int Interrupt to check.
+ *
+ * @retval true If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg,
+ nrf_ecb_int_mask_t ecb_int);
+
+/**
+ * @brief Function for setting the pointer to the ECB data buffer.
+ *
+ * @note The buffer has to be placed in the Data RAM region.
+ * For description of the data structure in this buffer, see the Product Specification.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ * @param[in] p_buffer Pointer to the ECB data buffer.
+ */
+__STATIC_INLINE void nrf_ecb_data_pointer_set(NRF_ECB_Type * p_reg, void const * p_buffer);
+
+/**
+ * @brief Function for getting the pointer to the ECB data buffer.
+ *
+ * @param[in] p_reg Pointer to the peripheral register structure.
+ *
+ * @return Pointer to the ECB data buffer.
+ */
+__STATIC_INLINE void * nrf_ecb_data_pointer_get(NRF_ECB_Type const * p_reg);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_ecb_task_trigger(NRF_ECB_Type * p_reg, nrf_ecb_task_t task)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg,
+ nrf_ecb_task_t task)
+{
+ return ((uint32_t)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event)
+{
+ return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_ecb_event_address_get(NRF_ECB_Type const * p_reg,
+ nrf_ecb_event_t event)
+{
+ return ((uint32_t)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_ecb_int_enable(NRF_ECB_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_ecb_int_disable(NRF_ECB_Type * p_reg, uint32_t mask)
+{
+ p_reg->INTENCLR = mask;
+}
+
+__STATIC_INLINE bool nrf_ecb_int_enable_check(NRF_ECB_Type const * p_reg,
+ nrf_ecb_int_mask_t ecb_int)
+{
+ return (bool)(p_reg->INTENSET & ecb_int);
+}
+
+__STATIC_INLINE void nrf_ecb_data_pointer_set(NRF_ECB_Type * p_reg, void const * p_buffer)
+{
+ p_reg->ECBDATAPTR = (uint32_t)p_buffer;
+}
+
+__STATIC_INLINE void * nrf_ecb_data_pointer_get(NRF_ECB_Type const * p_reg)
+{
+ return (void *)(p_reg->ECBDATAPTR);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
index dc6709f46b..5ff23ffb92 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
index 94544edce7..253bd7b591 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -312,6 +312,24 @@ __STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
*/
__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
+/**
+ * @brief Function for reading the direction configuration of a GPIO pin.
+ *
+ * @param pin_number Specifies the pin number to read.
+ *
+ * @retval Direction configuration.
+ */
+__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number);
+
+/**
+ * @brief Function for reading the pull configuration of a GPIO pin.
+ *
+ * @param pin_number Specifies the pin number to read.
+ *
+ * @retval Pull configuration.
+ */
+__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number);
+
/**
* @brief Function for setting output direction on selected pins on a given port.
*
@@ -665,6 +683,24 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
}
+__STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number)
+{
+ NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+ return (nrf_gpio_pin_dir_t)((reg->PIN_CNF[pin_number] &
+ GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos);
+}
+
+
+__STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number)
+{
+ NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+ return (nrf_gpio_pin_pull_t)((reg->PIN_CNF[pin_number] &
+ GPIO_PIN_CNF_PULL_Msk) >> GPIO_PIN_CNF_PULL_Pos);
+}
+
+
__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
{
p_reg->DIRSET = out_mask;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
index 0e44941e48..ab923af740 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -292,6 +292,15 @@ __STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t in
*/
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
+/**@brief Function for checking if particular Task-Event is enabled.
+ *
+ * @param[in] idx Task-Event index.
+ *
+ * @retval true If the Task-Event mode is set to Task or Event.
+ * @retval false If the Task-Event mode is set to Disabled.
+ */
+__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx);
+
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
{
@@ -408,6 +417,11 @@ __STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
{
NRF_GPIOTE->CONFIG[idx] = 0;
}
+
+__STATIC_INLINE bool nrf_gpiote_te_is_enabled(uint32_t idx)
+{
+ return (NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_MODE_Msk) != GPIOTE_CONFIG_MODE_Disabled;
+}
#endif //SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
index 7d77a4d9ef..91053a9166 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
index c1ab7f77fa..d7347e602f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
new file mode 100644
index 0000000000..57560e16f5
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
@@ -0,0 +1,1070 @@
+/*
+ * Copyright (c) 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_NFCT_H__
+#define NRF_NFCT_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_nfct_hal NFCT HAL
+ * @{
+ * @ingroup nrf_nfct
+ *
+ * @brief Hardware access layer (HAL) for the Near Field Communication Tag (NFCT) peripheral.
+ */
+
+#define NRF_NFCT_CRC_SIZE 2 /**< CRC size in bytes. */
+
+/**
+ * @brief NFCT tasks
+ */
+typedef enum /*lint -save -e30 */
+{
+ NRF_NFCT_TASK_ACTIVATE = offsetof(NRF_NFCT_Type, TASKS_ACTIVATE), /**< Activate the NFCT peripheral for the incoming and outgoing frames, change state to activated. */
+ NRF_NFCT_TASK_DISABLE = offsetof(NRF_NFCT_Type, TASKS_DISABLE), /**< Disable the NFCT peripheral. */
+ NRF_NFCT_TASK_SENSE = offsetof(NRF_NFCT_Type, TASKS_SENSE), /**< Enable the NFC sense field mode, change state to sense mode. */
+ NRF_NFCT_TASK_STARTTX = offsetof(NRF_NFCT_Type, TASKS_STARTTX), /**< Start the transmission of an outgoing frame, change state to transmit. */
+ NRF_NFCT_TASK_ENABLERXDATA = offsetof(NRF_NFCT_Type, TASKS_ENABLERXDATA), /**< Initialize EasyDMA for receive. */
+ NRF_NFCT_TASK_GOIDLE = offsetof(NRF_NFCT_Type, TASKS_GOIDLE), /**< Force state machine to the IDLE state. */
+ NRF_NFCT_TASK_GOSLEEP = offsetof(NRF_NFCT_Type, TASKS_GOSLEEP), /**< Force state machine to the SLEEP_A state. */
+} nrf_nfct_task_t; /*lint -restore */
+
+/**
+ * @brief NFCT events
+ */
+typedef enum /*lint -save -e30 */
+{
+ NRF_NFCT_EVENT_READY = offsetof(NRF_NFCT_Type, EVENTS_READY), /**< The NFCT peripheral is ready to receive and send frames. */
+ NRF_NFCT_EVENT_FIELDDETECTED = offsetof(NRF_NFCT_Type, EVENTS_FIELDDETECTED), /**< Remote NFC field is detected. */
+ NRF_NFCT_EVENT_FIELDLOST = offsetof(NRF_NFCT_Type, EVENTS_FIELDLOST), /**< Remote NFC field is lost. */
+ NRF_NFCT_EVENT_TXFRAMESTART = offsetof(NRF_NFCT_Type, EVENTS_TXFRAMESTART), /**< The start of the first symbol of a transmitted frame. */
+ NRF_NFCT_EVENT_TXFRAMEEND = offsetof(NRF_NFCT_Type, EVENTS_TXFRAMEEND), /**< The end of the last transmitted on-air symbol of a frame. */
+ NRF_NFCT_EVENT_RXFRAMESTART = offsetof(NRF_NFCT_Type, EVENTS_RXFRAMESTART), /**< The end of the first symbol of a received frame. */
+ NRF_NFCT_EVENT_RXFRAMEEND = offsetof(NRF_NFCT_Type, EVENTS_RXFRAMEEND), /**< Received data was checked (CRC, parity) and transferred to RAM, and EasyDMA ended accessing the RX buffer. */
+ NRF_NFCT_EVENT_ERROR = offsetof(NRF_NFCT_Type, EVENTS_ERROR), /**< NFC error reported. The ERRORSTATUS register contains details on the source of the error. */
+ NRF_NFCT_EVENT_RXERROR = offsetof(NRF_NFCT_Type, EVENTS_RXERROR), /**< NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */
+ NRF_NFCT_EVENT_ENDRX = offsetof(NRF_NFCT_Type, EVENTS_ENDRX), /**< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
+ NRF_NFCT_EVENT_ENDTX = offsetof(NRF_NFCT_Type, EVENTS_ENDTX), /**< Transmission of data in RAM ended, and EasyDMA ended accessing the TX buffer. */
+ NRF_NFCT_EVENT_AUTOCOLRESSTARTED = offsetof(NRF_NFCT_Type, EVENTS_AUTOCOLRESSTARTED), /**< Auto collision resolution process started. */
+ NRF_NFCT_EVENT_COLLISION = offsetof(NRF_NFCT_Type, EVENTS_COLLISION), /**< NFC auto collision resolution error reported. */
+ NRF_NFCT_EVENT_SELECTED = offsetof(NRF_NFCT_Type, EVENTS_SELECTED), /**< NFC auto collision resolution successfully completed. */
+ NRF_NFCT_EVENT_STARTED = offsetof(NRF_NFCT_Type, EVENTS_STARTED), /**< EasyDMA is ready to receive or send frames. */
+} nrf_nfct_event_t; /*lint -restore */
+
+/**
+ * @brief NFCT shorts
+ */
+typedef enum
+{
+ NRF_NFCT_SHORT_FIELDDETECTED_ACTIVATE_MASK = NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk, /**< Shortcut between the FIELDDETECTED event and the ACTIVATE task. */
+ NRF_NFCT_SHORT_FIELDLOST_SENSE_MASK = NFCT_SHORTS_FIELDLOST_SENSE_Msk, /**< Shortcut between the FIELDLOST event and the SENSE task. */
+#if defined(NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_NFCT_SHORT_TXFRAMEEND_ENABLERXDATA_MASK = NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk, /**< Shortcut between the TXFRAMEEND event and the ENABLERXDATA task. */
+#endif // defined(NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk) || defined(__NRFX_DOXYGEN__)
+} nrf_nfct_short_mask_t;
+
+/**
+ * @brief NFCT interrupts
+ */
+typedef enum
+{
+ NRF_NFCT_INT_READY_MASK = NFCT_INTEN_READY_Msk, /**< Interrupt on READY event. */
+ NRF_NFCT_INT_FIELDDETECTED_MASK = NFCT_INTEN_FIELDDETECTED_Msk, /**< Interrupt on FIELDDETECTED event. */
+ NRF_NFCT_INT_FIELDLOST_MASK = NFCT_INTEN_FIELDLOST_Msk, /**< Interrupt on FIELDLOST event. */
+ NRF_NFCT_INT_TXFRAMESTART_MASK = NFCT_INTEN_TXFRAMESTART_Msk, /**< Interrupt on TXFRAMESTART event. */
+ NRF_NFCT_INT_TXFRAMEEND_MASK = NFCT_INTEN_TXFRAMEEND_Msk, /**< Interrupt on TXFRAMEEND event. */
+ NRF_NFCT_INT_RXFRAMESTART_MASK = NFCT_INTEN_RXFRAMESTART_Msk, /**< Interrupt on RXFRAMESTART event. */
+ NRF_NFCT_INT_RXFRAMEEND_MASK = NFCT_INTEN_RXFRAMEEND_Msk, /**< Interrupt on RXFRAMEEND event. */
+ NRF_NFCT_INT_ERROR_MASK = NFCT_INTEN_ERROR_Msk, /**< Interrupt on ERROR event. */
+ NRF_NFCT_INT_RXERROR_MASK = NFCT_INTEN_RXERROR_Msk, /**< Interrupt on RXERROR event. */
+ NRF_NFCT_INT_ENDRX_MASK = NFCT_INTEN_ENDRX_Msk, /**< Interrupt on ENDRX event. */
+ NRF_NFCT_INT_ENDTX_MASK = NFCT_INTEN_ENDTX_Msk, /**< Interrupt on ENDTX event. */
+ NRF_NFCT_INT_AUTOCOLRESSTARTED_MASK = NFCT_INTEN_AUTOCOLRESSTARTED_Msk, /**< Interrupt on AUTOCOLRESSTARTED event. */
+ NRF_NFCT_INT_COLLISION_MASK = NFCT_INTEN_COLLISION_Msk, /**< Interrupt on COLLISION event. */
+ NRF_NFCT_INT_SELECTED_MASK = NFCT_INTEN_SELECTED_Msk, /**< Interrupt on SELECTED event. */
+ NRF_NFCT_INT_STARTED_MASK = NFCT_INTEN_STARTED_Msk, /**< Interrupt on STARTED event. */
+} nrf_nfct_int_mask_t;
+
+/**
+ * @brief NFC error status bit masks.
+ */
+typedef enum
+{
+ NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK = NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk, /**< Timeout of the Frame Delay Timer (no frame transmission started in the FDT window). */
+#if defined(NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_NFCT_ERROR_NFCFIELDTOOSTRONG_MASK = NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk, /**< Field level is too high at maximum load resistance. */
+#endif // defined(NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk) || defined(__NRFX_DOXYGEN__)
+#if defined(NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_NFCT_ERROR_NFCFIELDTOOWEAK_MASK = NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk, /**< Field level is too low at minimum load resistance. */
+#endif // defined(NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk) || defined(__NRFX_DOXYGEN__)
+} nrf_nfct_error_status_t;
+
+/**
+ * @brief NFC received frame status bit masks.
+ */
+typedef enum
+{
+ NRF_NFCT_RX_FRAME_STATUS_CRC_MASK = NFCT_FRAMESTATUS_RX_CRCERROR_Msk, /**< CRC status mask. */
+ NRF_NFCT_RX_FRAME_STATUS_PARITY_MASK = NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk, /**< Parity status mask. */
+ NRF_NFCT_RX_FRAME_STATUS_OVERRUN_MASK = NFCT_FRAMESTATUS_RX_OVERRUN_Msk, /**< Overrun status mask. */
+} nrf_nfct_rx_frame_status_t;
+
+#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief NFC tag state.
+ */
+typedef enum
+{
+ NRF_NFCT_TAG_STATE_DISABLED = NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled, /**< Disabled or sensing NFC field. */
+ NRF_NFCT_TAG_STATE_RAMP_UP = NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp, /**< Ramping up. */
+ NRF_NFCT_TAG_STATE_IDLE = NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle, /**< Idle. */
+ NRF_NFCT_TAG_STATE_RECEIVE = NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive, /**< Receiving data. */
+ NRF_NFCT_TAG_STATE_FRAME_DELAY = NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay, /**< Counting Frame Delay Time since the last symbol of the last received frame. */
+ NRF_NFCT_TAG_STATE_TRANSMIT = NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit /**< Transmitting data. */
+} nrf_nfct_tag_state_t;
+#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief NFC tag sleep state.
+ *
+ * @details Shows the sleep state during automatic collision resolution
+ * according to the NFC Forum Activity Technical Specification v2.0.
+ */
+typedef enum
+{
+ NRF_NFCT_SLEEP_STATE_IDLE = NFCT_SLEEPSTATE_SLEEPSTATE_Idle, /**< 'IDLE' state. */
+ NRF_NFCT_SLEEP_STATE_SLEEP_A = NFCT_SLEEPSTATE_SLEEPSTATE_SleepA /**< 'SLEEP_A' state. */
+} nrf_nfct_sleep_state_t;
+#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief NFC field state bit masks.
+ */
+typedef enum
+{
+ NRF_NFCT_FIELD_STATE_PRESENT_MASK = NFCT_FIELDPRESENT_FIELDPRESENT_Msk, /**< Field presence mask. */
+ NRF_NFCT_FIELD_STATE_LOCK_MASK = NFCT_FIELDPRESENT_LOCKDETECT_Msk /**< Field lock mask. */
+} nrf_nfct_field_state_t;
+
+/**
+ * @brief NFC frame delay mode for data transmission.
+ */
+typedef enum
+{
+ NRF_NFCT_FRAME_DELAY_MODE_FREERUN = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun, /**< Frame transmission starts when @ref NRF_NFCT_TASK_STARTTX is set (delay timer is not used). */
+ NRF_NFCT_FRAME_DELAY_MODE_WINDOW = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window, /**< Frame transmission starts in a window between FRAMEDELAYMIN and FRAMEDELAYMAX. */
+ NRF_NFCT_FRAME_DELAY_MODE_EXACTVAL = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal, /**< Frame transmission starts when the delay timer reaches FRAMEDELAYMAX. */
+ NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID = NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid /**< Frame transmission starts in a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX. */
+} nrf_nfct_frame_delay_mode_t;
+
+/**
+ * @brief Bit masks for NFC transmission frame configuration.
+ */
+typedef enum
+{
+ NRF_NFCT_TX_FRAME_CONFIG_PARITY = NFCT_TXD_FRAMECONFIG_PARITY_Msk, /**< Indicates whether parity is added in the transmitted frames. */
+ NRF_NFCT_TX_FRAME_CONFIG_DISCARD_START = NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk, /**< Indicates whether unused bits are discarded at the start or at the end of the transmitted frames. */
+ NRF_NFCT_TX_FRAME_CONFIG_SOF = NFCT_TXD_FRAMECONFIG_SOF_Msk, /**< Indicates whether SoF symbol is added in the transmitted frames. */
+ NRF_NFCT_TX_FRAME_CONFIG_CRC16 = NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk /**< Indicates whether CRC is added in the transmitted frames. */
+} nrf_nfct_tx_frame_config_t;
+
+/**
+ * @brief Bit masks for NFC reception frame configuration.
+ */
+typedef enum
+{
+ NRF_NFCT_RX_FRAME_CONFIG_PARITY = NFCT_RXD_FRAMECONFIG_PARITY_Msk, /**< Indicates whether parity is expected in the received frames. */
+ NRF_NFCT_RX_FRAME_CONFIG_SOF = NFCT_RXD_FRAMECONFIG_SOF_Msk, /**< Indicates whether SoF symbol is expected in the received frames. */
+ NRF_NFCT_RX_FRAME_CONFIG_CRC16 = NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk /**< Indicates whether CRC is expected and checked in the received frames. */
+} nrf_nfct_rx_frame_config_t;
+
+/**
+ * @brief 'NFCI1 size' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ */
+typedef enum
+{
+ NRF_NFCT_SENSRES_NFCID1_SIZE_SINGLE =
+ NFCT_SENSRES_NFCIDSIZE_NFCID1Single << NFCT_SENSRES_NFCIDSIZE_Pos, /**< Single size NFCID1 (4 bytes). */
+ NRF_NFCT_SENSRES_NFCID1_SIZE_DOUBLE =
+ NFCT_SENSRES_NFCIDSIZE_NFCID1Double << NFCT_SENSRES_NFCIDSIZE_Pos, /**< Double size NFCID1 (7 bytes). */
+ NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE =
+ NFCT_SENSRES_NFCIDSIZE_NFCID1Triple << NFCT_SENSRES_NFCIDSIZE_Pos, /**< Triple size NFCID1 (10 bytes). */
+ NRF_NFCT_SENSRES_NFCID1_SIZE_DEFAULT =
+ NFCT_SENSRES_NFCIDSIZE_Msk /**< Default size. Use this option to leave NFCID1 size unchanged. */
+} nrf_nfct_sensres_nfcid1_size_t;
+
+/**
+ * @brief 'Bit frame SDD' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ */
+typedef enum
+{
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_00000 =
+ NFCT_SENSRES_BITFRAMESDD_SDD00000 << NFCT_SENSRES_BITFRAMESDD_Pos, /**< SDD pattern 00000. */
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_00001 =
+ NFCT_SENSRES_BITFRAMESDD_SDD00001 << NFCT_SENSRES_BITFRAMESDD_Pos, /**< SDD pattern 00001. */
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_00010 =
+ NFCT_SENSRES_BITFRAMESDD_SDD00010 << NFCT_SENSRES_BITFRAMESDD_Pos, /**< SDD pattern 00010. */
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_00100 =
+ NFCT_SENSRES_BITFRAMESDD_SDD00100 << NFCT_SENSRES_BITFRAMESDD_Pos, /**< SDD pattern 00100. */
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_01000 =
+ NFCT_SENSRES_BITFRAMESDD_SDD01000 << NFCT_SENSRES_BITFRAMESDD_Pos, /**< SDD pattern 01000. */
+ NRF_NFCT_SENSRES_BIT_FRAME_SDD_10000 =
+ NFCT_SENSRES_BITFRAMESDD_SDD10000 << NFCT_SENSRES_BITFRAMESDD_Pos /**< SDD pattern 10000. */
+} nrf_nfct_sensres_bit_frame_sdd_t;
+
+/**
+ * @brief 'Platofrm Config' NFC field configuration for the SENS_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ */
+typedef enum
+{
+ /**< SENS_RES 'Platform Config' field (b4-b1) value for Type 1 Tag platform. */
+ NRF_NFCT_SENSRES_PLATFORM_CONFIG_T1T = 6 << NFCT_SENSRES_PLATFCONFIG_Pos,
+ /**< SENS_RES 'Platform Config' field (b7-b6) value for any platform except Type 1 Tag platform. */
+ NRF_NFCT_SENSRES_PLATFORM_CONFIG_OTHER = 0 << NFCT_SENSRES_PLATFCONFIG_Pos
+} nrf_nfct_sensres_platform_config_t;
+
+/**
+ * @brief Bit masks for SEL_RES NFC frame configuration.
+ */
+typedef enum
+{
+ NRF_NFCT_SELRES_CASCADE_MASK = NFCT_SELRES_CASCADE_Msk, /**< SEL_RES Cascade field bit mask. */
+ NRF_NFCT_SELRES_PROTOCOL_MASK = NFCT_SELRES_PROTOCOL_Msk /**< SEL_RES Protocol field bit mask. */
+} nrf_nfct_selres_t;
+
+/**
+ * @brief Protocol NFC field (bits b7 and b6) configuration for the SEL_RES frame according to the NFC Forum Digital Protocol Technical Specification.
+ */
+typedef enum
+{
+ NRF_NFCT_SELRES_PROTOCOL_T2T = 0, /**< Type 2 Tag platform. */
+ NRF_NFCT_SELRES_PROTOCOL_T4AT = 1, /**< Type 4A Tag platform. */
+ NRF_NFCT_SELRES_PROTOCOL_NFCDEP = 2, /**< NFC-DEP Protocol. */
+ NRF_NFCT_SELRES_PROTOCOL_NFCDEP_T4AT = 3, /**< NFC-DEP Protocol and Type 4A Tag platform). */
+} nrf_nfct_selres_protocol_t;
+
+/**
+ * @brief Function for activating a specific NFCT task.
+ *
+ * @param[in] task Task.
+ */
+__STATIC_INLINE void nrf_nfct_task_trigger(nrf_nfct_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific NFCT task register.
+ *
+ * @param[in] task Task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_task_address_get(nrf_nfct_task_t task);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in] event Event.
+ */
+__STATIC_INLINE void nrf_nfct_event_clear(nrf_nfct_event_t event);
+
+/**
+ * @brief Function for returning the state of a specific event.
+ *
+ * @param[in] event Event.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_nfct_event_check(nrf_nfct_event_t event);
+
+/**
+ * @brief Function for returning the address of a specific NFCT event register.
+ *
+ * @param[in] event Event.
+ *
+ * @return Address.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_event_address_get(nrf_nfct_event_t event);
+
+/**
+ * @brief Function for enabling selected shortcuts.
+ *
+ * @param[in] short_mask Shortcut mask.
+ */
+__STATIC_INLINE void nrf_nfct_shorts_enable(uint32_t short_mask);
+
+/**
+ * @brief Function for disabling selected shortcuts.
+ *
+ * @param[in] short_mask Shortcut mask.
+ */
+__STATIC_INLINE void nrf_nfct_shorts_disable(uint32_t short_mask);
+
+/**
+ * @brief Function for retrieving the enabled shortcuts.
+ *
+ * @return Flags of the currently enabled shortcuts.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_shorts_get(void);
+
+/**
+ * @brief Function for setting shortcuts.
+ *
+ * @param[in] short_mask Shortcut mask.
+ */
+__STATIC_INLINE void nrf_nfct_shorts_set(uint32_t short_mask);
+
+/**
+ * @brief Function for enabling the selected interrupts.
+ *
+ * @param[in] int_mask Interrupt mask.
+ */
+__STATIC_INLINE void nrf_nfct_int_enable(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of the selected interrupts.
+ *
+ * @param[in] int_mask Interrupt mask.
+ *
+ * @retval true If any of the selected interrupts is enabled.
+ * @retval false If none of the selected interrupts is enabled.
+ */
+__STATIC_INLINE bool nrf_nfct_int_enable_check(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the information about enabled interrupts.
+ *
+ * @return The flags of the enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_int_enable_get(void);
+
+/**
+ * @brief Function for disabling the selected interrupts.
+ *
+ * @param[in] int_mask Interrupt mask.
+ */
+__STATIC_INLINE void nrf_nfct_int_disable(uint32_t int_mask);
+
+/**
+ * @brief Function for getting the NFCT error status.
+ *
+ * @return The NFCT error status flags, defined in @ref nrf_nfct_error_status_t.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_error_status_get(void);
+
+/**
+ * @brief Function for clearing the NFCT error status.
+ *
+ * @param[in] error_flag Error flags to be cleared, defined in @ref nrf_nfct_error_status_t.
+ */
+__STATIC_INLINE void nrf_nfct_error_status_clear(uint32_t error_flag);
+
+/**
+ * @brief Function for getting the NFC frame reception status.
+ *
+ * @return The flags of the NFC frame reception status, defined in @ref nrf_nfct_rx_frame_status_t.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_rx_frame_status_get(void);
+
+/**
+ * @brief Function for clearing the NFC frame reception status.
+ *
+ * @param[in] framestatus_flags Status flags to be cleared, defined in @ref nrf_nfct_rx_frame_status_t.
+ */
+__STATIC_INLINE void nrf_nfct_rx_frame_status_clear(uint32_t framestatus_flags);
+
+#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the NFC tag state.
+ *
+ * @retval NRF_NFCT_TAG_STATE_DISABLED NFC tag is disabled.
+ * @retval NRF_NFCT_TAG_STATE_RAMP_UP NFC tag is ramping up.
+ * @retval NRF_NFCT_TAG_STATE_IDLE NFC tag is activated and idle.
+ * @retval NRF_NFCT_TAG_STATE_RECEIVE NFC tag is receiving data.
+ * @retval NRF_NFCT_TAG_STATE_FRAME_DELAY Frame Delay Timer of the NFC tag is counting ticks
+ * since the last symbol of the last received frame.
+ * @retval NRF_NFCT_TAG_STATE_TRANSMIT NFC tag is transmitting data.
+ */
+__STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(void);
+#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the NFC tag sleep state during the automatic collision resolution.
+ *
+ * @details The returned value is the last state before the autimatic collision resolution started.
+ *
+ * @retval NRF_NFCT_SLEEP_STATE_IDLE NFC tag was in IDLE state before the automatic collision resolution started.
+ * @retval NRF_NFCT_SLEEP_STATE_SLEEP_A NFC tag was in SLEEP_A state before the automatic collision resolution started.
+ */
+__STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(void);
+#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for getting the status of the external NFC field detection.
+ *
+ * @return The NFC field detection status. Status bits can be checked by using @ref nrf_nfct_field_state_t.
+ */
+__STATIC_INLINE uint8_t nrf_nfct_field_status_get(void);
+
+/**
+ * @brief Function for getting the minimum Frame Delay Time value.
+ *
+ * @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
+ * the last symbol of the last received frame and the start of the transmission of a new TX frame.
+ *
+ *
+ * @return The minimum Frame Delay Time value in 13.56-MHz clock ticks.
+ */
+__STATIC_INLINE uint16_t nrf_nfct_frame_delay_min_get(void);
+
+/**
+ * @brief Function for setting the minimum Frame Delay Time value.
+ *
+ * @details This is the minimum value for Frame Delay Timer. It controls the shortest time between
+ * the last symbol of the last received frame and the start of the transmission of a new TX frame.
+ *
+ * @param[in] frame_delay_min Minimum Frame Delay Time value in 13.56-MHz clock ticks.
+ */
+__STATIC_INLINE void nrf_nfct_frame_delay_min_set(uint16_t frame_delay_min);
+
+/**
+ * @brief Function for getting the maximum Frame Delay Time value.
+ *
+ * @details This is the maximum value for Frame Delay Timer. It controls the longest time between
+ * the last symbol of the last received frame and the start of the transmission of a new TX frame.
+ * If no transmission starts before the Frame Delay Timer timeout,
+ * @ref NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK is set.
+ *
+ * @return The maximum Frame Delay Time value in 13.56-MHz clock ticks.
+ */
+__STATIC_INLINE uint32_t nrf_nfct_frame_delay_max_get(void);
+
+/**
+ * @brief Function for setting the maximum Frame Delay Time value.
+ *
+ * @details This is the maximum value for Frame Delay Timer. It controls the longest time between
+ * the last symbol of the last received frame and the start of the transmission of a new TX frame.
+ * If no transmission starts before the Frame Delay Timer timeout,
+ * @ref NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK is set.
+ *
+ * @param[in] frame_delay_max Maximum Frame Delay Time value in 13.56-MHz clock ticks.
+ */
+__STATIC_INLINE void nrf_nfct_frame_delay_max_set(uint32_t frame_delay_max);
+
+/**
+ * @brief Function for getting the Frame Delay Mode configuration.
+ *
+ * @return The configured Frame Delay Mode.
+ */
+__STATIC_INLINE nrf_nfct_frame_delay_mode_t nrf_nfct_frame_delay_mode_get(void);
+
+/**
+ * @brief Function for setting the NFC Frame Delay Mode configuration.
+ *
+ * @param[in] frame_delay_mode Frame Delay Mode configuration.
+ */
+__STATIC_INLINE void nrf_nfct_frame_delay_mode_set(nrf_nfct_frame_delay_mode_t frame_delay_mode);
+
+/**
+ * @brief Function for getting the pointer to the NFCT RX/TX buffer.
+ *
+ * @return The configured pointer to the receive or transmit buffer.
+ */
+__STATIC_INLINE uint8_t * nrf_nfct_rxtx_buffer_get(void);
+
+/**
+ * @brief Function for setting the the NFCT RX/TX buffer (address and maximum length).
+ *
+ * @note Buffer for the NFC RX/TX data is used by EasyDMA and must be located in RAM.
+ *
+ * @param[in] p_rxtx_buf Pointer to the receive or transmit buffer.
+ * @param[in] max_txrx_len Maximum receive or transmit length in bytes (size of the RAM buffer for EasyDMA).
+ */
+__STATIC_INLINE void nrf_nfct_rxtx_buffer_set(uint8_t * p_rxtx_buf,
+ uint16_t max_txrx_len);
+
+/**
+ * @brief Function for getting the NFCT RX/TX maximum buffer length.
+ *
+ * @return The configured maximum receive or transmit length in bytes (size of the RX/TX buffer for EasyDMA).
+ */
+__STATIC_INLINE uint16_t nrf_nfct_max_rxtx_length_get(void);
+
+/**
+ * @brief Function for getting the flags for NFC frame transmission configuration.
+ *
+ * @return The flags of the NFCT frame transmission configuration, defined in @ref nrf_nfct_tx_frame_config_t.
+ */
+__STATIC_INLINE uint8_t nrf_nfct_tx_frame_config_get(void);
+
+/**
+ * @brief Function for setting up the flags of the NFC frame transmission configuration.
+ *
+ * @param[in] flags Flags for NFCT TX configuration. Use @ref nrf_nfct_tx_frame_config_t for setting.
+ */
+__STATIC_INLINE void nrf_nfct_tx_frame_config_set(uint8_t flags);
+
+/**
+ * @brief Function for getting the length of the configured transmission frame.
+ *
+ * @note NFC frames do not have to consist of full bytes only, therefore data amount for transmission
+ * is configured in number of bits.
+ *
+ * @return Number of bits to be sent excluding CRC, parity, SoF, and EoF.
+ */
+__STATIC_INLINE uint16_t nrf_nfct_tx_bits_get(void);
+
+/**
+ * @brief Function for setting up the NFC frame transmission.
+ *
+ * @details Set the number of TX bits excluding CRC, parity, SoF, and EoF.
+ *
+ * @note Source of data for transmission is set by using @ref nrf_nfct_rxtx_buffer_set.
+ * @note NFC frames do not have to consist of full bytes only, therefore data amount for transmission
+ * is configured in number of bits.
+ *
+ * @param[in] tx_bits Overall number of bits to be sent.
+ */
+__STATIC_INLINE void nrf_nfct_tx_bits_set(uint16_t tx_bits);
+
+/**
+ * @brief Function for getting the flags of the NFC frame reception configuration.
+ *
+ * @return The flags for NFCT frame reception configuration, defined in @ref nrf_nfct_rx_frame_config_t.
+ */
+__STATIC_INLINE uint8_t nrf_nfct_rx_frame_config_get(void);
+
+/**
+ * @brief Function for setting up the NFC frame reception.
+ *
+ * @note Destination for the received data is set using @ref nrf_nfct_rxtx_buffer_set.
+ *
+ * @param[in] flags NFCT RX configuration flags. Use @ref nrf_nfct_rx_frame_config_t for setting
+ * the desired configuration.
+ */
+__STATIC_INLINE void nrf_nfct_rx_frame_config_set(uint8_t flags);
+
+/**
+ * @brief Function for getting the number of bits received from the NFC poller.
+ *
+ * @param[in] crc_excluded Flag for excluding CRC size from calculation.
+ *
+ * @return Number of received bits including or excluding CRC, and excluding parity and SoF/EoF framing.
+ */
+__STATIC_INLINE uint16_t nrf_nfct_rx_bits_get(bool crc_excluded);
+
+/**
+ * @brief Function for getting the NFCID1 (NFC tag identifier).
+ *
+ * @note This function always returns the full configuration of the NFCID1 setting (10 bytes), regardless
+ * of the NFCID1 size. The NFCID1 size can be configured using @ref nrf_nfct_sensres_nfcid1_size_set or
+ * @ref nrf_nfct_nfcid1_set.
+ *
+ * @param[out] p_nfcid1_buf Pointer to a buffer for the NDFCID1 parameter. The NFCID1 values are in
+ * little endian order, that is: |NFCID1_3RD_LAST|NFCID1_2ND_LAST|NFCID1_LAST|.
+ *
+ * @return Configured NFCID1 length
+ */
+__STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_get(uint8_t * p_nfcid1_buf);
+
+/**
+ * @brief Function for setting the NFCID1 (NFC tag identifier).
+ *
+ * @note This function also configures the NFCIDSIZE field in the SENSRES register of the NRF_NFCT peripheral.
+ *
+ * @param[in] p_nfcid1_buf Pointer to the buffer with NDFCID1 bytes.
+ * @param[in] nfcid1_size Size of the NFCID1 in bytes.
+ */
+__STATIC_INLINE void nrf_nfct_nfcid1_set(uint8_t const * p_nfcid1_buf,
+ nrf_nfct_sensres_nfcid1_size_t nfcid1_size);
+
+#if defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting the setting for the automatic collision resolution.
+ *
+ * @details The automatic collision resolution mechanism as defined in ISO 14443-3 and NFC Forum
+ * Digital Protocol Technical Specification 2.0, section 6.
+ *
+ * @retval true If automatic collision resolution is enabled.
+ * @retval false If automatic collision resolution is disabled.
+ */
+__STATIC_INLINE bool nrf_nfct_autocolres_is_enabled(void);
+
+/**
+ * @brief Function for enabling the automatic collision resolution.
+ *
+ * @details The automatic collision resolution mechanism as defined in ISO 14443-3 and NFC Forum
+ * Digital Protocol Technical Specification 2.0, section 6.
+ */
+__STATIC_INLINE void nrf_nfct_autocolres_enable(void);
+
+/**
+ * @brief Function for disabling the automatic collision resolution.
+ *
+ * @details The automatic collision resolution mechanism as defined in ISO 14443-3 and NFC Forum
+ * Digital Protocol Technical Specification 2.0, section 6.
+ */
+__STATIC_INLINE void nrf_nfct_autocolres_disable(void);
+#endif // defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for getting the NFCID1 size from the SENS_RES frame configuration.
+ *
+ * @details The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @return NFCID1 (tag identifier) size.
+ */
+__STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_sensres_nfcid1_size_get(void);
+
+/**
+ * @brief Function for setting the NFCID1 (tag identifier) size.field in the SENS_RES frame
+ * configuration.
+ *
+ * @note The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @param[in] nfcid1_size NFCID1 (tag identifier) size.
+ *
+ * @sa nrf_nfct_nfcid1_set()
+ */
+__STATIC_INLINE void nrf_nfct_sensres_nfcid1_size_set(nrf_nfct_sensres_nfcid1_size_t nfcid1_size);
+
+/**
+ * @brief Function for getting the Bit Frame SDD field from the SENS_RES frame configuration.
+ *
+ * @details The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @return The Bit Frame SDD field configuration.
+ */
+__STATIC_INLINE nrf_nfct_sensres_bit_frame_sdd_t nrf_nfct_sensres_bit_frame_sdd_get(void);
+
+/**
+ * @brief Function for setting the Bit Frame SDD field in the SENS_RES frame configuration.
+ *
+ * @note The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @param[in] bit_frame_sdd The Bit Frame SDD field configuration.
+ */
+__STATIC_INLINE void nrf_nfct_sensres_bit_frame_sdd_set(nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd);
+
+/**
+ * @brief Function for getting the Platform Config field from the SENS_RES frame configuration.
+ *
+ * @details The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @return The Platform Config field configuration.
+ */
+__STATIC_INLINE nrf_nfct_sensres_platform_config_t nrf_nfct_sensres_platform_config_get(void);
+
+/**
+ * @brief Function for setting the Platform Config field in the SENS_RES frame configuration.
+ *
+ * @note The SENS_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @param[in] platform_config The Platform Config field configuration.
+ */
+__STATIC_INLINE void nrf_nfct_sensres_platform_config_set(nrf_nfct_sensres_platform_config_t platform_config);
+
+/**
+ * @brief Function for checking the CASCADE bit of the SEL_RES frame.
+ *
+ * @details The CASCADE bit in the SEL_RES register is handled automatically by the NFCT hardware
+ * and indicates the status of the NFCID1 read operation to the NFC poller according to
+ * the NFC Forum Digital Protocol Speficiation 2.0, section 6.8.2.
+ *
+ * @retval true If NFCID1 read procedure is not complete.
+ * @retval false If NFCID1 read procedure is complete.
+ */
+__STATIC_INLINE bool nrf_nfct_selsres_cascade_check(void);
+
+/**
+ * @brief Function for getting the Protocol field in the SEL_RES frame.
+ *
+ * @details The SEL_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @return Value of the Protocol field in the SEL_RES frame.
+ */
+__STATIC_INLINE nrf_nfct_selres_protocol_t nrf_nfct_selsres_protocol_get(void);
+
+/**
+ * @brief Function for setting the Protocol field in the SEL_RES frame configuration.
+ *
+ * @details The SEL_RES frame is handled automatically by the NFCT hardware.
+ *
+ * @param[in] sel_res_protocol Value of the Protocol field in the SEL_RES frame.
+ */
+__STATIC_INLINE void nrf_nfct_selres_protocol_set(nrf_nfct_selres_protocol_t sel_res_protocol);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_nfct_task_trigger(nrf_nfct_task_t task)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_NFCT + (uint32_t)task)) = 1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_task_address_get(nrf_nfct_task_t task)
+{
+ return (uint32_t)((uint8_t *)NRF_NFCT + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_nfct_event_clear(nrf_nfct_event_t event)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_NFCT + (uint32_t)event)) = 0UL;
+ __DSB();
+}
+
+__STATIC_INLINE bool nrf_nfct_event_check(nrf_nfct_event_t event)
+{
+ return (bool)*(volatile const uint32_t *)((uint8_t *)NRF_NFCT + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_event_address_get(nrf_nfct_event_t event)
+{
+ return (uint32_t)((uint8_t *)NRF_NFCT + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_nfct_shorts_enable(uint32_t short_mask)
+{
+ NRF_NFCT->SHORTS |= short_mask;
+}
+
+__STATIC_INLINE void nrf_nfct_shorts_disable(uint32_t short_mask)
+{
+ NRF_NFCT->SHORTS &= ~short_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_shorts_get(void)
+{
+ return NRF_NFCT->SHORTS;
+}
+
+__STATIC_INLINE void nrf_nfct_shorts_set(uint32_t short_mask)
+{
+ NRF_NFCT->SHORTS = short_mask;
+}
+
+__STATIC_INLINE void nrf_nfct_int_enable(uint32_t int_mask)
+{
+ NRF_NFCT->INTENSET = int_mask;
+}
+
+__STATIC_INLINE bool nrf_nfct_int_enable_check(uint32_t int_mask)
+{
+ return (bool)(NRF_NFCT->INTENSET & int_mask);
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_int_enable_get(void)
+{
+ return NRF_NFCT->INTENSET;
+}
+
+__STATIC_INLINE void nrf_nfct_int_disable(uint32_t int_mask)
+{
+ NRF_NFCT->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_error_status_get(void)
+{
+ return NRF_NFCT->ERRORSTATUS;
+}
+
+__STATIC_INLINE void nrf_nfct_error_status_clear(uint32_t error_flags)
+{
+ NRF_NFCT->ERRORSTATUS = error_flags;
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_rx_frame_status_get(void)
+{
+ return NRF_NFCT->FRAMESTATUS.RX;
+}
+
+__STATIC_INLINE void nrf_nfct_rx_frame_status_clear(uint32_t framestatus_flags)
+{
+ NRF_NFCT->FRAMESTATUS.RX = framestatus_flags;
+}
+
+#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+__STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(void)
+{
+ return (nrf_nfct_tag_state_t)((NRF_NFCT->NFCTAGSTATE & NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) >>
+ NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos);
+}
+#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+__STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(void)
+{
+ return (nrf_nfct_sleep_state_t)((NRF_NFCT->SLEEPSTATE & NFCT_SLEEPSTATE_SLEEPSTATE_Msk) >>
+ NFCT_SLEEPSTATE_SLEEPSTATE_Pos);
+}
+#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__)
+
+__STATIC_INLINE uint8_t nrf_nfct_field_status_get(void)
+{
+ return (uint8_t)(NRF_NFCT->FIELDPRESENT);
+}
+
+__STATIC_INLINE uint16_t nrf_nfct_frame_delay_min_get(void)
+{
+ return (uint16_t)((NRF_NFCT->FRAMEDELAYMIN & NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk) >>
+ NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos);
+}
+
+__STATIC_INLINE void nrf_nfct_frame_delay_min_set(uint16_t frame_delay_min)
+{
+ NRF_NFCT->FRAMEDELAYMIN =
+ ((uint32_t)frame_delay_min << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) &
+ NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk;
+}
+
+__STATIC_INLINE uint32_t nrf_nfct_frame_delay_max_get(void)
+{
+ return (NRF_NFCT->FRAMEDELAYMAX & NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk) >>
+ NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos;
+}
+
+__STATIC_INLINE void nrf_nfct_frame_delay_max_set(uint32_t frame_delay_max)
+{
+ NRF_NFCT->FRAMEDELAYMAX =
+ ((uint32_t)frame_delay_max << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) &
+ NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk;
+}
+
+__STATIC_INLINE nrf_nfct_frame_delay_mode_t nrf_nfct_frame_delay_mode_get(void)
+{
+ return (nrf_nfct_frame_delay_mode_t)(NRF_NFCT->FRAMEDELAYMODE &
+ NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk);
+}
+
+__STATIC_INLINE void nrf_nfct_frame_delay_mode_set(nrf_nfct_frame_delay_mode_t frame_delay_mode)
+{
+ NRF_NFCT->FRAMEDELAYMODE = (uint32_t)frame_delay_mode;
+}
+
+__STATIC_INLINE uint8_t * nrf_nfct_rxtx_buffer_get(void)
+{
+ return (uint8_t *)(NRF_NFCT->PACKETPTR);
+}
+
+__STATIC_INLINE void nrf_nfct_rxtx_buffer_set(uint8_t * p_rxtx_buf,
+ uint16_t max_txrx_len)
+{
+ NRF_NFCT->PACKETPTR = (uint32_t)p_rxtx_buf;
+ NRF_NFCT->MAXLEN = ((uint32_t)max_txrx_len << NFCT_MAXLEN_MAXLEN_Pos) &
+ NFCT_MAXLEN_MAXLEN_Msk;
+}
+
+__STATIC_INLINE uint16_t nrf_nfct_max_rxtx_length_get(void)
+{
+ return (uint16_t)((NRF_NFCT->MAXLEN & NFCT_MAXLEN_MAXLEN_Msk) >> NFCT_MAXLEN_MAXLEN_Pos);
+}
+
+__STATIC_INLINE uint8_t nrf_nfct_tx_frame_config_get(void)
+{
+ return (uint8_t)(NRF_NFCT->TXD.FRAMECONFIG);
+}
+
+__STATIC_INLINE void nrf_nfct_tx_frame_config_set(uint8_t flags)
+{
+ NRF_NFCT->TXD.FRAMECONFIG = flags;
+}
+
+__STATIC_INLINE uint16_t nrf_nfct_tx_bits_get(void)
+{
+ return (uint16_t)(NRF_NFCT->TXD.AMOUNT & (NFCT_TXD_AMOUNT_TXDATABITS_Msk |
+ NFCT_TXD_AMOUNT_TXDATABYTES_Msk));
+}
+
+__STATIC_INLINE void nrf_nfct_tx_bits_set(uint16_t tx_bits)
+{
+ NRF_NFCT->TXD.AMOUNT = (tx_bits & (NFCT_TXD_AMOUNT_TXDATABITS_Msk | NFCT_TXD_AMOUNT_TXDATABYTES_Msk));
+}
+
+__STATIC_INLINE uint8_t nrf_nfct_rx_frame_config_get(void)
+{
+ return (uint8_t)(NRF_NFCT->RXD.FRAMECONFIG);
+}
+
+__STATIC_INLINE void nrf_nfct_rx_frame_config_set(uint8_t flags)
+{
+ NRF_NFCT->RXD.FRAMECONFIG = flags;
+}
+
+__STATIC_INLINE uint16_t nrf_nfct_rx_bits_get(bool crc_excluded)
+{
+ uint16_t rx_bits = NRF_NFCT->RXD.AMOUNT & (NFCT_RXD_AMOUNT_RXDATABITS_Msk |
+ NFCT_RXD_AMOUNT_RXDATABYTES_Msk);
+ return rx_bits - (crc_excluded ? (8u * NRF_NFCT_CRC_SIZE) : 0);
+}
+
+__STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_get(uint8_t * p_nfcid1_buf)
+{
+ uint32_t nfcid1_last = NRF_NFCT->NFCID1_LAST;
+ nrf_nfct_sensres_nfcid1_size_t size =
+ (nrf_nfct_sensres_nfcid1_size_t)(NRF_NFCT->SENSRES & NFCT_SENSRES_NFCIDSIZE_Msk);
+
+ if (size != NRF_NFCT_SENSRES_NFCID1_SIZE_SINGLE)
+ {
+ uint32_t nfcid1_2nd_last = NRF_NFCT->NFCID1_2ND_LAST;
+
+ if (size == NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE)
+ {
+ uint32_t nfcid1_3rd_last = NRF_NFCT->NFCID1_3RD_LAST;
+
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_3rd_last >> 16UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_3rd_last >> 8UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_3rd_last >> 0UL);
+ }
+
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_2nd_last >> 16UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_2nd_last >> 8UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_2nd_last >> 0UL);
+ }
+
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_last >> 24UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_last >> 16UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_last >> 8UL);
+ *p_nfcid1_buf++ = (uint8_t)(nfcid1_last >> 0UL);
+
+ return size;
+}
+
+__STATIC_INLINE void nrf_nfct_nfcid1_set(uint8_t const * p_nfcid1_buf,
+ nrf_nfct_sensres_nfcid1_size_t nfcid1_size)
+{
+ nrf_nfct_sensres_nfcid1_size_t size = (nfcid1_size == NRF_NFCT_SENSRES_NFCID1_SIZE_DEFAULT) ?
+ NRF_NFCT_SENSRES_NFCID1_SIZE_DOUBLE : nfcid1_size;
+
+ if (size != NRF_NFCT_SENSRES_NFCID1_SIZE_SINGLE)
+ {
+ if (size == NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE)
+ {
+ NRF_NFCT->NFCID1_3RD_LAST = ((uint32_t)p_nfcid1_buf[0] << 16UL) |
+ ((uint32_t)p_nfcid1_buf[1] << 8UL) |
+ ((uint32_t)p_nfcid1_buf[2] << 0UL);
+ p_nfcid1_buf += 3UL;
+ }
+ NRF_NFCT->NFCID1_2ND_LAST = ((uint32_t)p_nfcid1_buf[0] << 16UL) |
+ ((uint32_t)p_nfcid1_buf[1] << 8UL) |
+ ((uint32_t)p_nfcid1_buf[2] << 0UL);
+ p_nfcid1_buf += 3UL;
+ }
+
+ NRF_NFCT->NFCID1_LAST = ((uint32_t)p_nfcid1_buf[0] << 24UL) |
+ ((uint32_t)p_nfcid1_buf[1] << 16UL) |
+ ((uint32_t)p_nfcid1_buf[2] << 8UL) |
+ ((uint32_t)p_nfcid1_buf[3] << 0UL);
+
+ NRF_NFCT->SENSRES = ((NRF_NFCT->SENSRES & ~NFCT_SENSRES_NFCIDSIZE_Msk) |
+ (uint32_t)size);
+}
+
+#if defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__)
+__STATIC_INLINE bool nrf_nfct_autocolres_is_enabled(void)
+{
+ return (NRF_NFCT->AUTOCOLRESCONFIG & NFCT_AUTOCOLRESCONFIG_MODE_Msk) ==
+ (NFCT_AUTOCOLRESCONFIG_MODE_Enabled << NFCT_AUTOCOLRESCONFIG_MODE_Pos);
+}
+
+__STATIC_INLINE void nrf_nfct_autocolres_enable(void)
+{
+ NRF_NFCT->AUTOCOLRESCONFIG =
+ (NRF_NFCT->AUTOCOLRESCONFIG & ~NFCT_AUTOCOLRESCONFIG_MODE_Msk) |
+ (NFCT_AUTOCOLRESCONFIG_MODE_Enabled << NFCT_AUTOCOLRESCONFIG_MODE_Pos);
+}
+
+__STATIC_INLINE void nrf_nfct_autocolres_disable(void)
+{
+ NRF_NFCT->AUTOCOLRESCONFIG =
+ (NRF_NFCT->AUTOCOLRESCONFIG & ~NFCT_AUTOCOLRESCONFIG_MODE_Msk) |
+ (NFCT_AUTOCOLRESCONFIG_MODE_Disabled << NFCT_AUTOCOLRESCONFIG_MODE_Pos);
+}
+#endif // defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__)
+
+__STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_sensres_nfcid1_size_get(void)
+{
+ return (nrf_nfct_sensres_nfcid1_size_t)(NRF_NFCT->SENSRES & NFCT_SENSRES_NFCIDSIZE_Msk);
+}
+
+__STATIC_INLINE void nrf_nfct_sensres_nfcid1_size_set(nrf_nfct_sensres_nfcid1_size_t nfcid1_size)
+{
+ NRF_NFCT->SENSRES = ((NRF_NFCT->SENSRES & ~(NFCT_SENSRES_NFCIDSIZE_Msk)) | (uint32_t)nfcid1_size);
+}
+
+__STATIC_INLINE nrf_nfct_sensres_bit_frame_sdd_t nrf_nfct_sensres_bit_frame_sdd_get(void)
+{
+ return (nrf_nfct_sensres_bit_frame_sdd_t)(NRF_NFCT->SENSRES & NFCT_SENSRES_BITFRAMESDD_Msk);
+}
+
+__STATIC_INLINE void nrf_nfct_sensres_bit_frame_sdd_set(nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd)
+{
+ NRF_NFCT->SENSRES = ((NRF_NFCT->SENSRES & ~(NFCT_SENSRES_BITFRAMESDD_Msk)) | (uint32_t)bit_frame_sdd);
+}
+
+__STATIC_INLINE nrf_nfct_sensres_platform_config_t nrf_nfct_sensres_platform_config_get(void)
+{
+ return (nrf_nfct_sensres_platform_config_t)(NRF_NFCT->SENSRES & NFCT_SENSRES_PLATFCONFIG_Msk);
+}
+
+__STATIC_INLINE void nrf_nfct_sensres_platform_config_set(nrf_nfct_sensres_platform_config_t platform_config)
+{
+ NRF_NFCT->SENSRES = ((NRF_NFCT->SENSRES & ~(NFCT_SENSRES_PLATFCONFIG_Msk)) | (uint32_t)platform_config);
+}
+
+__STATIC_INLINE bool nrf_nfct_selsres_cascade_check(void)
+{
+ return (bool)(NRF_NFCT->SELRES & NFCT_SELRES_CASCADE_Msk);
+}
+
+__STATIC_INLINE nrf_nfct_selres_protocol_t nrf_nfct_selsres_protocol_get(void)
+{
+ return (nrf_nfct_selres_protocol_t)((NRF_NFCT->SELRES & NFCT_SELRES_PROTOCOL_Msk) >>
+ NFCT_SELRES_PROTOCOL_Pos);
+}
+
+__STATIC_INLINE void nrf_nfct_selres_protocol_set(nrf_nfct_selres_protocol_t sel_res_protocol)
+{
+ NRF_NFCT->SELRES = (NRF_NFCT->SELRES & ~NFCT_SELRES_PROTOCOL_Msk) |
+ ((uint32_t)sel_res_protocol << NFCT_SELRES_PROTOCOL_Pos);
+}
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_NFCT_H__ */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.c b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.c
index 6bb66db6cb..be4bde459b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.c
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
index afc928acc8..556672a2d6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nvmc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
index 39344f9e08..f9a37b9dbf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
index 7628f8d424..b44e6819d7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -38,10 +38,6 @@
extern "C" {
#endif
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
/**
* @defgroup nrf_power_hal POWER HAL
* @{
@@ -955,46 +951,34 @@ __STATIC_INLINE uint8_t nrf_power_gpregret2_get(void)
__STATIC_INLINE void nrf_power_dcdcen_set(bool enable)
{
-#if NRF_POWER_HAS_VDDH
- NRF_POWER->DCDCEN = (enable ?
- POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
- POWER_DCDCEN_DCDCEN_Pos;
-#else
NRF_POWER->DCDCEN = (enable ?
POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
POWER_DCDCEN_DCDCEN_Pos;
-#endif
}
__STATIC_INLINE bool nrf_power_dcdcen_get(void)
{
-#if NRF_POWER_HAS_VDDH
return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
==
(POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
-#else
- return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
- ==
- (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
-#endif
}
#if NRF_POWER_HAS_RAMPOWER_REGS
__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask)
{
- NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+ NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
NRF_POWER->RAM[block].POWERSET = section_mask;
}
__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask)
{
- NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+ NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
NRF_POWER->RAM[block].POWERCLR = section_mask;
}
__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block)
{
- NRFX_ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+ NRFX_ASSERT(block < NRFX_ARRAY_SIZE(NRF_POWER->RAM));
return NRF_POWER->RAM[block].POWER;
}
#endif /* NRF_POWER_HAS_RAMPOWER_REGS */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
index 96d9f06126..40f9124366 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -187,6 +187,13 @@ __STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_chan
*/
__STATIC_INLINE void nrf_ppi_channel_disable_all(void);
+/**
+ * @brief Function for enabling multiple PPI channels.
+ *
+ * @param[in] mask Channel mask.
+ */
+__STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask);
+
/**
* @brief Function for disabling multiple PPI channels.
*
@@ -207,6 +214,25 @@ __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t eep,
uint32_t tep);
+/**
+ * @brief Function for setting up the event endpoint for a given PPI channel.
+ *
+ * @param[in] eep Event register address.
+ * @param[in] channel Channel to which the given endpoint is assigned.
+ */
+__STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
+ uint32_t eep);
+
+/**
+ * @brief Function for setting up the task endpoint for a given PPI channel.
+ *
+ * @param[in] tep Task register address.
+ * @param[in] channel Channel to which the given endpoint is assigned.
+ */
+__STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
+ uint32_t tep);
+
+
#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting up task endpoint for a given PPI fork.
@@ -367,6 +393,11 @@ __STATIC_INLINE void nrf_ppi_channel_disable_all(void)
NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
}
+__STATIC_INLINE void nrf_ppi_channels_enable(uint32_t mask)
+{
+ NRF_PPI->CHENSET = mask;
+}
+
__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
{
NRF_PPI->CHENCLR = mask;
@@ -380,6 +411,18 @@ __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
NRF_PPI->CH[(uint32_t) channel].TEP = tep;
}
+__STATIC_INLINE void nrf_ppi_event_endpoint_setup(nrf_ppi_channel_t channel,
+ uint32_t eep)
+{
+ NRF_PPI->CH[(uint32_t) channel].EEP = eep;
+}
+
+__STATIC_INLINE void nrf_ppi_task_endpoint_setup(nrf_ppi_channel_t channel,
+ uint32_t tep)
+{
+ NRF_PPI->CH[(uint32_t) channel].TEP = tep;
+}
+
#if defined(PPI_FEATURE_FORKS_PRESENT)
__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
index 88d87ea6e0..74d274426a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
index de81380628..e87c65d237 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -44,6 +44,13 @@ extern "C" {
* @brief Hardware access layer for managing the Quadrature Decoder (QDEC) peripheral.
*/
+/**
+ * @brief This value can be provided as a parameter for the @ref nrf_qdec_pio_assign
+ * function call to specify that a LED signal shall not be use by the QDEC and
+ * connected to a physical pin.
+ */
+#define NRF_QDEC_LED_NOT_CONNECTED 0xFFFFFFFF
+
/**
* @enum nrf_qdec_task_t
* @brief QDEC tasks.
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
index d0767d7252..57b2c0c452 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
new file mode 100644
index 0000000000..4861d047bc
--- /dev/null
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
@@ -0,0 +1,1422 @@
+/*
+ * Copyright (c) 2018, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRF_RADIO_H__
+#define NRF_RADIO_H__
+
+#include <nrfx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_radio_hal RADIO HAL
+ * @{
+ * @ingroup nrf_radio
+ * @brief Hardware access layer for managing the RADIO peripheral.
+ */
+
+/**
+ * @brief RADIO tasks.
+ */
+typedef enum
+{
+ /*lint -save -e30*/
+ NRF_RADIO_TASK_TXEN = offsetof(NRF_RADIO_Type, TASKS_TXEN), /**< Enable RADIO in TX mode. */
+ NRF_RADIO_TASK_RXEN = offsetof(NRF_RADIO_Type, TASKS_RXEN), /**< Enable RADIO in RX mode. */
+ NRF_RADIO_TASK_START = offsetof(NRF_RADIO_Type, TASKS_START), /**< Start RADIO. */
+ NRF_RADIO_TASK_STOP = offsetof(NRF_RADIO_Type, TASKS_STOP), /**< Stop RADIO. */
+ NRF_RADIO_TASK_DISABLE = offsetof(NRF_RADIO_Type, TASKS_DISABLE), /**< Disable RADIO. */
+ NRF_RADIO_TASK_RSSISTART = offsetof(NRF_RADIO_Type, TASKS_RSSISTART), /**< Start the RSSI and take one single sample of the receive signal strength. */
+ NRF_RADIO_TASK_RSSISTOP = offsetof(NRF_RADIO_Type, TASKS_RSSISTOP), /**< Stop the RSSI measurement. */
+ NRF_RADIO_TASK_BCSTART = offsetof(NRF_RADIO_Type, TASKS_BCSTART), /**< Start the bit counter. */
+ NRF_RADIO_TASK_BCSTOP = offsetof(NRF_RADIO_Type, TASKS_BCSTOP), /**< Stop the bit counter. */
+#if defined(RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TASK_EDSTART = offsetof(NRF_RADIO_Type, TASKS_EDSTART), /**< Start the Energy Detect measurement used in IEEE 802.15.4 mode. */
+#endif
+#if defined(RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TASK_EDSTOP = offsetof(NRF_RADIO_Type, TASKS_EDSTOP), /**< Stop the Energy Detect measurement. */
+#endif
+#if defined(RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TASK_CCASTART = offsetof(NRF_RADIO_Type, TASKS_CCASTART), /**< Start the Clear Channel Assessment used in IEEE 802.15.4 mode. */
+#endif
+#if defined(RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TASK_CCASTOP = offsetof(NRF_RADIO_Type, TASKS_CCASTOP), /**< Stop the Clear Channel Assessment. */
+#endif
+ /*lint -restore*/
+} nrf_radio_task_t;
+
+/**
+ * @brief RADIO events.
+ */
+typedef enum
+{
+ /*lint -save -e30*/
+ NRF_RADIO_EVENT_READY = offsetof(NRF_RADIO_Type, EVENTS_READY), /**< Radio has ramped up and is ready to be started. */
+ NRF_RADIO_EVENT_ADDRESS = offsetof(NRF_RADIO_Type, EVENTS_ADDRESS), /**< Address sent or received. */
+ NRF_RADIO_EVENT_PAYLOAD = offsetof(NRF_RADIO_Type, EVENTS_PAYLOAD), /**< Packet payload sent or received. */
+ NRF_RADIO_EVENT_END = offsetof(NRF_RADIO_Type, EVENTS_END), /**< Packet transmitted or received. */
+ NRF_RADIO_EVENT_DISABLED = offsetof(NRF_RADIO_Type, EVENTS_DISABLED), /**< RADIO has been disabled. */
+ NRF_RADIO_EVENT_DEVMATCH = offsetof(NRF_RADIO_Type, EVENTS_DEVMATCH), /**< A device address match occurred on the last received packet. */
+ NRF_RADIO_EVENT_DEVMISS = offsetof(NRF_RADIO_Type, EVENTS_DEVMISS), /**< No device address match occurred on the last received packet. */
+ NRF_RADIO_EVENT_RSSIEND = offsetof(NRF_RADIO_Type, EVENTS_RSSIEND), /**< Sampling of receive signal strength complete. */
+ NRF_RADIO_EVENT_BCMATCH = offsetof(NRF_RADIO_Type, EVENTS_BCMATCH), /**< Bit counter reached bit count value. */
+#if defined(RADIO_INTENSET_CRCOK_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_CRCOK = offsetof(NRF_RADIO_Type, EVENTS_CRCOK), /**< Packet received with correct CRC. */
+#endif
+#if defined(RADIO_INTENSET_CRCERROR_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_CRCERROR = offsetof(NRF_RADIO_Type, EVENTS_CRCERROR), /**< Packet received with incorrect CRC. */
+#endif
+#if defined(RADIO_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_FRAMESTART = offsetof(NRF_RADIO_Type, EVENTS_FRAMESTART), /**< IEEE 802.15.4 length field received. */
+#endif
+#if defined(RADIO_INTENSET_EDEND_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_EDEND = offsetof(NRF_RADIO_Type, EVENTS_EDEND), /**< Energy Detection procedure ended. */
+#endif
+#if defined(RADIO_INTENSET_EDSTOPPED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_EDSTOPPED = offsetof(NRF_RADIO_Type, EVENTS_EDSTOPPED), /**< The sampling of Energy Detection has stopped. */
+#endif
+#if defined(RADIO_INTENSET_CCAIDLE_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_CCAIDLE = offsetof(NRF_RADIO_Type, EVENTS_CCAIDLE), /**< Wireless medium in idle - clear to send. */
+#endif
+#if defined(RADIO_INTENSET_CCABUSY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_CCABUSY = offsetof(NRF_RADIO_Type, EVENTS_CCABUSY), /**< Wireless medium busy - do not send. */
+#endif
+#if defined(RADIO_INTENSET_CCASTOPPED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_CCASTOPPED = offsetof(NRF_RADIO_Type, EVENTS_CCASTOPPED), /**< The CCA has stopped. */
+#endif
+#if defined(RADIO_INTENSET_RATEBOOST_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_RATEBOOST = offsetof(NRF_RADIO_Type, EVENTS_RATEBOOST), /**< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */
+#endif
+#if defined(RADIO_INTENSET_TXREADY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_TXREADY = offsetof(NRF_RADIO_Type, EVENTS_TXREADY), /**< RADIO has ramped up and is ready to be started TX path. */
+#endif
+#if defined(RADIO_INTENSET_RXREADY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_RXREADY = offsetof(NRF_RADIO_Type, EVENTS_RXREADY), /**< RADIO has ramped up and is ready to be started RX path. */
+#endif
+#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_MHRMATCH = offsetof(NRF_RADIO_Type, EVENTS_MHRMATCH), /**< MAC Header match found. */
+#endif
+#if defined(RADIO_INTENSET_PHYEND_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_EVENT_PHYEND = offsetof(NRF_RADIO_Type, EVENTS_PHYEND), /**< Generated in Ble_LR125Kbit, Ble_LR500Kbit
+ and BleIeee802154_250Kbit modes when last
+ bit is sent on the air. */
+#endif
+ /*lint -restore*/
+} nrf_radio_event_t;
+
+/**
+ * @brief RADIO interrupts.
+ */
+typedef enum
+{
+ NRF_RADIO_INT_READY_MASK = RADIO_INTENSET_READY_Msk, /**< Interrupt on READY event. */
+ NRF_RADIO_INT_ADDRESS_MASK = RADIO_INTENSET_ADDRESS_Msk, /**< Interrupt on ADDRESS event. */
+ NRF_RADIO_INT_PAYLOAD_MASK = RADIO_INTENSET_PAYLOAD_Msk, /**< Interrupt on PAYLOAD event. */
+ NRF_RADIO_INT_END_MASK = RADIO_INTENSET_END_Msk, /**< Interrupt on END event. */
+ NRF_RADIO_INT_DISABLED_MASK = RADIO_INTENSET_DISABLED_Msk, /**< Interrupt on DISABLED event. */
+ NRF_RADIO_INT_DEVMATCH_MASK = RADIO_INTENSET_DEVMATCH_Msk, /**< Interrupt on DEVMATCH event. */
+ NRF_RADIO_INT_DEVMISS_MASK = RADIO_INTENSET_DEVMISS_Msk, /**< Interrupt on DEVMISS event. */
+ NRF_RADIO_INT_RSSIEND_MASK = RADIO_INTENSET_RSSIEND_Msk, /**< Interrupt on RSSIEND event. */
+ NRF_RADIO_INT_BCMATCH_MASK = RADIO_INTENSET_BCMATCH_Msk, /**< Interrupt on BCMATCH event. */
+#if defined(RADIO_INTENSET_CRCOK_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_CRCOK_MASK = RADIO_INTENSET_CRCOK_Msk, /**< Interrupt on CRCOK event. */
+#endif
+#if defined(RADIO_INTENSET_CRCERROR_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_CRCERROR_MASK = RADIO_INTENSET_CRCERROR_Msk, /**< Interrupt on CRCERROR event. */
+#endif
+#if defined(RADIO_INTENSET_FRAMESTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_FRAMESTART_MASK = RADIO_INTENSET_FRAMESTART_Msk, /**< Interrupt on FRAMESTART event. */
+#endif
+#if defined(RADIO_INTENSET_EDEND_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_EDEND_MASK = RADIO_INTENSET_EDEND_Msk, /**< Interrupt on EDEND event. */
+#endif
+#if defined(RADIO_INTENSET_EDSTOPPED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_EDSTOPPED_MASK = RADIO_INTENSET_EDSTOPPED_Msk, /**< Interrupt on EDSTOPPED event. */
+#endif
+#if defined(RADIO_INTENSET_CCAIDLE_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_CCAIDLE_MASK = RADIO_INTENSET_CCAIDLE_Msk, /**< Interrupt on CCAIDLE event. */
+#endif
+#if defined(RADIO_INTENSET_CCABUSY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_CCABUSY_MASK = RADIO_INTENSET_CCABUSY_Msk, /**< Interrupt on CCABUSY event. */
+#endif
+#if defined(RADIO_INTENSET_CCASTOPPED_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_CCASTOPPED_MASK = RADIO_INTENSET_CCASTOPPED_Msk, /**< Interrupt on CCASTOPPED event. */
+#endif
+#if defined(RADIO_INTENSET_RATEBOOST_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_RATEBOOST_MASK = RADIO_INTENSET_RATEBOOST_Msk, /**< Interrupt on RATEBOOST event. */
+#endif
+#if defined(RADIO_INTENSET_TXREADY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_TXREADY_MASK = RADIO_INTENSET_TXREADY_Msk, /**< Interrupt on TXREADY event. */
+#endif
+#if defined(RADIO_INTENSET_RXREADY_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_RXREADY_MASK = RADIO_INTENSET_RXREADY_Msk, /**< Interrupt on RXREADY event. */
+#endif
+#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_MHRMATCH_MASK = RADIO_INTENSET_MHRMATCH_Msk, /**< Interrupt on MHRMATCH event. */
+#endif
+#if defined(RADIO_INTENSET_PHYEND_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_INT_PHYEND_MASK = RADIO_INTENSET_PHYEND_Msk, /**< Interrupt on PHYEND event. */
+#endif
+} nrf_radio_int_mask_t;
+
+/**
+ * @brief RADIO shortcuts.
+ */
+typedef enum
+{
+ NRF_RADIO_SHORT_READY_START_MASK = RADIO_SHORTS_READY_START_Msk, /**< Shortcut between READY event and START task. */
+ NRF_RADIO_SHORT_END_DISABLE_MASK = RADIO_SHORTS_END_DISABLE_Msk, /**< Shortcut between END event and DISABLE task. */
+ NRF_RADIO_SHORT_DISABLED_TXEN_MASK = RADIO_SHORTS_DISABLED_TXEN_Msk, /**< Shortcut between DISABLED event and TXEN task. */
+ NRF_RADIO_SHORT_DISABLED_RXEN_MASK = RADIO_SHORTS_DISABLED_RXEN_Msk, /**< Shortcut between DISABLED event and RXEN task. */
+ NRF_RADIO_SHORT_ADDRESS_RSSISTART_MASK = RADIO_SHORTS_ADDRESS_RSSISTART_Msk, /**< Shortcut between ADDRESS event and RSSISTART task. */
+ NRF_RADIO_SHORT_END_START_MASK = RADIO_SHORTS_END_START_Msk, /**< Shortcut between END event and START task. */
+ NRF_RADIO_SHORT_ADDRESS_BCSTART_MASK = RADIO_SHORTS_ADDRESS_BCSTART_Msk, /**< Shortcut between ADDRESS event and BCSTART task. */
+ NRF_RADIO_SHORT_DISABLED_RSSISTOP_MASK = RADIO_SHORTS_DISABLED_RSSISTOP_Msk, /**< Shortcut between DISABLED event and RSSISTOP task. */
+#if defined(RADIO_SHORTS_RXREADY_CCASTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_RXREADY_CCASTART_MASK = RADIO_SHORTS_RXREADY_CCASTART_Msk, /**< Shortcut between RXREADY event and CCASTART task. */
+#endif
+#if defined(RADIO_SHORTS_CCAIDLE_TXEN_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_CCAIDLE_TXEN_MASK = RADIO_SHORTS_CCAIDLE_TXEN_Msk, /**< Shortcut between CCAIDLE event and TXEN task. */
+#endif
+#if defined(RADIO_SHORTS_CCABUSY_DISABLE_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_CCABUSY_DISABLE_MASK = RADIO_SHORTS_CCABUSY_DISABLE_Msk, /**< Shortcut between CCABUSY event and DISABLE task. */
+#endif
+#if defined(RADIO_SHORTS_FRAMESTART_BCSTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_FRAMESTART_BCSTART_MASK = RADIO_SHORTS_FRAMESTART_BCSTART_Msk, /**< Shortcut between FRAMESTART event and BCSTART task. */
+#endif
+#if defined(RADIO_SHORTS_READY_EDSTART_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_READY_EDSTART_MASK = RADIO_SHORTS_READY_EDSTART_Msk, /**< Shortcut between READY event and EDSTART task. */
+#endif
+#if defined(RADIO_SHORTS_EDEND_DISABLE_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_EDEND_DISABLE_MASK = RADIO_SHORTS_EDEND_DISABLE_Msk, /**< Shortcut between EDEND event and DISABLE task. */
+#endif
+#if defined(RADIO_SHORTS_CCAIDLE_STOP_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_CCAIDLE_STOP_MASK = RADIO_SHORTS_CCAIDLE_STOP_Msk, /**< Shortcut between CCAIDLE event and STOP task. */
+#endif
+#if defined(RADIO_SHORTS_TXREADY_START_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_TXREADY_START_MASK = RADIO_SHORTS_TXREADY_START_Msk, /**< Shortcut between TXREADY event and START task. */
+#endif
+#if defined(RADIO_SHORTS_RXREADY_START_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_RXREADY_START_MASK = RADIO_SHORTS_RXREADY_START_Msk, /**< Shortcut between RXREADY event and START task. */
+#endif
+#if defined(RADIO_SHORTS_PHYEND_DISABLE_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_PHYEND_DISABLE_MASK = RADIO_SHORTS_PHYEND_DISABLE_Msk, /**< Shortcut between PHYEND event and DISABLE task. */
+#endif
+#if defined(RADIO_SHORTS_PHYEND_START_Msk) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_SHORT_PHYEND_START_MASK = RADIO_SHORTS_PHYEND_START_Msk, /**< Shortcut between PHYEND event and START task. */
+#endif
+} nrf_radio_short_mask_t;
+
+#if defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief RADIO Clear Channel Assessment modes.
+ */
+typedef enum
+{
+ NRF_RADIO_CCA_MODE_ED = RADIO_CCACTRL_CCAMODE_EdMode, /**< Energy Above Threshold. Will report busy whenever energy is detected above set threshold. */
+ NRF_RADIO_CCA_MODE_CARRIER = RADIO_CCACTRL_CCAMODE_CarrierMode, /**< Carrier Seen. Will report busy whenever compliant IEEE 802.15.4 signal is seen. */
+ NRF_RADIO_CCA_MODE_CARRIER_AND_ED = RADIO_CCACTRL_CCAMODE_CarrierAndEdMode, /**< Energy Above Threshold AND Carrier Seen. */
+ NRF_RADIO_CCA_MODE_CARRIER_OR_ED = RADIO_CCACTRL_CCAMODE_CarrierOrEdMode, /**< Energy Above Threshold OR Carrier Seen. */
+ NRF_RADIO_CCA_MODE_ED_TEST1 = RADIO_CCACTRL_CCAMODE_EdModeTest1, /**< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
+} nrf_radio_cca_mode_t;
+#endif // defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Types of RADIO States.
+ */
+typedef enum
+{
+ NRF_RADIO_STATE_DISABLED = RADIO_STATE_STATE_Disabled, /**< No operations are going on inside the radio and the power consumption is at a minimum. */
+ NRF_RADIO_STATE_RXRU = RADIO_STATE_STATE_RxRu, /**< The radio is ramping up and preparing for reception. */
+ NRF_RADIO_STATE_RXIDLE = RADIO_STATE_STATE_RxIdle, /**< The radio is ready for reception to start. */
+ NRF_RADIO_STATE_RX = RADIO_STATE_STATE_Rx, /**< Reception has been started. */
+ NRF_RADIO_STATE_RXDISABLE = RADIO_STATE_STATE_RxDisable, /**< The radio is disabling the receiver. */
+ NRF_RADIO_STATE_TXRU = RADIO_STATE_STATE_TxRu, /**< The radio is ramping up and preparing for transmission. */
+ NRF_RADIO_STATE_TXIDLE = RADIO_STATE_STATE_TxIdle, /**< The radio is ready for transmission to start. */
+ NRF_RADIO_STATE_TX = RADIO_STATE_STATE_Tx, /**< The radio is transmitting a packet. */
+ NRF_RADIO_STATE_TXDISABLE = RADIO_STATE_STATE_TxDisable, /**< The radio is disabling the transmitter. */
+} nrf_radio_state_t;
+
+/**
+ * @brief Types of RADIO TX power.
+ */
+typedef enum
+{
+#if defined(RADIO_TXPOWER_TXPOWER_Pos8dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS8DBM = RADIO_TXPOWER_TXPOWER_Pos8dBm, /**< 8 dBm. */
+#endif
+#if defined(RADIO_TXPOWER_TXPOWER_Pos7dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS7DBM = RADIO_TXPOWER_TXPOWER_Pos7dBm, /**< 7 dBm. */
+#endif
+#if defined(RADIO_TXPOWER_TXPOWER_Pos6dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS6DBM = RADIO_TXPOWER_TXPOWER_Pos6dBm, /**< 6 dBm. */
+#endif
+#if defined(RADIO_TXPOWER_TXPOWER_Pos5dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS5DBM = RADIO_TXPOWER_TXPOWER_Pos5dBm, /**< 5 dBm. */
+#endif
+ NRF_RADIO_TXPOWER_POS4DBM = RADIO_TXPOWER_TXPOWER_Pos4dBm, /**< 4 dBm. */
+#if defined(RADIO_TXPOWER_TXPOWER_Pos3dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS3DBM = RADIO_TXPOWER_TXPOWER_Pos3dBm, /**< 3 dBm. */
+#endif
+#if defined(RADIO_TXPOWER_TXPOWER_Pos2dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_POS2DBM = RADIO_TXPOWER_TXPOWER_Pos2dBm, /**< 2 dBm. */
+#endif
+ NRF_RADIO_TXPOWER_0DBM = RADIO_TXPOWER_TXPOWER_0dBm, /**< 0 dBm. */
+ NRF_RADIO_TXPOWER_NEG4DBM = RADIO_TXPOWER_TXPOWER_Neg4dBm, /**< -4 dBm. */
+ NRF_RADIO_TXPOWER_NEG8DBM = RADIO_TXPOWER_TXPOWER_Neg8dBm, /**< -8 dBm. */
+ NRF_RADIO_TXPOWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm, /**< -12 dBm. */
+ NRF_RADIO_TXPOWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm, /**< -16 dBm. */
+ NRF_RADIO_TXPOWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm, /**< -20 dBm. */
+ NRF_RADIO_TXPOWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm, /**< -30 dBm. */
+#if defined(RADIO_TXPOWER_TXPOWER_Neg40dBm) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_TXPOWER_NEG40DBM = RADIO_TXPOWER_TXPOWER_Neg40dBm, /**< -40 dBm. */
+#endif
+} nrf_radio_txpower_t;
+
+/**
+ * @brief Types of RADIO modes (data rate and modulation).
+ */
+typedef enum
+{
+ NRF_RADIO_MODE_NRF_1MBIT = RADIO_MODE_MODE_Nrf_1Mbit, /**< 1Mbit/s Nordic proprietary radio mode. */
+ NRF_RADIO_MODE_NRF_2MBIT = RADIO_MODE_MODE_Nrf_2Mbit, /**< 2Mbit/s Nordic proprietary radio mode. */
+#if defined(RADIO_MODE_MODE_Nrf_250Kbit) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_MODE_NRF_250KBIT = RADIO_MODE_MODE_Nrf_250Kbit, /**< 250Kbit/s Nordic proprietary radio mode. */
+#endif
+ NRF_RADIO_MODE_BLE_1MBIT = RADIO_MODE_MODE_Ble_1Mbit, /**< 1 Mbit/s Bluetooth Low Energy. */
+#if defined(RADIO_MODE_MODE_Ble_2Mbit) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_MODE_BLE_2MBIT = RADIO_MODE_MODE_Ble_2Mbit, /**< 2 Mbit/s Bluetooth Low Energy. */
+#endif
+#if defined(RADIO_MODE_MODE_Ble_LR125Kbit) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_MODE_BLE_LR125KBIT = RADIO_MODE_MODE_Ble_LR125Kbit, /*!< Bluetooth Low Energy Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
+#endif
+#if defined(RADIO_MODE_MODE_Ble_LR500Kbit) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_MODE_BLE_LR500KBIT = RADIO_MODE_MODE_Ble_LR500Kbit, /*!< Bluetooth Low Energy Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */
+#endif
+#if defined(RADIO_MODE_MODE_Ieee802154_250Kbit) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_MODE_IEEE802154_250KBIT = RADIO_MODE_MODE_Ieee802154_250Kbit, /**< IEEE 802.15.4-2006 250 kbit/s. */
+#endif
+} nrf_radio_mode_t;
+
+#if defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Types of preamble length.
+ */
+typedef enum
+{
+ NRF_RADIO_PREAMBLE_LENGTH_8BIT = RADIO_PCNF0_PLEN_8bit, /**< 8-bit preamble. */
+ NRF_RADIO_PREAMBLE_LENGTH_16BIT = RADIO_PCNF0_PLEN_16bit, /**< 16-bit preamble. */
+#if defined(RADIO_PCNF0_PLEN_32bitZero) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_PREAMBLE_LENGTH_32BIT_ZERO = RADIO_PCNF0_PLEN_32bitZero, /**< 32-bit zero preamble used for IEEE 802.15.4. */
+#endif
+#if defined(RADIO_PCNF0_PLEN_LongRange) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_PREAMBLE_LENGTH_LONG_RANGE = RADIO_PCNF0_PLEN_LongRange, /**< Preamble - used for BTLE Long Range. */
+#endif
+} nrf_radio_preamble_length_t;
+#endif // defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Types of CRC calculatons regarding address.
+ */
+typedef enum
+{
+ NRF_RADIO_CRC_ADDR_INCLUDE = RADIO_CRCCNF_SKIPADDR_Include, /**< CRC calculation includes address field. */
+ NRF_RADIO_CRC_ADDR_SKIP = RADIO_CRCCNF_SKIPADDR_Skip, /**< CRC calculation does not include address field. */
+#if defined(RADIO_CRCCNF_SKIPADDR_Ieee802154) || defined(__NRFX_DOXYGEN__)
+ NRF_RADIO_CRC_ADDR_IEEE802154 = RADIO_CRCCNF_SKIPADDR_Ieee802154, /**< CRC calculation as per 802.15.4 standard. */
+#endif
+} nrf_radio_crc_addr_t;
+
+/**
+ * @brief Packet configuration.
+ */
+typedef struct
+{
+ uint8_t lflen; /**< Length on air of LENGTH field in number of bits. */
+ uint8_t s0len; /**< Length on air of S0 field in number of bytes. */
+ uint8_t s1len; /**< Length on air of S1 field in number of bits. */
+#if defined(RADIO_PCNF0_S1INCL_Msk) || defined(__NRFX_DOXYGEN__)
+ bool s1incl; /**< Include or exclude S1 field in RAM. */
+#endif
+#if defined(RADIO_PCNF0_CILEN_Msk) || defined(__NRFX_DOXYGEN__)
+ uint8_t cilen; /**< Length of code indicator - long range. */
+#endif
+#if defined(RADIO_PCNF0_PLEN_Msk) || defined(__NRFX_DOXYGEN__)
+ nrf_radio_preamble_length_t plen; /**< Length of preamble on air. Decision point: TASKS_START task. */
+#endif
+#if defined(RADIO_PCNF0_CRCINC_Msk) || defined(__NRFX_DOXYGEN__)
+ bool crcinc; /**< Indicates if LENGTH field contains CRC or not. */
+#endif
+#if defined(RADIO_PCNF0_TERMLEN_Msk) || defined(__NRFX_DOXYGEN__)
+ uint8_t termlen; /**< Length of TERM field in Long Range operation. */
+#endif
+ uint8_t maxlen; /**< Maximum length of packet payload. */
+ uint8_t statlen; /**< Static length in number of bytes. */
+ uint8_t balen; /**< Base address length in number of bytes. */
+ bool big_endian; /**< On air endianness of packet. */
+ bool whiteen; /**< Enable or disable packet whitening. */
+} nrf_radio_packet_conf_t;
+
+/**
+ * @brief Function for activating a specific RADIO task.
+ *
+ * @param[in] radio_task Task to activate.
+ */
+__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task);
+
+/**
+ * @brief Function for getting the address of a specific RADIO task register.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in] radio_task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task);
+
+/**
+ * @brief Function for clearing a specific RADIO event.
+ *
+ * @param[in] radio_event Event to clean.
+ */
+__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event);
+
+/**
+ * @brief Function for checking the state of a specific RADIO event.
+ *
+ * @param[in] radio_event Event to check.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event);
+
+/**
+ * @brief Function for getting the address of a specific RADIO event register.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in] radio_event Requested Event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event);
+
+/**
+ * @brief Function for enabling specified RADIO shortcuts.
+ *
+ * @param[in] radio_shorts_mask Mask of shortcuts.
+ *
+ */
+__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask);
+
+/**
+ * @brief Function for disabling specified RADIO shortcuts.
+ *
+ * @param[in] radio_shorts_mask Mask of shortcuts.
+ */
+__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask);
+
+/**
+ * @brief Function for setting the configuration of RADIO shortcuts.
+ *
+ * @param[in] radio_shorts_mask Shortcuts configuration to set.
+ */
+__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask);
+
+/**
+ * @brief Function for getting the configuration of RADIO shortcuts.
+ *
+ * @return Mask of currently enabled shortcuts.
+ */
+__STATIC_INLINE uint32_t nrf_radio_shorts_get(void);
+
+/**
+ * @brief Function for enabling specified RADIO interrupts.
+ *
+ * @param[in] radio_int_mask Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask);
+
+/**
+ * @brief Function for disabling specified RADIO interrupts.
+ *
+ * @param[in] radio_int_mask Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask);
+
+/**
+ * @brief Function for getting the state of a specific interrupt.
+ *
+ * @param[in] radio_int_mask Interrupt to check.
+ *
+ * @retval true If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask);
+
+/**
+ * @brief Function for getting CRC status of last received packet.
+ *
+ * @retval true If the packet was received without CRC error .
+ * @retval false If the packet was received with CRC error.
+ */
+__STATIC_INLINE bool nrf_radio_crc_status_check(void);
+
+/**
+ * @brief Function for getting the received address.
+ *
+ * @return Received address.
+ */
+__STATIC_INLINE uint8_t nrf_radio_rxmatch_get(void);
+
+/**
+ * @brief Function for getting CRC field of the last received packet.
+ *
+ * @return CRC field of previously received packet.
+ */
+__STATIC_INLINE uint32_t nrf_radio_rxcrc_get(void);
+
+/**
+ * @brief Function for getting the device address match index.
+ *
+ * @return Device adress match index.
+ */
+__STATIC_INLINE uint8_t nrf_radio_dai_get(void);
+
+#if defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting status on payload length.
+ *
+ * @retval 0 If the payload is lesser than PCNF1.MAXLEN.
+ * @retval 1 If the payload is greater than PCNF1.MAXLEN.
+ */
+__STATIC_INLINE uint8_t nrf_radio_pdustat_get(void);
+
+/**
+ * @brief Function for getting status on what rate packet is received with in Long Range.
+ *
+ * @retval 0 If the frame is received at 125kbps.
+ * @retval 1 If the frame is received at 500kbps.
+ */
+__STATIC_INLINE uint8_t nrf_radio_cistat_get(void);
+#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for setting packet pointer to given location in memory.
+ *
+ * @param[in] p_packet Packet pointer.
+ */
+__STATIC_INLINE void nrf_radio_packetptr_set(const void * p_packet);
+
+/**
+ * @brief Function for getting packet pointer.
+ *
+ * @return Pointer to tx or rx packet buffer.
+ */
+__STATIC_INLINE void * nrf_radio_packetptr_get(void);
+
+/**
+ * @brief Function for setting the radio frequency.
+ *
+ * @param[in] radio_frequency Frequency in MHz.
+ */
+__STATIC_INLINE void nrf_radio_frequency_set(uint16_t radio_frequency);
+
+/**
+ * @brief Function for getting the radio frequency.
+ *
+ * @return Frequency in MHz.
+ */
+__STATIC_INLINE uint16_t nrf_radio_frequency_get(void);
+
+/**
+ * @brief Function for setting the radio transmit power.
+ *
+ * @param[in] tx_power Transmit power of the radio [dBm].
+ */
+__STATIC_INLINE void nrf_radio_txpower_set(nrf_radio_txpower_t tx_power);
+
+/**
+ * @brief Function for getting the radio transmit power.
+ *
+ * @return Transmit power of the radio.
+ */
+__STATIC_INLINE nrf_radio_txpower_t nrf_radio_txpower_get(void);
+
+/**
+ * @brief Function for setting the radio data rate and modulation settings.
+ *
+ * @param[in] radio_mode Radio data rate and modulation.
+ */
+__STATIC_INLINE void nrf_radio_mode_set(nrf_radio_mode_t radio_mode);
+
+/**
+ * @brief Function for getting Radio data rate and modulation settings.
+ *
+ * @return Radio data rate and modulation.
+ */
+__STATIC_INLINE nrf_radio_mode_t nrf_radio_mode_get(void);
+
+/**
+ * @brief Function for setting the packet configuration.
+ *
+ * @param[in] p_config Pointer to the structure with packet configuration.
+ */
+__STATIC_INLINE void nrf_radio_packet_configure(const nrf_radio_packet_conf_t * p_config);
+
+/**
+ * @brief Function for setting the base address 0.
+ *
+ * @param address Base address 0 value.
+ */
+__STATIC_INLINE void nrf_radio_base0_set(uint32_t address);
+
+/**
+ * @brief Function for getting the base address 0.
+ *
+ * @return Base address 0.
+ */
+__STATIC_INLINE uint32_t nrf_radio_base0_get(void);
+
+/**
+ * @brief Function for setting Base address 1.
+ *
+ * @param address Base address 1 value.
+ */
+__STATIC_INLINE void nrf_radio_base1_set(uint32_t address);
+
+/**
+ * @brief Function for getting base address 1.
+ *
+ * @return Base address 1.
+ */
+__STATIC_INLINE uint32_t nrf_radio_base1_get(void);
+
+/**
+ * @brief Function for setting prefixes bytes for logical addresses 0-3.
+ *
+ * @param prefixes Prefixes bytes for logical addresses 0-3.
+ */
+__STATIC_INLINE void nrf_radio_prefix0_set(uint32_t prefixes);
+
+/**
+ * @brief Function for getting prefixes bytes for logical addresses 0-3
+ *
+ * @return Prefixes bytes for logical addresses 0-3
+ */
+__STATIC_INLINE uint32_t nrf_radio_prefix0_get(void);
+
+/**
+ * @brief Function for setting prefixes bytes for logical addresses 4-7.
+ *
+ * @param prefixes Prefixes bytes for logical addresses 4-7.
+ */
+__STATIC_INLINE void nrf_radio_prefix1_set(uint32_t prefixes);
+
+/**
+ * @brief Function for getting prefixes bytes for logical addresses 4-7
+ *
+ * @return Prefixes bytes for logical addresses 4-7
+ */
+__STATIC_INLINE uint32_t nrf_radio_prefix1_get(void);
+
+/**
+ * @brief Function for setting the transmit address.
+ *
+ * @param txaddress Logical address to be used when transmitting a packet.
+ */
+__STATIC_INLINE void nrf_radio_txaddress_set(uint8_t txaddress);
+
+/**
+ * @brief Function for getting the transmit address select.
+ *
+ * @return Logical address to be used when transmitting a packet.
+ */
+__STATIC_INLINE uint8_t nrf_radio_txaddress_get(void);
+
+/**
+ * @brief Function for for selecting the receive addresses.
+ *
+ * @param rxaddresses Enable or disable reception on logical address i.
+ * Read more in the Product Specification.
+ */
+__STATIC_INLINE void nrf_radio_rxaddresses_set(uint8_t rxaddresses);
+
+/**
+ * @brief Function for getting receive address select.
+ *
+ * @return Receive address select.
+ */
+__STATIC_INLINE uint8_t nrf_radio_rxaddresses_get(void);
+
+/**
+ * @brief Function for configure CRC.
+ *
+ * @param[in] crc_length CRC length in number of bytes [0-3].
+ * @param[in] crc_address Include or exclude packet address field out of CRC.
+ * @param[in] crc_polynominal CRC polynominal to set.
+ */
+__STATIC_INLINE void nrf_radio_crc_configure(uint8_t crc_length,
+ nrf_radio_crc_addr_t crc_address,
+ uint32_t crc_polynominal);
+
+/**
+ * @brief Function for setting CRC initial value.
+ *
+ * @param crc_init_value CRC initial value
+ */
+__STATIC_INLINE void nrf_radio_crcinit_set(uint32_t crc_init_value);
+
+/**
+ * @brief Function for getting CRC initial value.
+ *
+ * @return CRC initial value.
+ */
+__STATIC_INLINE uint32_t nrf_radio_crcinit_get(void);
+
+/**
+ * @brief Function for setting Inter Frame Spacing interval.
+ *
+ * @param[in] radio_ifs Inter frame spacing interval [us].
+ */
+__STATIC_INLINE void nrf_radio_ifs_set(uint32_t radio_ifs);
+
+/**
+ * @brief Function for getting Inter Frame Spacing interval.
+ *
+ * @return Inter frame spacing interval [us].
+ */
+__STATIC_INLINE uint32_t nrf_radio_ifs_get(void);
+
+/**
+ * @brief Function for getting RSSI sample result.
+ *
+ * @note The read value is a positive value while the actual received signal
+ * is a negative value. Actual received signal strength is therefore as follows:
+ * received signal strength = - read_value dBm .
+ *
+ * @return RSSI sample result.
+ */
+__STATIC_INLINE uint8_t nrf_radio_rssi_sample_get(void);
+
+/**
+ * @brief Function for getting the current state of the radio module.
+ *
+ * @return Current radio state.
+ */
+__STATIC_INLINE nrf_radio_state_t nrf_radio_state_get(void);
+
+/**
+ * @brief Function for setting the data whitening initial value.
+ *
+ * @param datawhiteiv Data whitening initial value.
+ */
+__STATIC_INLINE void nrf_radio_datawhiteiv_set(uint8_t datawhiteiv);
+
+/**
+ * @brief Function for getting the data whitening initial value.
+ *
+ * @return Data whitening initial value.
+ */
+__STATIC_INLINE uint8_t nrf_radio_datawhiteiv_get(void);
+
+/**
+ * @brief Function for setting Bit counter compare.
+ *
+ * @param[in] radio_bcc Bit counter compare [bits].
+ */
+__STATIC_INLINE void nrf_radio_bcc_set(uint32_t radio_bcc);
+
+/**
+ * @brief Function for getting Bit counter compare.
+ *
+ * @return Bit counter compare.
+ */
+__STATIC_INLINE uint32_t nrf_radio_bcc_get(void);
+
+/**
+ * @brief Function for setting Device address base segment.
+ *
+ * @param dab_value Particular base segment value.
+ * @param segment Index of the particular Device address base segment register.
+ */
+__STATIC_INLINE void nrf_radio_dab_set(uint32_t dab_value, uint8_t segment);
+
+/**
+ * @brief Function for getting Device address base segment.
+ *
+ * @param segment Number of the Device address base segment.
+ *
+ * @return Particular segment of the Device address base.
+ */
+__STATIC_INLINE uint32_t nrf_radio_dab_get(uint8_t segment);
+
+/**
+ * @brief Function for setting device address prefix.
+ *
+ * @param dap_value Particular device address prefix value.
+ * @param prefix_index Index of the particular device address prefix register.
+ */
+__STATIC_INLINE void nrf_radio_dap_set(uint16_t dap_value, uint8_t prefix_index);
+
+/**
+ * @brief Function for getting Device address prefix.
+ *
+ * @param prefix_index Number of the Device address prefix segment.
+ *
+ * @return Particular segment of the Device address prefix.
+ */
+__STATIC_INLINE uint32_t nrf_radio_dap_get(uint8_t prefix_index);
+
+/**
+ * @brief Function for setting device address match configuration.
+ *
+ * @note Read more about configuring device address match in the Product Specification.
+ *
+ * @param ena Device address matching bitmask.
+ * @param txadd TxAdd bitmask.
+ */
+__STATIC_INLINE void nrf_radio_dacnf_set(uint8_t ena, uint8_t txadd);
+
+/**
+ * @brief Function for getting ENA field of the Device address match configuration register.
+ *
+ * @return ENA field of the Device address match configuration register.
+ */
+__STATIC_INLINE uint8_t nrf_radio_dacnf_ena_get(void);
+
+/**
+ * @brief Function for getting TXADD field of the Device address match configuration register.
+ *
+ * @return TXADD field of the Device address match configuration register.
+ */
+__STATIC_INLINE uint8_t nrf_radio_dacnf_txadd_get(void);
+
+#if defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting MAC Header Match Unit search pattern configuration.
+ *
+ * @param[in] radio_mhmu_search_pattern Search Pattern Configuration.
+ */
+__STATIC_INLINE void nrf_radio_mhmu_search_pattern_set(uint32_t radio_mhmu_search_pattern);
+
+/**
+ * @brief Function for getting MAC Header Match Unit search pattern configuration.
+ *
+ * @return Search Pattern Configuration.
+ */
+__STATIC_INLINE uint32_t nrf_radio_mhmu_search_pattern_get(void);
+
+/**
+ * @brief Function for setting MAC Header Match Unit pattern mask configuration.
+ *
+ * @param[in] radio_mhmu_pattern_mask Pattern mask.
+ */
+__STATIC_INLINE void nrf_radio_mhmu_pattern_mask_set(uint32_t radio_mhmu_pattern_mask);
+
+/**
+ * @brief Function for getting MAC Header Match Unit pattern mask configuration.
+ *
+ * @return Pattern mask.
+ */
+__STATIC_INLINE uint32_t nrf_radio_mhmu_pattern_mask_get(void);
+#endif // defined(RADIO_INTENSET_MHRMATCH_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined(RADIO_MODECNF0_RU_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting Radio mode configuration register 0.
+ *
+ * @param fast_ramp_up Use fast radio ramp-up time
+ * @param default_tx Default TX value during inactivity.
+ */
+__STATIC_INLINE void nrf_radio_modecnf0_set(bool fast_ramp_up, uint8_t default_tx);
+
+/**
+ * @brief Function for getting ramp-up time configuration of the Radio mode configuration register 0.
+ *
+ * @retval true If the ramp-up time is set to fast.
+ * @retval false If the ramp-up time is set to default.
+ */
+__STATIC_INLINE bool nrf_radio_modecnf0_ru_get(void);
+
+/**
+ * @brief Function for getting default TX value of the Radio mode configuration register 0.
+ *
+ * @return Default TX value.
+ */
+__STATIC_INLINE uint8_t nrf_radio_modecnf0_dtx_get(void);
+#endif // defined(RADIO_MODECNF0_RU_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined(RADIO_SFD_SFD_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting IEEE 802.15.4 start of frame delimiter.
+ *
+ * @param sfd IEEE 802.15.4 start of frame delimiter.
+ */
+__STATIC_INLINE void nrf_radio_sfd_set(uint8_t sfd);
+
+/**
+ * @brief Function for getting IEEE 802.15.4 start of frame delimiter.
+ *
+ * @return IEEE 802.15.4 start of frame delimiter.
+ */
+__STATIC_INLINE uint8_t nrf_radio_sfd_get(void);
+#endif // defined(RADIO_SFD_SFD_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined(RADIO_EDCNT_EDCNT_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for setting number of iterations to perform ED scan.
+ *
+ * @param[in] ed_loop_count Number of iterations during ED procedure.
+ */
+__STATIC_INLINE void nrf_radio_ed_loop_count_set(uint32_t ed_loop_count);
+#endif // defined(RADIO_EDCNT_EDCNT_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined(RADIO_EDSAMPLE_EDLVL_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for getting Energy Detection level.
+ *
+ * @return IEEE 802.15.4 energy detect level.
+ */
+__STATIC_INLINE uint8_t nrf_radio_ed_sample_get(void);
+#endif // defined(RADIO_EDSAMPLE_EDLVL_Msk) || defined(__NRFX_DOXYGEN__)
+
+#if defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
+/**
+ * @brief Function for configuring the IEEE 802.15.4 clear channel assessment.
+ *
+ * @param cca_mode Mode of CCA.
+ * @param cca_ed_threshold Energy Detection threshold value.
+ * @param cca_corr_threshold Correlator Busy Threshold.
+ * @param cca_corr_cnt Limit of occurances above Correlator Threshold.
+ * When not equal to zero the correlator based
+ * signal detect is enabled.
+ */
+__STATIC_INLINE void nrf_radio_cca_configure(nrf_radio_cca_mode_t cca_mode,
+ uint8_t cca_ed_threshold,
+ uint8_t cca_corr_threshold,
+ uint8_t cca_corr_cnt);
+#endif // defined(RADIO_CCACTRL_CCAMODE_Msk) || defined(__NRFX_DOXYGEN__)
+
+/**
+ * @brief Function for setting power mode of the radio peripheral.
+ *
+ * @param[in] radio_power If radio should be powered on.
+ */
+__STATIC_INLINE void nrf_radio_power_set(bool radio_power);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_radio_task_trigger(nrf_radio_task_t radio_task)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_task_address_get(nrf_radio_task_t radio_task)
+{
+ return ((uint32_t)NRF_RADIO + (uint32_t)radio_task);
+}
+
+__STATIC_INLINE void nrf_radio_event_clear(nrf_radio_event_t radio_event)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_radio_event_check(nrf_radio_event_t radio_event)
+{
+ return (bool) *((volatile uint32_t *)((uint8_t *)NRF_RADIO + radio_event));
+}
+
+__STATIC_INLINE uint32_t nrf_radio_event_address_get(nrf_radio_event_t radio_event)
+{
+ return ((uint32_t)NRF_RADIO + (uint32_t)radio_event);
+}
+
+__STATIC_INLINE void nrf_radio_shorts_enable(uint32_t radio_shorts_mask)
+{
+ NRF_RADIO->SHORTS |= radio_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_radio_shorts_disable(uint32_t radio_shorts_mask)
+{
+ NRF_RADIO->SHORTS &= ~radio_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_radio_shorts_set(uint32_t radio_shorts_mask)
+{
+ NRF_RADIO->SHORTS = radio_shorts_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_shorts_get(void)
+{
+ return NRF_RADIO->SHORTS;
+}
+
+__STATIC_INLINE void nrf_radio_int_enable(uint32_t radio_int_mask)
+{
+ NRF_RADIO->INTENSET = radio_int_mask;
+}
+
+__STATIC_INLINE void nrf_radio_int_disable(uint32_t radio_int_mask)
+{
+ NRF_RADIO->INTENCLR = radio_int_mask;
+}
+
+__STATIC_INLINE bool nrf_radio_int_enable_check(nrf_radio_int_mask_t radio_int_mask)
+{
+ return (bool)(NRF_RADIO->INTENSET & radio_int_mask);
+}
+
+__STATIC_INLINE bool nrf_radio_crc_status_check(void)
+{
+ return ((NRF_RADIO->CRCSTATUS & RADIO_CRCSTATUS_CRCSTATUS_Msk) >> RADIO_CRCSTATUS_CRCSTATUS_Pos)
+ == RADIO_CRCSTATUS_CRCSTATUS_CRCOk ;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_rxmatch_get(void)
+{
+ return (uint8_t)NRF_RADIO->RXMATCH;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_rxcrc_get(void)
+{
+ return NRF_RADIO->RXCRC;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_dai_get(void)
+{
+ return (uint8_t)NRF_RADIO->DAI;
+}
+
+#if defined(RADIO_PDUSTAT_PDUSTAT_Msk)
+__STATIC_INLINE uint8_t nrf_radio_pdustat_get(void)
+{
+ return (uint8_t)(NRF_RADIO->PDUSTAT & RADIO_PDUSTAT_PDUSTAT_Msk);
+}
+
+__STATIC_INLINE uint8_t nrf_radio_cistat_get(void)
+{
+ return (uint8_t)((NRF_RADIO->PDUSTAT & RADIO_PDUSTAT_CISTAT_Msk) >> RADIO_PDUSTAT_CISTAT_Pos);
+}
+#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk)
+
+__STATIC_INLINE void nrf_radio_packetptr_set(const void * p_packet)
+{
+ NRF_RADIO->PACKETPTR = (uint32_t)p_packet;
+}
+
+__STATIC_INLINE void * nrf_radio_packetptr_get(void)
+{
+ return (void *)NRF_RADIO->PACKETPTR;
+}
+
+__STATIC_INLINE void nrf_radio_frequency_set(uint16_t radio_frequency)
+{
+ NRFX_ASSERT(radio_frequency <= 2500);
+
+#if defined(RADIO_FREQUENCY_MAP_Msk)
+ NRFX_ASSERT(radio_frequency >= 2360);
+
+ uint32_t delta;
+ if (radio_frequency < 2400)
+ {
+ delta = ((uint32_t)(radio_frequency - 2360)) |
+ (RADIO_FREQUENCY_MAP_Low << RADIO_FREQUENCY_MAP_Pos);
+ }
+ else
+ {
+ delta = ((uint32_t)(radio_frequency - 2400)) |
+ (RADIO_FREQUENCY_MAP_Default << RADIO_FREQUENCY_MAP_Pos);
+ }
+
+ NRF_RADIO->FREQUENCY = delta;
+#else
+ NRFX_ASSERT(radio_frequency >= 2400);
+ NRF_RADIO->FREQUENCY = (uint32_t)(2400 - radio_frequency);
+#endif //defined(RADIO_FREQUENCY_MAP_Msk)
+}
+
+__STATIC_INLINE uint16_t nrf_radio_frequency_get(void)
+{
+ uint32_t freq;
+
+#if defined(RADIO_FREQUENCY_MAP_Msk)
+ if (((NRF_RADIO->FREQUENCY & RADIO_FREQUENCY_MAP_Msk) >> RADIO_FREQUENCY_MAP_Pos) ==
+ RADIO_FREQUENCY_MAP_Low)
+ {
+ freq = 2360;
+ }
+ else
+#endif
+ {
+ freq = 2400;
+ }
+ freq += NRF_RADIO->FREQUENCY & RADIO_FREQUENCY_FREQUENCY_Msk;
+
+ return freq;
+}
+
+__STATIC_INLINE void nrf_radio_txpower_set(nrf_radio_txpower_t tx_power)
+{
+ NRF_RADIO->TXPOWER = (((uint32_t)tx_power) << RADIO_TXPOWER_TXPOWER_Pos);
+}
+
+__STATIC_INLINE nrf_radio_txpower_t nrf_radio_txpower_get(void)
+{
+ return (nrf_radio_txpower_t)(NRF_RADIO->TXPOWER >> RADIO_TXPOWER_TXPOWER_Pos);
+}
+
+__STATIC_INLINE void nrf_radio_mode_set(nrf_radio_mode_t radio_mode)
+{
+ NRF_RADIO->MODE = ((uint32_t) radio_mode << RADIO_MODE_MODE_Pos);
+}
+
+__STATIC_INLINE nrf_radio_mode_t nrf_radio_mode_get(void)
+{
+ return (nrf_radio_mode_t)((NRF_RADIO->MODE & RADIO_MODE_MODE_Msk) >> RADIO_MODE_MODE_Pos);
+}
+
+__STATIC_INLINE void nrf_radio_packet_configure(const nrf_radio_packet_conf_t * p_config)
+{
+ NRF_RADIO->PCNF0 = (((uint32_t)p_config->lflen << RADIO_PCNF0_LFLEN_Pos) |
+ ((uint32_t)p_config->s0len << RADIO_PCNF0_S0LEN_Pos) |
+ ((uint32_t)p_config->s1len << RADIO_PCNF0_S1LEN_Pos) |
+#if defined(RADIO_PCNF0_S1INCL_Msk)
+ (p_config->s1incl ?
+ (RADIO_PCNF0_S1INCL_Include << RADIO_PCNF0_S1INCL_Pos) :
+ (RADIO_PCNF0_S1INCL_Automatic << RADIO_PCNF0_S1INCL_Pos) ) |
+#endif
+#if defined(RADIO_PCNF0_CILEN_Msk)
+ ((uint32_t)p_config->cilen << RADIO_PCNF0_CILEN_Pos) |
+#endif
+#if defined(RADIO_PCNF0_PLEN_Msk)
+ ((uint32_t)p_config->plen << RADIO_PCNF0_PLEN_Pos) |
+#endif
+#if defined(RADIO_PCNF0_CRCINC_Msk)
+ (p_config->crcinc ?
+ (RADIO_PCNF0_CRCINC_Include << RADIO_PCNF0_CRCINC_Pos) :
+ (RADIO_PCNF0_CRCINC_Exclude << RADIO_PCNF0_CRCINC_Pos) ) |
+#endif
+#if defined(RADIO_PCNF0_TERMLEN_Msk)
+ ((uint32_t)p_config->termlen << RADIO_PCNF0_TERMLEN_Pos) |
+#endif
+ 0);
+
+ NRF_RADIO->PCNF1 = (((uint32_t)p_config->maxlen << RADIO_PCNF1_MAXLEN_Pos) |
+ ((uint32_t)p_config->statlen << RADIO_PCNF1_STATLEN_Pos) |
+ ((uint32_t)p_config->balen << RADIO_PCNF1_BALEN_Pos) |
+ (p_config->big_endian ?
+ (RADIO_PCNF1_ENDIAN_Big << RADIO_PCNF1_ENDIAN_Pos) :
+ (RADIO_PCNF1_ENDIAN_Little << RADIO_PCNF1_ENDIAN_Pos) ) |
+ (p_config->whiteen ?
+ (RADIO_PCNF1_WHITEEN_Enabled << RADIO_PCNF1_WHITEEN_Pos) :
+ (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) ));
+}
+
+__STATIC_INLINE void nrf_radio_base0_set(uint32_t address)
+{
+ NRF_RADIO->BASE0 = address;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_base0_get(void)
+{
+ return NRF_RADIO->BASE0;
+}
+
+__STATIC_INLINE void nrf_radio_base1_set(uint32_t address)
+{
+ NRF_RADIO->BASE1 = address;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_base1_get(void)
+{
+ return NRF_RADIO->BASE1;
+}
+
+__STATIC_INLINE void nrf_radio_prefix0_set(uint32_t prefix0_value)
+{
+ NRF_RADIO->PREFIX0 = prefix0_value;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_prefix0_get(void)
+{
+ return NRF_RADIO->PREFIX0;
+}
+
+__STATIC_INLINE void nrf_radio_prefix1_set(uint32_t prefix1_value)
+{
+ NRF_RADIO->PREFIX1 = prefix1_value;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_prefix1_get(void)
+{
+ return NRF_RADIO->PREFIX1;
+}
+
+__STATIC_INLINE void nrf_radio_txaddress_set(uint8_t txaddress)
+{
+ NRF_RADIO->TXADDRESS = ((uint32_t)txaddress) << RADIO_TXADDRESS_TXADDRESS_Pos;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_txaddress_get(void)
+{
+ return (uint8_t)((NRF_RADIO->TXADDRESS & RADIO_TXADDRESS_TXADDRESS_Msk) >>
+ RADIO_TXADDRESS_TXADDRESS_Pos);
+}
+
+__STATIC_INLINE void nrf_radio_rxaddresses_set(uint8_t rxaddresses)
+{
+ NRF_RADIO->RXADDRESSES = (uint32_t)(rxaddresses);
+}
+
+__STATIC_INLINE uint8_t nrf_radio_rxaddresses_get(void)
+{
+ return (uint8_t)(NRF_RADIO->RXADDRESSES);
+}
+
+__STATIC_INLINE void nrf_radio_crc_configure(uint8_t crc_length,
+ nrf_radio_crc_addr_t crc_address,
+ uint32_t crc_polynominal)
+{
+ NRF_RADIO->CRCCNF = ((uint32_t)crc_length << RADIO_CRCCNF_LEN_Pos) |
+ ((uint32_t)crc_address << RADIO_CRCCNF_SKIPADDR_Pos);
+ NRF_RADIO->CRCPOLY = (crc_polynominal << RADIO_CRCPOLY_CRCPOLY_Pos);
+}
+
+__STATIC_INLINE void nrf_radio_crcinit_set(uint32_t crc_init_value)
+{
+ NRF_RADIO->CRCINIT = crc_init_value;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_crcinit_get(void)
+{
+ return NRF_RADIO->CRCINIT;
+}
+
+__STATIC_INLINE void nrf_radio_ifs_set(uint32_t radio_ifs)
+{
+ NRF_RADIO->TIFS = radio_ifs;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_ifs_get(void)
+{
+ return NRF_RADIO->TIFS;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_rssi_sample_get(void)
+{
+ return (uint8_t)((NRF_RADIO->RSSISAMPLE & RADIO_RSSISAMPLE_RSSISAMPLE_Msk) >>
+ RADIO_RSSISAMPLE_RSSISAMPLE_Pos);
+}
+
+__STATIC_INLINE nrf_radio_state_t nrf_radio_state_get(void)
+{
+ return (nrf_radio_state_t) NRF_RADIO->STATE;
+}
+
+__STATIC_INLINE void nrf_radio_datawhiteiv_set(uint8_t datawhiteiv)
+{
+ NRF_RADIO->DATAWHITEIV = (((uint32_t)datawhiteiv) & RADIO_DATAWHITEIV_DATAWHITEIV_Msk);
+}
+
+__STATIC_INLINE uint8_t nrf_radio_datawhiteiv_get(void)
+{
+ return (uint8_t)(NRF_RADIO->DATAWHITEIV & RADIO_DATAWHITEIV_DATAWHITEIV_Msk);
+}
+
+__STATIC_INLINE void nrf_radio_bcc_set(uint32_t radio_bcc)
+{
+ NRF_RADIO->BCC = radio_bcc;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_bcc_get(void)
+{
+ return NRF_RADIO->BCC;
+}
+
+__STATIC_INLINE void nrf_radio_dab_set(uint32_t dab_value, uint8_t segment)
+{
+ NRFX_ASSERT(segment < 8);
+ NRF_RADIO->DAB[segment] = dab_value;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_dab_get(uint8_t segment)
+{
+ NRFX_ASSERT(segment < 8);
+ return NRF_RADIO->DAB[segment];
+}
+
+__STATIC_INLINE void nrf_radio_dap_set(uint16_t dap_value, uint8_t prefix_index)
+{
+ NRFX_ASSERT(prefix_index < 8);
+ NRF_RADIO->DAP[prefix_index] = (uint32_t)dap_value;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_dap_get(uint8_t prefix_index)
+{
+ NRFX_ASSERT(prefix_index < 8);
+ return NRF_RADIO->DAP[prefix_index];
+}
+
+__STATIC_INLINE void nrf_radio_dacnf_set(uint8_t ena, uint8_t txadd)
+{
+ NRF_RADIO->DACNF = (((uint32_t)ena << RADIO_DACNF_ENA0_Pos) |
+ ((uint32_t)txadd << RADIO_DACNF_TXADD0_Pos));
+}
+
+__STATIC_INLINE uint8_t nrf_radio_dacnf_ena_get(void)
+{
+ return (NRF_RADIO->DACNF & (RADIO_DACNF_ENA0_Msk |
+ RADIO_DACNF_ENA1_Msk |
+ RADIO_DACNF_ENA2_Msk |
+ RADIO_DACNF_ENA3_Msk |
+ RADIO_DACNF_ENA4_Msk |
+ RADIO_DACNF_ENA5_Msk |
+ RADIO_DACNF_ENA6_Msk |
+ RADIO_DACNF_ENA7_Msk)) >> RADIO_DACNF_ENA0_Pos;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_dacnf_txadd_get(void)
+{
+ return (NRF_RADIO->DACNF & (RADIO_DACNF_TXADD0_Msk |
+ RADIO_DACNF_TXADD1_Msk |
+ RADIO_DACNF_TXADD2_Msk |
+ RADIO_DACNF_TXADD3_Msk |
+ RADIO_DACNF_TXADD4_Msk |
+ RADIO_DACNF_TXADD5_Msk |
+ RADIO_DACNF_TXADD6_Msk |
+ RADIO_DACNF_TXADD7_Msk)) >> RADIO_DACNF_TXADD0_Pos;
+}
+
+#if defined(RADIO_INTENSET_MHRMATCH_Msk)
+__STATIC_INLINE void nrf_radio_mhmu_search_pattern_set(uint32_t radio_mhmu_search_pattern)
+{
+ NRF_RADIO->MHRMATCHCONF = radio_mhmu_search_pattern;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_mhmu_search_pattern_get(void)
+{
+ return NRF_RADIO->MHRMATCHCONF;
+}
+
+__STATIC_INLINE void nrf_radio_mhmu_pattern_mask_set(uint32_t radio_mhmu_pattern_mask)
+{
+ NRF_RADIO->MHRMATCHMAS = radio_mhmu_pattern_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_radio_mhmu_pattern_mask_get(void)
+{
+ return NRF_RADIO->MHRMATCHMAS;
+}
+#endif // defined(RADIO_INTENSET_MHRMATCH_Msk)
+
+#if defined(RADIO_MODECNF0_RU_Msk)
+__STATIC_INLINE void nrf_radio_modecnf0_set(bool fast_ramp_up, uint8_t default_tx)
+{
+ NRF_RADIO->MODECNF0 = (fast_ramp_up ? (RADIO_MODECNF0_RU_Fast << RADIO_MODECNF0_RU_Pos) :
+ (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) ) |
+ (((uint32_t)default_tx) << RADIO_MODECNF0_DTX_Pos);
+}
+
+__STATIC_INLINE bool nrf_radio_modecnf0_ru_get(void)
+{
+ return ((NRF_RADIO->MODECNF0 & RADIO_MODECNF0_RU_Msk) >> RADIO_MODECNF0_RU_Pos) ==
+ RADIO_MODECNF0_RU_Fast;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_modecnf0_dtx_get(void)
+{
+ return (uint8_t)((NRF_RADIO->MODECNF0 & RADIO_MODECNF0_DTX_Msk) >> RADIO_MODECNF0_DTX_Pos);
+}
+#endif // defined(RADIO_MODECNF0_RU_Msk)
+
+#if defined(RADIO_SFD_SFD_Msk)
+__STATIC_INLINE void nrf_radio_sfd_set(uint8_t sfd)
+{
+ NRF_RADIO->SFD = ((uint32_t)sfd) << RADIO_SFD_SFD_Pos;
+}
+
+__STATIC_INLINE uint8_t nrf_radio_sfd_get(void)
+{
+ return (uint8_t)((NRF_RADIO->SFD & RADIO_SFD_SFD_Msk) >> RADIO_SFD_SFD_Pos);
+}
+#endif // defined(RADIO_SFD_SFD_Msk)
+
+#if defined(RADIO_EDCNT_EDCNT_Msk)
+__STATIC_INLINE void nrf_radio_ed_loop_count_set(uint32_t ed_loop_count)
+{
+ NRF_RADIO->EDCNT = (ed_loop_count & RADIO_EDCNT_EDCNT_Msk);
+}
+#endif
+
+#if defined(RADIO_EDSAMPLE_EDLVL_Msk)
+__STATIC_INLINE uint8_t nrf_radio_ed_sample_get(void)
+{
+ return (uint8_t) NRF_RADIO->EDSAMPLE;
+}
+#endif
+
+#if defined(RADIO_CCACTRL_CCAMODE_Msk)
+
+__STATIC_INLINE void nrf_radio_cca_configure(nrf_radio_cca_mode_t cca_mode,
+ uint8_t cca_ed_threshold,
+ uint8_t cca_corr_threshold,
+ uint8_t cca_corr_cnt)
+{
+ NRF_RADIO->CCACTRL = (((uint32_t)cca_mode << RADIO_CCACTRL_CCAMODE_Pos) |
+ ((uint32_t)cca_ed_threshold << RADIO_CCACTRL_CCAEDTHRES_Pos) |
+ ((uint32_t)cca_corr_threshold << RADIO_CCACTRL_CCACORRTHRES_Pos) |
+ ((uint32_t)cca_corr_cnt << RADIO_CCACTRL_CCACORRCNT_Pos));
+}
+#endif
+
+__STATIC_INLINE void nrf_radio_power_set(bool radio_power)
+{
+ NRF_RADIO->POWER = (uint32_t) radio_power;
+}
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_RADIO_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
index 2d932ba498..21cee2db67 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
index cb1218c852..a104ab8f85 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
index b72f320812..537141885a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -407,6 +407,19 @@ __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
}
+/**
+ * @brief Function for configuring the positive input pin for a specific SAADC channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] pselp Positive input.
+ */
+__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel,
+ nrf_saadc_input_t pselp)
+{
+ NRF_SAADC->CH[channel].PSELP = pselp;
+}
+
+
/**
* @brief Function for setting the SAADC channel monitoring limits.
*
@@ -526,19 +539,44 @@ __STATIC_INLINE bool nrf_saadc_enable_check(void)
/**
* @brief Function for initializing the SAADC result buffer.
*
- * @param[in] buffer Pointer to the result buffer.
- * @param[in] num Size of buffer in words.
+ * @param[in] p_buffer Pointer to the result buffer.
+ * @param[in] size Size of the buffer (in 16-bit samples).
*/
-__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num)
+__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * p_buffer,
+ uint32_t size)
{
- NRF_SAADC->RESULT.PTR = (uint32_t)buffer;
- NRF_SAADC->RESULT.MAXCNT = num;
+ NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer;
+ NRF_SAADC->RESULT.MAXCNT = size;
}
+
/**
- * @brief Function for getting the number of buffer words transferred since last START operation.
+ * @brief Function for setting the SAADC result buffer pointer.
*
- * @returns Number of words transferred.
+ * @param[in] p_buffer Pointer to the result buffer.
+ */
+__STATIC_INLINE void nrf_saadc_buffer_pointer_set(nrf_saadc_value_t * p_buffer)
+{
+ NRF_SAADC->RESULT.PTR = (uint32_t)p_buffer;
+}
+
+
+/**
+ * @brief Function for getting the SAADC result buffer pointer.
+ *
+ * @return Pointer to the result buffer.
+ */
+__STATIC_INLINE nrf_saadc_value_t * nrf_saadc_buffer_pointer_get(void)
+{
+ return (nrf_saadc_value_t *)NRF_SAADC->RESULT.PTR;
+}
+
+
+/**
+ * @brief Function for getting the number of samples written to the result
+ * buffer since the previous START task.
+ *
+ * @returns Number of 16-bit samples written to the buffer.
*/
__STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
{
@@ -597,6 +635,20 @@ __STATIC_INLINE void nrf_saadc_channel_init(uint8_t
nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
}
+/**
+ * @brief Function for configuring the burst mode for the specified channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] burst Burst mode setting.
+ */
+__STATIC_INLINE void nrf_saadc_burst_set(uint8_t channel,
+ nrf_saadc_burst_t burst)
+{
+ NRF_SAADC->CH[channel].CONFIG =
+ (NRF_SAADC->CH[channel].CONFIG & ~SAADC_CH_CONFIG_BURST_Msk) |
+ (burst << SAADC_CH_CONFIG_BURST_Pos);
+}
+
/** @} */
#ifdef __cplusplus
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
index e672d5420c..d942d2dd7a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
index 1c93e03021..46717bc810 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
index d44d89affa..a644c4619e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
index 110c49368d..3058089ff5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_systick.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2016 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
index 3d567953ca..b08b423332 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2012 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
index 2cf38279a8..f925acfdd4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2014 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
index 90a6217860..2aa275e8c3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
index a67f0bb20e..d1eb5ad854 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
index 8ca0a28943..f689bb6113 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
index 863edf7081..cc00c745a4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
index 0fbef02c1b..03cb513e04 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -73,7 +73,7 @@ typedef enum
NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
- NRF_UARTE_EVENT_TXDDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
+ NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
index 43fc297105..681367f607 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_usbd.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -531,11 +531,11 @@ void nrf_usbd_int_disable(uint32_t int_mask)
*/
typedef enum
{
- NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK = USBD_EVENTCAUSE_ISOOUTCRC_Msk, /**< CRC error was detected on isochronous OUT endpoint 8. */
- NRF_USBD_EVENTCAUSE_SUSPEND_MASK = USBD_EVENTCAUSE_SUSPEND_Msk , /**< Signals that the USB lines have been seen idle long enough for the device to enter suspend. */
- NRF_USBD_EVENTCAUSE_RESUME_MASK = USBD_EVENTCAUSE_RESUME_Msk , /**< Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. */
- NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling */
- NRF_USBD_EVENTCAUSE_WUREQ_MASK = (1U << 10) /**< The USBD peripheral has exited Low Power mode */
+ NRF_USBD_EVENTCAUSE_ISOOUTCRC_MASK = USBD_EVENTCAUSE_ISOOUTCRC_Msk, /**< CRC error was detected on isochronous OUT endpoint 8. */
+ NRF_USBD_EVENTCAUSE_SUSPEND_MASK = USBD_EVENTCAUSE_SUSPEND_Msk, /**< Signals that the USB lines have been seen idle long enough for the device to enter suspend. */
+ NRF_USBD_EVENTCAUSE_RESUME_MASK = USBD_EVENTCAUSE_RESUME_Msk, /**< Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. */
+ NRF_USBD_EVENTCAUSE_WUREQ_MASK = USBD_EVENTCAUSE_USBWUALLOWED_Msk, /**< The USBD peripheral has exited Low Power mode */
+ NRF_USBD_EVENTCAUSE_READY_MASK = USBD_EVENTCAUSE_READY_Msk, /**< MAC is ready for normal operation, rised few us after USBD enabling */
}nrf_usbd_eventcause_mask_t;
/**
@@ -613,10 +613,19 @@ typedef enum
*/
typedef enum
{
- NRF_USBD_ISOSPLIT_OneDir = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either iso IN or OUT */
- NRF_USBD_ISOSPLIT_Half = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half */
+ NRF_USBD_ISOSPLIT_ONEDIR = USBD_ISOSPLIT_SPLIT_OneDir, /**< Full buffer dedicated to either iso IN or OUT */
+ NRF_USBD_ISOSPLIT_HALF = USBD_ISOSPLIT_SPLIT_HalfIN, /**< Buffer divided in half */
}nrf_usbd_isosplit_t;
+/**
+ * @brief ISOINCONFIG configurations
+ */
+typedef enum
+{
+ NRF_USBD_ISOINCONFIG_NORESP = USBD_ISOINCONFIG_RESPONSE_NoResp, /**< Endpoint does not respond to an ISO IN token when no data is ready */
+ NRF_USBD_ISOINCONFIG_ZERODATA = USBD_ISOINCONFIG_RESPONSE_ZeroData, /**< Endpoint responds with a zero-length data packet to an ISO IN token when no data is ready */
+}nrf_usbd_isoinconfig_t;
+
/**
* @brief Function for enabling USBD
*/
@@ -948,6 +957,20 @@ __STATIC_INLINE void nrf_usbd_lowpower_disable(void);
*/
__STATIC_INLINE bool nrf_usbd_lowpower_check(void);
+/**
+ * @brief Function for configuring ISO IN endpoint response to an IN token when no data is ready to be sent.
+ *
+ * @param config Required configuration
+ */
+__STATIC_INLINE void nrf_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config);
+
+/**
+ * @brief Function for getting the cofiguration of ISO IN endpoint response to an IN token when no data is ready to be sent.
+ *
+ * @return Current configuration
+ */
+__STATIC_INLINE nrf_usbd_isoinconfig_t nrf_usbd_isoinconfig_get(void);
+
/**
* @brief Function for configuring EasyDMA channel
*
@@ -1023,12 +1046,12 @@ uint32_t nrf_usbd_haltedep(uint8_t ep)
uint8_t epnr = NRF_USBD_EP_NR_GET(ep);
if (NRF_USBD_EPIN_CHECK(ep))
{
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->HALTED.EPIN));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->HALTED.EPIN));
return NRF_USBD->HALTED.EPIN[epnr];
}
else
{
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->HALTED.EPOUT));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->HALTED.EPOUT));
return NRF_USBD->HALTED.EPOUT[epnr];
}
}
@@ -1077,8 +1100,6 @@ uint32_t nrf_usbd_epdatastatus_get_and_clear(void)
uint32_t ret;
ret = nrf_usbd_epdatastatus_get();
nrf_usbd_epdatastatus_clear(ret);
- __ISB();
- __DSB();
return ret;
}
@@ -1124,7 +1145,7 @@ size_t nrf_usbd_epout_size_get(uint8_t ep)
return size_isoout;
}
- NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) < ARRAY_SIZE(NRF_USBD->SIZE.EPOUT));
+ NRFX_ASSERT(NRF_USBD_EP_NR_GET(ep) < NRFX_ARRAY_SIZE(NRF_USBD->SIZE.EPOUT));
return NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)];
}
@@ -1148,7 +1169,7 @@ size_t nrf_usbd_episoout_size_get(uint8_t ep)
void nrf_usbd_epout_clear(uint8_t ep)
{
- NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < ARRAY_SIZE(NRF_USBD->SIZE.EPOUT)));
+ NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep) && (NRF_USBD_EP_NR_GET(ep) < NRFX_ARRAY_SIZE(NRF_USBD->SIZE.EPOUT)));
NRF_USBD->SIZE.EPOUT[NRF_USBD_EP_NR_GET(ep)] = 0;
__ISB();
__DSB();
@@ -1302,6 +1323,16 @@ bool nrf_usbd_lowpower_check(void)
return (NRF_USBD->LOWPOWER != (USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos));
}
+void nrf_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config)
+{
+ NRF_USBD->ISOINCONFIG = ((uint32_t)config) << USBD_ISOINCONFIG_RESPONSE_Pos;
+}
+
+nrf_usbd_isoinconfig_t nrf_usbd_isoinconfig_get(void)
+{
+ return (nrf_usbd_isoinconfig_t)
+ (((NRF_USBD->ISOINCONFIG) & USBD_ISOINCONFIG_RESPONSE_Msk) >> USBD_ISOINCONFIG_RESPONSE_Pos);
+}
void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt)
{
@@ -1315,7 +1346,7 @@ void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt)
else
{
uint8_t epnr = NRF_USBD_EP_NR_GET(ep);
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPIN));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPIN));
NRF_USBD->EPIN[epnr].PTR = ptr;
NRF_USBD->EPIN[epnr].MAXCNT = maxcnt;
}
@@ -1330,7 +1361,7 @@ void nrf_usbd_ep_easydma_set(uint8_t ep, uint32_t ptr, uint32_t maxcnt)
else
{
uint8_t epnr = NRF_USBD_EP_NR_GET(ep);
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT));
NRF_USBD->EPOUT[epnr].PTR = ptr;
NRF_USBD->EPOUT[epnr].MAXCNT = maxcnt;
}
@@ -1350,7 +1381,7 @@ uint32_t nrf_usbd_ep_amount_get(uint8_t ep)
else
{
uint8_t epnr = NRF_USBD_EP_NR_GET(ep);
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT));
ret = NRF_USBD->EPIN[epnr].AMOUNT;
}
}
@@ -1363,7 +1394,7 @@ uint32_t nrf_usbd_ep_amount_get(uint8_t ep)
else
{
uint8_t epnr = NRF_USBD_EP_NR_GET(ep);
- NRFX_ASSERT(epnr < ARRAY_SIZE(NRF_USBD->EPOUT));
+ NRFX_ASSERT(epnr < NRFX_ARRAY_SIZE(NRF_USBD->EPOUT));
ret = NRF_USBD->EPOUT[epnr].AMOUNT;
}
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
index ab851f2b64..81c88bf968 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
@@ -1,21 +1,21 @@
-/**
+/*
* Copyright (c) 2015 - 2018, Nordic Semiconductor ASA
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
- *
+ *
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
- *
+ *
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
+ *
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
index 8b24d631ae..a697f612d5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
@@ -17,9 +17,11 @@
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
#endif
ENDIF
@@ -28,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 2048
+Stack_Size EQU 2048
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -46,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 2048
+Heap_Size EQU 2048
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
@@ -132,7 +134,7 @@ Reset_Handler PROC
IMPORT SystemInit
IMPORT __main
- MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
index 9e06ea998f..62da860879 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
@@ -17,9 +17,11 @@
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
#endif
ENDIF
@@ -28,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 8192
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -46,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 8192
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
index 24adada3b2..a41de458cb 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
@@ -17,9 +17,11 @@
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
#endif
ENDIF
@@ -28,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 2048
+Stack_Size EQU 2048
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -46,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 2048
+Heap_Size EQU 2048
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
index 1c5f17b61b..1a1662d4e3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
@@ -17,9 +17,11 @@
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
+#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
#endif
ENDIF
@@ -28,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 8192
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -46,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 8192
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
index 3322af724b..9ecb0ff97a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 2048
+ .equ Heap_Size, 2048
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -129,7 +129,7 @@ __isr_vector:
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
- .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
.text
.thumb
@@ -164,11 +164,11 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__bss_start__
- subs r3, r2
+ subs r3, r3, r2
ble .L_loop1_done
.L_loop1:
- subs r3, #4
+ subs r3, r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
@@ -191,11 +191,11 @@ Reset_Handler:
movs r0, 0
- subs r2, r1
+ subs r2, r2, r1
ble .L_loop3_done
.L_loop3:
- subs r2, #4
+ subs r2, r2, #4
str r0, [r1, r2]
bgt .L_loop3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
index f523b483d8..dfc79ee47d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 8192
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -230,11 +230,11 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__bss_start__
- subs r3, r2
+ subs r3, r3, r2
ble .L_loop1_done
.L_loop1:
- subs r3, #4
+ subs r3, r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
@@ -257,11 +257,11 @@ Reset_Handler:
movs r0, 0
- subs r2, r1
+ subs r2, r2, r1
ble .L_loop3_done
.L_loop3:
- subs r2, #4
+ subs r2, r2, #4
str r0, [r1, r2]
bgt .L_loop3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
index 58250ab68a..1c782f4c87 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 2048
+ .equ Heap_Size, 2048
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -230,11 +230,11 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__bss_start__
- subs r3, r2
+ subs r3, r3, r2
ble .L_loop1_done
.L_loop1:
- subs r3, #4
+ subs r3, r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
@@ -257,11 +257,11 @@ Reset_Handler:
movs r0, 0
- subs r2, r1
+ subs r2, r2, r1
ble .L_loop3_done
.L_loop3:
- subs r2, #4
+ subs r2, r2, #4
str r0, [r1, r2]
bgt .L_loop3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
index a8b6e8d6a3..0de37bbc69 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 8192
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -230,11 +230,11 @@ Reset_Handler:
ldr r2, =__data_start__
ldr r3, =__bss_start__
- subs r3, r2
+ subs r3, r3, r2
ble .L_loop1_done
.L_loop1:
- subs r3, #4
+ subs r3, r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
@@ -257,11 +257,11 @@ Reset_Handler:
movs r0, 0
- subs r2, r1
+ subs r2, r2, r1
ble .L_loop3_done
.L_loop3:
- subs r2, #4
+ subs r2, r2, #4
str r0, [r1, r2]
bgt .L_loop3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
index bbd662efde..c3feaeece5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
@@ -305,7 +305,6 @@ SWI4_IRQHandler
SWI5_IRQHandler
B .
-
END
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
index 904c719523..d58433962e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
@@ -451,7 +451,6 @@ I2S_IRQHandler
FPU_IRQHandler
B .
-
END
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
index eff0a97855..e1342f9b59 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
@@ -401,7 +401,6 @@ PWM0_IRQHandler
PDM_IRQHandler
B .
-
END
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
index c21cbcf29f..2ad45029bf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
@@ -481,7 +481,6 @@ PWM3_IRQHandler
SPIM3_IRQHandler
B .
-
END
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nRFxxx.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nRFxxx.h
deleted file mode 100644
index ba7205237f..0000000000
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nRFxxx.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*****************************************************************************
- * SEGGER Microcontroller GmbH & Co. KG *
- * Solutions for real time microcontroller applications *
- *****************************************************************************
- * *
- * (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
- * *
- * Internet: www.segger.com Support: support@segger.com *
- * *
- *****************************************************************************/
-
-#ifndef __nRFxxx_h
-#define __nRFxxx_h
-
-#if defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF51) || defined(NRF52) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA)
-
-#include "nrf.h"
-
-#endif
-
-#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
index b2447339ad..5cd8040cc8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
@@ -35,7 +35,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
-#define MDK_MINOR_VERSION 16
+#define MDK_MINOR_VERSION 17
#define MDK_MICRO_VERSION 0
/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
@@ -66,24 +66,26 @@ POSSIBILITY OF SUCH DAMAGE.
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
- #elif defined (NRF52840_XXAA)
- #include "nrf52840.h"
- #include "nrf52840_bitfields.h"
- #include "nrf51_to_nrf52840.h"
- #include "nrf52_to_nrf52840.h"
- #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
- #include "nrf52.h"
- #include "nrf52_bitfields.h"
- #include "nrf51_to_nrf52.h"
- #include "nrf52_name_change.h"
+
#elif defined (NRF52810_XXAA)
#include "nrf52810.h"
#include "nrf52810_bitfields.h"
#include "nrf51_to_nrf52810.h"
#include "nrf52_to_nrf52810.h"
+ #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
+ #include "nrf52.h"
+ #include "nrf52_bitfields.h"
+ #include "nrf51_to_nrf52.h"
+ #include "nrf52_name_change.h"
+ #elif defined (NRF52840_XXAA)
+ #include "nrf52840.h"
+ #include "nrf52840_bitfields.h"
+ #include "nrf51_to_nrf52840.h"
+ #include "nrf52_to_nrf52840.h"
+
#else
#error "Device must be defined. See nrf.h."
- #endif /* NRF51, NRF52832_XXAA, NRF52832_XXAB, NRF52810_XXAA, NRF52840_XXAA */
+ #endif /* NRF51, NRF52810_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA */
#include "compiler_abstraction.h"
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
index 5652089e10..6dea9a4ea0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
@@ -1,46 +1,40 @@
-
-/****************************************************************************************************//**
- * @file nrf51.h
- *
- * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
- * nrf51 from Nordic Semiconductor.
- *
- * @version V522
- * @date 8. March 2018
- *
- * @note Generated with SVDConv V2.81d
- * from CMSIS SVD File 'nrf51.svd' Version 522,
- *
- * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
+/*
+ * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*
- *******************************************************************************************************/
+ * @file nrf51.h
+ * @brief CMSIS HeaderFile
+ * @version 522
+ * @date 06. June 2018
+ * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38
+ * from File 'nrf51.svd',
+ * last modified on Wednesday, 06.06.2018 13:21:34
+ */
@@ -48,10 +42,12 @@
* @{
*/
+
/** @addtogroup nrf51
* @{
*/
+
#ifndef NRF51_H
#define NRF51_H
@@ -60,1134 +56,1246 @@ extern "C" {
#endif
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
- POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
- RADIO_IRQn = 1, /*!< 1 RADIO */
- UART0_IRQn = 2, /*!< 2 UART0 */
- SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
- SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
- GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
- ADC_IRQn = 7, /*!< 7 ADC */
- TIMER0_IRQn = 8, /*!< 8 TIMER0 */
- TIMER1_IRQn = 9, /*!< 9 TIMER1 */
- TIMER2_IRQn = 10, /*!< 10 TIMER2 */
- RTC0_IRQn = 11, /*!< 11 RTC0 */
- TEMP_IRQn = 12, /*!< 12 TEMP */
- RNG_IRQn = 13, /*!< 13 RNG */
- ECB_IRQn = 14, /*!< 14 ECB */
- CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
- WDT_IRQn = 16, /*!< 16 WDT */
- RTC1_IRQn = 17, /*!< 17 RTC1 */
- QDEC_IRQn = 18, /*!< 18 QDEC */
- LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
- SWI0_IRQn = 20, /*!< 20 SWI0 */
- SWI1_IRQn = 21, /*!< 21 SWI1 */
- SWI2_IRQn = 22, /*!< 22 SWI2 */
- SWI3_IRQn = 23, /*!< 23 SWI3 */
- SWI4_IRQn = 24, /*!< 24 SWI4 */
- SWI5_IRQn = 25 /*!< 25 SWI5 */
-} IRQn_Type;
-
-
/** @addtogroup Configuration_of_CMSIS
* @{
*/
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
-#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
-#define __MPU_PRESENT 0 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-/** @} */ /* End of group Configuration_of_CMSIS */
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
-#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
-#include "system_nrf51.h" /*!< nrf51 System */
+typedef enum {
+/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* =========================================== nrf51 Specific Interrupt Numbers ============================================ */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UART0_IRQn = 2, /*!< 2 UART0 */
+ SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
+ SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ ADC_IRQn = 7, /*!< 7 ADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
+ SWI0_IRQn = 20, /*!< 20 SWI0 */
+ SWI1_IRQn = 21, /*!< 21 SWI1 */
+ SWI2_IRQn = 22, /*!< 22 SWI2 */
+ SWI3_IRQn = 23, /*!< 23 SWI3 */
+ SWI4_IRQn = 24, /*!< 24 SWI4 */
+ SWI5_IRQn = 25 /*!< 25 SWI5 */
+} IRQn_Type;
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
+/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */
+#define __CM0_REV 0x0301U /*!< CM0 Core Revision */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */
+#include "system_nrf51.h" /*!< nrf51 System */
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
+
+
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
-#elif defined(__ICCARM__)
+#elif defined (__ICCARM__)
#pragma language=extended
-#elif defined(__GNUC__)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
+#elif defined (__TASKING__)
#pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.)
+ */
typedef struct {
- __O uint32_t EN; /*!< Enable channel group. */
- __O uint32_t DIS; /*!< Disable channel group. */
-} PPI_TASKS_CHG_Type;
+ __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */
+} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_CH [CH] (PPI Channel.)
+ */
typedef struct {
- __IO uint32_t EEP; /*!< Channel event end-point. */
- __IO uint32_t TEP; /*!< Channel task end-point. */
-} PPI_CH_Type;
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */
+} PPI_CH_Type; /*!< Size = 8 (0x8) */
+
+
+/** @} */ /* End of group Device_Peripheral_clusters */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
-/* ================================================================================ */
-/* ================ POWER ================ */
-/* ================================================================================ */
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
+ */
+
+
+
+/* =========================================================================================================================== */
+/* ================ POWER ================ */
+/* =========================================================================================================================== */
/**
* @brief Power Control. (POWER)
*/
-typedef struct { /*!< POWER Structure */
- __I uint32_t RESERVED0[30];
- __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
- __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
- __I uint32_t RESERVED1[34];
- __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __IO uint32_t RESETREAS; /*!< Reset reason. */
- __I uint32_t RESERVED4[9];
- __I uint32_t RAMSTATUS; /*!< Ram status register. */
- __I uint32_t RESERVED5[53];
- __O uint32_t SYSTEMOFF; /*!< System off register. */
- __I uint32_t RESERVED6[3];
- __IO uint32_t POFCON; /*!< Power failure configuration. */
- __I uint32_t RESERVED7[2];
- __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
- register. */
- __I uint32_t RESERVED8;
- __IO uint32_t RAMON; /*!< Ram on/off. */
- __I uint32_t RESERVED9[7];
- __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
- is a retained register. */
- __I uint32_t RESERVED10[3];
- __IO uint32_t RAMONB; /*!< Ram on/off. */
- __I uint32_t RESERVED11[8];
- __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
- __I uint32_t RESERVED12[291];
- __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================ CLOCK ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40000000) POWER Structure */
+ __IM uint32_t RESERVED[30];
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */
+ __IM uint32_t RESERVED1[34];
+ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[61];
+ __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */
+ __IM uint32_t RESERVED4[9];
+ __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */
+ __IM uint32_t RESERVED5[53];
+ __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */
+ __IM uint32_t RESERVED6[3];
+ __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */
+ __IM uint32_t RESERVED7[2];
+ __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register
+ is a retained register. */
+ __IM uint32_t RESERVED8;
+ __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */
+ __IM uint32_t RESERVED9[7];
+ __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register.
+ This register is a retained register. */
+ __IM uint32_t RESERVED10[3];
+ __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */
+ __IM uint32_t RESERVED11[8];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */
+ __IM uint32_t RESERVED12[291];
+ __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */
+} NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CLOCK ================ */
+/* =========================================================================================================================== */
/**
* @brief Clock control. (CLOCK)
*/
-typedef struct { /*!< CLOCK Structure */
- __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
- __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
- __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
- __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
- __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
- __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
- __I uint32_t RESERVED0[57];
- __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
- __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
- __I uint32_t RESERVED1;
- __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
- __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
- __I uint32_t RESERVED2[124];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[63];
- __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
- __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
- __I uint32_t RESERVED4;
- __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
- __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
- __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
- triggered. */
- __I uint32_t RESERVED5[62];
- __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
- __I uint32_t RESERVED6[7];
- __IO uint32_t CTIV; /*!< Calibration timer interval. */
- __I uint32_t RESERVED7[5];
- __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================ MPU ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */
+ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */
+ __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */
+ __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */
+ __IM uint32_t RESERVED[57];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */
+ __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */
+ __IM uint32_t RESERVED2[124];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[63];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task
+ LKCLKSTART is triggered. */
+ __IM uint32_t RESERVED5[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */
+ __IM uint32_t RESERVED7[5];
+ __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */
+} NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ MPU ================ */
+/* =========================================================================================================================== */
/**
* @brief Memory Protection Unit. (MPU)
*/
-typedef struct { /*!< MPU Structure */
- __I uint32_t RESERVED0[330];
- __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
- __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
- __I uint32_t RESERVED1[52];
- __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
- __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
- __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
- __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
-} NRF_MPU_Type;
+typedef struct { /*!< (@ 0x40000000) MPU Structure */
+ __IM uint32_t RESERVED[330];
+ __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */
+ __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */
+ __IM uint32_t RESERVED1[52];
+ __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */
+ __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */
+ __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism
+ in debug mode. */
+ __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */
+} NRF_MPU_Type; /*!< Size = 1552 (0x610) */
+
-/* ================================================================================ */
-/* ================ RADIO ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ RADIO ================ */
+/* =========================================================================================================================== */
/**
* @brief The radio. (RADIO)
*/
-typedef struct { /*!< RADIO Structure */
- __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
- __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
- __O uint32_t TASKS_START; /*!< Start radio. */
- __O uint32_t TASKS_STOP; /*!< Stop radio. */
- __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
- __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
- __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
- __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
- __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
- __I uint32_t RESERVED0[55];
- __IO uint32_t EVENTS_READY; /*!< Ready event. */
- __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
- __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
- __IO uint32_t EVENTS_END; /*!< End event. */
- __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
- __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
- __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
- sample is ready for readout at the RSSISAMPLE register. */
- __I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
- __I uint32_t RESERVED2[53];
- __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[61];
- __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t RESERVED5;
- __I uint32_t RXMATCH; /*!< Received address. */
- __I uint32_t RXCRC; /*!< Received CRC. */
- __I uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED6[60];
- __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
- __IO uint32_t FREQUENCY; /*!< Frequency. */
- __IO uint32_t TXPOWER; /*!< Output power. */
- __IO uint32_t MODE; /*!< Data rate and modulation. */
- __IO uint32_t PCNF0; /*!< Packet configuration 0. */
- __IO uint32_t PCNF1; /*!< Packet configuration 1. */
- __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
- __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
- __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
- __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
- __IO uint32_t TXADDRESS; /*!< Transmit address select. */
- __IO uint32_t RXADDRESSES; /*!< Receive address select. */
- __IO uint32_t CRCCNF; /*!< CRC configuration. */
- __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
- __IO uint32_t CRCINIT; /*!< CRC initial value. */
- __IO uint32_t TEST; /*!< Test features enable register. */
- __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
- __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED7;
- __I uint32_t STATE; /*!< Current radio state. */
- __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED8[2];
- __IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED9[39];
- __IO uint32_t DAB[8]; /*!< Device address base segment. */
- __IO uint32_t DAP[8]; /*!< Device address prefix. */
- __IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED10[56];
- __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
- __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
- __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
- __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
- __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED11[561];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================ UART ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40001000) RADIO Structure */
+ __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */
+ __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */
+ __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive
+ signal strength. */
+ __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */
+ __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */
+ __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */
+ __IM uint32_t RESERVED[55];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */
+ __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */
+ __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */
+ __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */
+ __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received
+ packet. */
+ __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last
+ received packet. */
+ __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete.
+ A new RSSI sample is ready for readout at
+ the RSSISAMPLE register. */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified
+ in BCC register. */
+ __IM uint32_t RESERVED2[53];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */
+ __IM uint32_t RESERVED3[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED4[61];
+ __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */
+ __IM uint32_t RESERVED5;
+ __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */
+ __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */
+ __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */
+ __IM uint32_t RESERVED6[60];
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */
+ __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */
+ __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */
+ __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */
+ __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */
+ __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */
+ __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */
+ __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */
+ __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */
+ __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */
+ __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */
+ __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */
+ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */
+ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */
+ __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */
+ __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */
+ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */
+ __IM uint32_t RESERVED7;
+ __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */
+ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */
+ __IM uint32_t RESERVED9[39];
+ __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */
+ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */
+ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */
+ __IM uint32_t RESERVED10[56];
+ __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */
+ __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */
+ __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */
+ __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */
+ __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */
+ __IM uint32_t RESERVED11[561];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+ * @brief Universal Asynchronous Receiver/Transmitter. (UART0)
*/
-typedef struct { /*!< UART Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
- __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
- __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
- __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
- __I uint32_t RESERVED0[3];
- __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
- __I uint32_t RESERVED1[56];
- __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
- __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
- __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
- __I uint32_t RESERVED2[4];
- __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
- __I uint32_t RESERVED3;
- __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
- __I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
- __I uint32_t RESERVED6[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED7[93];
- __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED8[31];
- __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
- __I uint32_t RESERVED9;
- __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
- __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
- __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
- __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
- __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
- Once read the character is consumed. If read when no character
- available, the UART will stop working. */
- __O uint32_t TXD; /*!< TXD register. */
- __I uint32_t RESERVED10;
- __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
- __I uint32_t RESERVED11[17];
- __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
- __I uint32_t RESERVED12[675];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================ SPI ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40002000) UART0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */
+ __IM uint32_t RESERVED5[46];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED7[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear
+ error. */
+ __IM uint32_t RESERVED8[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */
+ __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */
+ __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */
+ __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer
+ is displaced. Once read the character is
+ consumed. If read when no character available,
+ the UART will stop working. */
+ __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */
+ __IM uint32_t RESERVED11[17];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control
+ register. */
+ __IM uint32_t RESERVED12[675];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_UART_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief SPI master 0. (SPI)
+ * @brief SPI master 0. (SPI0)
*/
-typedef struct { /*!< SPI Structure */
- __I uint32_t RESERVED0[66];
- __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
- __I uint32_t RESERVED1[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[125];
- __IO uint32_t ENABLE; /*!< Enable SPI. */
- __I uint32_t RESERVED3;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __I uint32_t RESERVED4;
- __I uint32_t RXD; /*!< RX data. */
- __IO uint32_t TXD; /*!< TX data. */
- __I uint32_t RESERVED5;
- __IO uint32_t FREQUENCY; /*!< SPI frequency */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED7[681];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================ TWI ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40003000) SPI0 Structure */
+ __IM uint32_t RESERVED[66];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */
+ __IM uint32_t RESERVED1[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */
+ __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */
+ __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */
+ __IM uint32_t RESERVED7[681];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_SPI_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWI0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief Two-wire interface master 0. (TWI)
+ * @brief Two-wire interface master 0. (TWI0)
*/
-typedef struct { /*!< TWI Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
- __I uint32_t RESERVED1[2];
- __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
- __I uint32_t RESERVED2;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
- __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
- __I uint32_t RESERVED3[56];
- __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
- __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
- __I uint32_t RESERVED4[4];
- __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
- __I uint32_t RESERVED6[4];
- __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
- __I uint32_t RESERVED7[3];
- __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
- __I uint32_t RESERVED8[45];
- __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED9[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED10[110];
- __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED11[14];
- __IO uint32_t ENABLE; /*!< Enable two-wire master. */
- __I uint32_t RESERVED12;
- __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
- __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
- __I uint32_t RESERVED13[2];
- __I uint32_t RXD; /*!< RX data register. */
- __IO uint32_t TXD; /*!< TX data register. */
- __I uint32_t RESERVED14;
- __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
- __I uint32_t RESERVED15[24];
- __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
- __I uint32_t RESERVED16[668];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIS ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */
+ __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */
+ __IM uint32_t RESERVED8[45];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED10[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1
+ to clear error. */
+ __IM uint32_t RESERVED11[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */
+ __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */
+ __IM uint32_t RESERVED13[2];
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */
+ __IM uint32_t RESERVED15[24];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */
+ __IM uint32_t RESERVED16[668];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_TWI_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIS1 ================ */
+/* =========================================================================================================================== */
/**
- * @brief SPI slave 1. (SPIS)
+ * @brief SPI slave 1. (SPIS1)
*/
-typedef struct { /*!< SPIS Structure */
- __I uint32_t RESERVED0[9];
- __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
- __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
- __I uint32_t RESERVED1[54];
- __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
- __I uint32_t RESERVED2[2];
- __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
- __I uint32_t RESERVED3[5];
- __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
- __I uint32_t RESERVED4[53];
- __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
- __I uint32_t RESERVED5[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED6[61];
- __I uint32_t SEMSTAT; /*!< Semaphore status. */
- __I uint32_t RESERVED7[15];
- __IO uint32_t STATUS; /*!< Status from last transaction. */
- __I uint32_t RESERVED8[47];
- __IO uint32_t ENABLE; /*!< Enable SPIS. */
- __I uint32_t RESERVED9;
- __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
- __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
- __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
- __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
- __I uint32_t RESERVED10[7];
- __IO uint32_t RXDPTR; /*!< RX data pointer. */
- __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
- __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
- __I uint32_t RESERVED11;
- __IO uint32_t TXDPTR; /*!< TX data pointer. */
- __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
- __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
- __I uint32_t RESERVED12;
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED13;
- __IO uint32_t DEF; /*!< Default character. */
- __I uint32_t RESERVED14[24];
- __IO uint32_t ORC; /*!< Over-read character. */
- __I uint32_t RESERVED15[654];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIOTE ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */
+ __IM uint32_t RESERVED[9];
+ __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */
+ __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */
+ __IM uint32_t RESERVED1[54];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */
+ __IM uint32_t RESERVED4[53];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED6[61];
+ __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */
+ __IM uint32_t RESERVED8[47];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */
+ __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */
+ __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */
+ __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */
+ __IM uint32_t RESERVED10[7];
+ __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */
+ __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */
+ __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */
+ __IM uint32_t RESERVED11;
+ __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */
+ __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */
+ __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */
+ __IM uint32_t RESERVED14[24];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */
+ __IM uint32_t RESERVED15[654];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOTE ================ */
+/* =========================================================================================================================== */
/**
* @brief GPIO tasks and events. (GPIOTE)
*/
-typedef struct { /*!< GPIOTE Structure */
- __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
- __I uint32_t RESERVED1[27];
- __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
- __I uint32_t RESERVED2[97];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[129];
- __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
- __I uint32_t RESERVED4[695];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_GPIOTE_Type;
+typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
+ __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */
+ __IM uint32_t RESERVED1[27];
+ __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */
+ __IM uint32_t RESERVED2[97];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[129];
+ __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */
+ __IM uint32_t RESERVED4[695];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */
-/* ================================================================================ */
-/* ================ ADC ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ ADC ================ */
+/* =========================================================================================================================== */
/**
* @brief Analog to digital converter. (ADC)
*/
-typedef struct { /*!< ADC Structure */
- __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
- __O uint32_t TASKS_STOP; /*!< Stop ADC. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t BUSY; /*!< ADC busy register. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t ENABLE; /*!< ADC enable. */
- __IO uint32_t CONFIG; /*!< ADC configuration register. */
- __I uint32_t RESULT; /*!< Result of ADC conversion. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ADC_Type;
-
-
-/* ================================================================================ */
-/* ================ TIMER ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40007000) ADC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */
+ __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */
+ __IM uint32_t RESERVED4[700];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_ADC_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief Timer 0. (TIMER)
+ * @brief Timer 0. (TIMER0)
*/
-typedef struct { /*!< TIMER Structure */
- __O uint32_t TASKS_START; /*!< Start Timer. */
- __O uint32_t TASKS_STOP; /*!< Stop Timer. */
- __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
- __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
- __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
- __I uint32_t RESERVED0[11];
- __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[44];
- __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED4[126];
- __IO uint32_t MODE; /*!< Timer Mode selection. */
- __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
- __I uint32_t RESERVED5;
- __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
- clock frequency is divided by 2^SCALE. */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED7[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================ RTC ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */
+ __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */
+ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */
+ __IM uint32_t RESERVED[11];
+ __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */
+ __IM uint32_t RESERVED2[44];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */
+ __IM uint32_t RESERVED3[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED4[126];
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */
+ __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max
+ value 9). Source clock frequency is divided
+ by 2^SCALE. */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */
+ __IM uint32_t RESERVED7[683];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief Real time counter 0. (RTC)
+ * @brief Real time counter 0. (RTC0)
*/
-typedef struct { /*!< RTC Structure */
- __O uint32_t TASKS_START; /*!< Start RTC Counter. */
- __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
- __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
- __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
- __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
- __I uint32_t RESERVED1[14];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
- __I uint32_t RESERVED2[109];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[13];
- __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
- __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
- the value of EVTEN. */
- __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
- gives the value of EVTEN. */
- __I uint32_t RESERVED4[110];
- __I uint32_t COUNTER; /*!< Current COUNTER value. */
- __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
- Must be written when RTC is STOPed. */
- __I uint32_t RESERVED5[13];
- __IO uint32_t CC[4]; /*!< Capture/compare registers. */
- __I uint32_t RESERVED6[683];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================ TEMP ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */
+ __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */
+ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */
+ __IM uint32_t RESERVED1[14];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */
+ __IM uint32_t RESERVED2[109];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each
+ RTC event. */
+ __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of
+ this register gives the value of EVTEN. */
+ __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of
+ this register gives the value of EVTEN. */
+ __IM uint32_t RESERVED4[110];
+ __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+ Must be written when RTC is STOPed. */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */
+ __IM uint32_t RESERVED6[683];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_RTC_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TEMP ================ */
+/* =========================================================================================================================== */
/**
* @brief Temperature Sensor. (TEMP)
*/
-typedef struct { /*!< TEMP Structure */
- __O uint32_t TASKS_START; /*!< Start temperature measurement. */
- __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[127];
- __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
- __I uint32_t RESERVED3[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_TEMP_Type;
+typedef struct { /*!< (@ 0x4000C000) TEMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready
+ event. */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED2[127];
+ __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format,
+ 0.25 degC pecision. */
+ __IM uint32_t RESERVED3[700];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */
+
-/* ================================================================================ */
-/* ================ RNG ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ RNG ================ */
+/* =========================================================================================================================== */
/**
* @brief Random Number Generator. (RNG)
*/
-typedef struct { /*!< RNG Structure */
- __O uint32_t TASKS_START; /*!< Start the random number generator. */
- __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
- __I uint32_t RESERVED1[63];
- __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
- __I uint32_t RESERVED3[126];
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t VALUE; /*!< RNG random number. */
- __I uint32_t RESERVED4[700];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_RNG_Type;
-
-
-/* ================================================================================ */
-/* ================ ECB ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000D000) RNG Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE
+ register. */
+ __IM uint32_t RESERVED1[63];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */
+ __IM uint32_t RESERVED3[126];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */
+ __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */
+ __IM uint32_t RESERVED4[700];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_RNG_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ ECB ================ */
+/* =========================================================================================================================== */
/**
* @brief AES ECB Mode Encryption. (ECB)
*/
-typedef struct { /*!< ECB Structure */
- __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
- will not initiate a new encryption and the ERRORECB event will
- be triggered. */
- __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
- this will will trigger the ERRORECB event. */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
- __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
- error. */
- __I uint32_t RESERVED1[127];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
- __I uint32_t RESERVED3[701];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_ECB_Type;
-
-
-/* ================================================================================ */
-/* ================ AAR ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000E000) ECB Structure */
+ __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation
+ is running, this will not initiate a new
+ encryption and the ERRORECB event will be
+ triggered. */
+ __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation
+ is running, this will will trigger the ERRORECB
+ event. */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */
+ __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task
+ or due to an error. */
+ __IM uint32_t RESERVED1[127];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */
+ __IM uint32_t RESERVED3[701];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_ECB_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AAR ================ */
+/* =========================================================================================================================== */
/**
* @brief Accelerated Address Resolver. (AAR)
*/
-typedef struct { /*!< AAR Structure */
- __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
- data structure. */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
- __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
- __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t STATUS; /*!< Resolution status. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable AAR. */
- __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
- __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
- __I uint32_t RESERVED5;
- __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
- resolution. A minimum of 3 bytes must be reserved. */
- __I uint32_t RESERVED6[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================ CCM ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000F000) AAR Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
+ in the IRK data structure. */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */
+ __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */
+ __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */
+ __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data
+ structure. */
+ __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary
+ storage during resolution. A minimum of
+ 3 bytes must be reserved. */
+ __IM uint32_t RESERVED6[697];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_AAR_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CCM ================ */
+/* =========================================================================================================================== */
/**
* @brief AES CCM Mode Encryption. (CCM)
*/
-typedef struct { /*!< CCM Structure */
- __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
- itself when completed. */
- __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
- completed. */
- __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
- __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
- __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< CCM enable. */
- __IO uint32_t MODE; /*!< Operation mode. */
- __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
- __IO uint32_t INPTR; /*!< Pointer to the input packet. */
- __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
- resolution. A minimum of 43 bytes must be reserved. */
- __I uint32_t RESERVED5[697];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================ WDT ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000F000) CCM Structure */
+ __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation
+ will stop by itself when completed. */
+ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop
+ by itself when completed. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */
+ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and
+ NONCE vector. */
+ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */
+ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary
+ storage during resolution. A minimum of
+ 43 bytes must be reserved. */
+ __IM uint32_t RESERVED5[697];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_CCM_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WDT ================ */
+/* =========================================================================================================================== */
/**
* @brief Watchdog Timer. (WDT)
*/
-typedef struct { /*!< WDT Structure */
- __O uint32_t TASKS_START; /*!< Start the watchdog. */
- __I uint32_t RESERVED0[63];
- __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED2[61];
- __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
- __I uint32_t REQSTATUS; /*!< Request status. */
- __I uint32_t RESERVED3[63];
- __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
- __IO uint32_t RREN; /*!< Reload request enable. */
- __IO uint32_t CONFIG; /*!< Configuration register. */
- __I uint32_t RESERVED4[60];
- __O uint32_t RR[8]; /*!< Reload requests registers. */
- __I uint32_t RESERVED5[631];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_WDT_Type;
-
-
-/* ================================================================================ */
-/* ================ QDEC ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40010000) WDT Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */
+ __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock
+ cycles. */
+ __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */
+ __IM uint32_t RESERVED4[60];
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */
+ __IM uint32_t RESERVED5[631];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_WDT_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ QDEC ================ */
+/* =========================================================================================================================== */
/**
* @brief Rotary decoder. (QDEC)
*/
-typedef struct { /*!< QDEC Structure */
- __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
- __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
- __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
- and clears the ACC registers. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
- __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
- ACC register different than zero. */
- __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[125];
- __IO uint32_t ENABLE; /*!< Enable the QDEC. */
- __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
- __IO uint32_t SAMPLEPER; /*!< Sample period. */
- __I int32_t SAMPLE; /*!< Motion sample value. */
- __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
- __I int32_t ACC; /*!< Accumulated valid transitions register. */
- __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
- task. */
- __IO uint32_t PSELLED; /*!< Pin select for LED output. */
- __IO uint32_t PSELA; /*!< Pin select for phase A input. */
- __IO uint32_t PSELB; /*!< Pin select for phase B input. */
- __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
- __I uint32_t RESERVED4[5];
- __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
- __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
- __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
- task. */
- __I uint32_t RESERVED5[684];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================ LPCOMP ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40012000) QDEC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */
+ __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD
+ registers, and clears the ACC registers. */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */
+ __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC
+ register, and ACC register different than
+ zero. */
+ __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */
+ __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */
+ __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */
+ __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */
+ __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */
+ __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */
+ __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by
+ the TASKS_READCLEACC task. */
+ __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */
+ __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */
+ __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */
+ __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */
+ __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */
+ __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated
+ by the TASKS_READCLEACC task. */
+ __IM uint32_t RESERVED5[684];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LPCOMP ================ */
+/* =========================================================================================================================== */
/**
* @brief Low power comparator. (LPCOMP)
*/
-typedef struct { /*!< LPCOMP Structure */
- __O uint32_t TASKS_START; /*!< Start the comparator. */
- __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
- __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
- __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
- __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Result of last compare. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
- __IO uint32_t PSEL; /*!< Input pin select. */
- __IO uint32_t REFSEL; /*!< Reference select. */
- __IO uint32_t EXTREFSEL; /*!< External reference select. */
- __I uint32_t RESERVED5[4];
- __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
- __I uint32_t RESERVED6[694];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================ SWI ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */
+ __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */
+ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */
+ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */
+ __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */
+ __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */
+ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */
+ __IM uint32_t RESERVED5[4];
+ __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */
+ __IM uint32_t RESERVED6[694];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */
+} NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SWI ================ */
+/* =========================================================================================================================== */
/**
* @brief SW Interrupts. (SWI)
*/
-typedef struct { /*!< SWI Structure */
- __I uint32_t UNUSED; /*!< Unused. */
-} NRF_SWI_Type;
+typedef struct { /*!< (@ 0x40014000) SWI Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_SWI_Type; /*!< Size = 4 (0x4) */
-/* ================================================================================ */
-/* ================ NVMC ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ NVMC ================ */
+/* =========================================================================================================================== */
/**
* @brief Non Volatile Memory Controller. (NVMC)
*/
-typedef struct { /*!< NVMC Structure */
- __I uint32_t RESERVED0[256];
- __I uint32_t READY; /*!< Ready flag. */
- __I uint32_t RESERVED1[64];
- __IO uint32_t CONFIG; /*!< Configuration register. */
+typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
+ __IM uint32_t RESERVED[256];
+ __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */
+ __IM uint32_t RESERVED1[64];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */
union {
- __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
- __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
+ __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile
+ memory page. */
+ __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile
+ memory page. */
};
- __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
- __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
- __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
-} NRF_NVMC_Type;
+ __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */
+ __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile
+ memory page. */
+ __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration
+ Registers. */
+} NRF_NVMC_Type; /*!< Size = 1304 (0x518) */
+
-/* ================================================================================ */
-/* ================ PPI ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ PPI ================ */
+/* =========================================================================================================================== */
/**
* @brief PPI controller. (PPI)
*/
-typedef struct { /*!< PPI Structure */
- PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
- __I uint32_t RESERVED0[312];
- __IO uint32_t CHEN; /*!< Channel enable. */
- __IO uint32_t CHENSET; /*!< Channel enable set. */
- __IO uint32_t CHENCLR; /*!< Channel enable clear. */
- __I uint32_t RESERVED1;
- PPI_CH_Type CH[16]; /*!< PPI Channel. */
- __I uint32_t RESERVED2[156];
- __IO uint32_t CHG[4]; /*!< Channel group configuration. */
-} NRF_PPI_Type;
+typedef struct { /*!< (@ 0x4001F000) PPI Structure */
+ __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */
+ __IM uint32_t RESERVED[312];
+ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */
+ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */
+ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */
+ __IM uint32_t RESERVED1;
+ __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */
+ __IM uint32_t RESERVED2[156];
+ __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */
+} NRF_PPI_Type; /*!< Size = 2064 (0x810) */
+
-/* ================================================================================ */
-/* ================ FICR ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ FICR ================ */
+/* =========================================================================================================================== */
/**
* @brief Factory Information Configuration. (FICR)
*/
-typedef struct { /*!< FICR Structure */
- __I uint32_t RESERVED0[4];
- __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
- __I uint32_t CODESIZE; /*!< Code memory size in pages. */
- __I uint32_t RESERVED1[4];
- __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
- __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
- __I uint32_t RESERVED2;
- __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
+typedef struct { /*!< (@ 0x10000000) FICR Structure */
+ __IM uint32_t RESERVED[4];
+ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */
+ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */
+ __IM uint32_t RESERVED1[4];
+ __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */
+ __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */
+ __IM uint32_t RESERVED2;
+ __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */
union {
- __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
- kept for backward compatinility purposes. Use SIZERAMBLOCKS
- instead. */
- __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
+ __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */
+ __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes.
+ This name is kept for backward compatinility
+ purposes. Use SIZERAMBLOCKS instead. */
};
- __I uint32_t RESERVED3[5];
- __I uint32_t CONFIGID; /*!< Configuration identifier. */
- __I uint32_t DEVICEID[2]; /*!< Device identifier. */
- __I uint32_t RESERVED4[6];
- __I uint32_t ER[4]; /*!< Encryption root. */
- __I uint32_t IR[4]; /*!< Identity root. */
- __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
- __I uint32_t DEVICEADDR[2]; /*!< Device address. */
- __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
- __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
- mode. */
- __I uint32_t RESERVED5[10];
- __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
- mode. */
-} NRF_FICR_Type;
-
-
-/* ================================================================================ */
-/* ================ UICR ================ */
-/* ================================================================================ */
+ __IM uint32_t RESERVED3[5];
+ __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */
+ __IM uint32_t RESERVED4[6];
+ __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */
+ __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */
+ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */
+ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */
+ __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */
+ __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in
+ RADIO for NRF_1Mbit mode. */
+ __IM uint32_t RESERVED5[10];
+ __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in
+ RADIO for BLE_1Mbit mode. */
+} NRF_FICR_Type; /*!< Size = 256 (0x100) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UICR ================ */
+/* =========================================================================================================================== */
/**
* @brief User Information Configuration. (UICR)
*/
-typedef struct { /*!< UICR Structure */
- __IO uint32_t CLENR0; /*!< Length of code region 0. */
- __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
- __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
- __I uint32_t RESERVED0;
- __I uint32_t FWID; /*!< Firmware ID. */
+typedef struct { /*!< (@ 0x10001000) UICR Structure */
+ __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */
+ __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */
+ __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */
+ __IM uint32_t RESERVED;
+ __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */
union {
- __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
- __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
+ __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */
+ __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */
};
- __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
- __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
-} NRF_UICR_Type;
+ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */
+ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */
+} NRF_UICR_Type; /*!< Size = 256 (0x100) */
-/* ================================================================================ */
-/* ================ GPIO ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ GPIO ================ */
+/* =========================================================================================================================== */
/**
* @brief General purpose input and output. (GPIO)
*/
-typedef struct { /*!< GPIO Structure */
- __I uint32_t RESERVED0[321];
- __IO uint32_t OUT; /*!< Write GPIO port. */
- __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
- __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
- __I uint32_t IN; /*!< Read GPIO port. */
- __IO uint32_t DIR; /*!< Direction of GPIO pins. */
- __IO uint32_t DIRSET; /*!< DIR set register. */
- __IO uint32_t DIRCLR; /*!< DIR clear register. */
- __I uint32_t RESERVED1[120];
- __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
-} NRF_GPIO_Type;
-
-
-/* -------------------- End of section using anonymous unions ------------------- */
-#if defined(__CC_ARM)
+typedef struct { /*!< (@ 0x50000000) GPIO Structure */
+ __IM uint32_t RESERVED[321];
+ __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */
+ __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */
+ __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */
+ __IM uint32_t RESERVED1[120];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */
+} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_MPU_BASE 0x40000000UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_SPI0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_SPI1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
+#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_ADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
+#define NRF_LPCOMP_BASE 0x40013000UL
+#define NRF_SWI_BASE 0x40014000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_GPIO_BASE 0x50000000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
+#define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
+#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
+#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
+#define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
+#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
+#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
+#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
+#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE)
+#define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE)
+#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
+#define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
#pragma pop
-#elif defined(__ICCARM__)
+#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif defined(__GNUC__)
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
+#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
+#elif defined (__TASKING__)
#pragma warning restore
-#else
- #warning Not supported compiler type
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-
-#define NRF_POWER_BASE 0x40000000UL
-#define NRF_CLOCK_BASE 0x40000000UL
-#define NRF_MPU_BASE 0x40000000UL
-#define NRF_RADIO_BASE 0x40001000UL
-#define NRF_UART0_BASE 0x40002000UL
-#define NRF_SPI0_BASE 0x40003000UL
-#define NRF_TWI0_BASE 0x40003000UL
-#define NRF_SPI1_BASE 0x40004000UL
-#define NRF_TWI1_BASE 0x40004000UL
-#define NRF_SPIS1_BASE 0x40004000UL
-#define NRF_GPIOTE_BASE 0x40006000UL
-#define NRF_ADC_BASE 0x40007000UL
-#define NRF_TIMER0_BASE 0x40008000UL
-#define NRF_TIMER1_BASE 0x40009000UL
-#define NRF_TIMER2_BASE 0x4000A000UL
-#define NRF_RTC0_BASE 0x4000B000UL
-#define NRF_TEMP_BASE 0x4000C000UL
-#define NRF_RNG_BASE 0x4000D000UL
-#define NRF_ECB_BASE 0x4000E000UL
-#define NRF_AAR_BASE 0x4000F000UL
-#define NRF_CCM_BASE 0x4000F000UL
-#define NRF_WDT_BASE 0x40010000UL
-#define NRF_RTC1_BASE 0x40011000UL
-#define NRF_QDEC_BASE 0x40012000UL
-#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_SWI_BASE 0x40014000UL
-#define NRF_NVMC_BASE 0x4001E000UL
-#define NRF_PPI_BASE 0x4001F000UL
-#define NRF_FICR_BASE 0x10000000UL
-#define NRF_UICR_BASE 0x10001000UL
-#define NRF_GPIO_BASE 0x50000000UL
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-
-#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
-#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
-#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
-#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
-#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
-#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
-#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
-#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
-#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
-#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
-#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
-#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
-#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
-#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
-#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
-#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
-#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
-#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
-#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
-#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
-#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
-#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
-#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
-#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
-#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
-#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
-#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
-#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
-#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
-#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
-#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nrf51 */
-/** @} */ /* End of group Nordic Semiconductor */
-
#ifdef __cplusplus
}
#endif
+#endif /* NRF51_H */
-#endif /* nrf51_H */
+/** @} */ /* End of group nrf51 */
+
+/** @} */ /* End of group Nordic Semiconductor */
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
index ab1e93cd67..1b44852fc1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
@@ -6939,8 +6939,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
<version>522</version>
<description>SPI master 1.</description>
<baseAddress>0x40004000</baseAddress>
- <groupName>SPI</groupName>
- <size>32</size>
<access>read-write</access>
<interrupt>
<name>SPI1_TWI1</name>
@@ -6953,8 +6951,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
<version>522</version>
<description>Two-wire interface master 1.</description>
<baseAddress>0x40004000</baseAddress>
- <groupName>TWI</groupName>
- <size>32</size>
<access>read-write</access>
<alternatePeripheral>SPI1</alternatePeripheral>
<interrupt>
@@ -8874,8 +8870,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
<version>522</version>
<description>Timer 1.</description>
<baseAddress>0x40009000</baseAddress>
- <groupName>TIMER</groupName>
- <size>32</size>
<access>read-write</access>
<interrupt>
<name>TIMER1</name>
@@ -8888,8 +8882,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
<version>522</version>
<description>Timer 2.</description>
<baseAddress>0x4000A000</baseAddress>
- <groupName>TIMER</groupName>
- <size>32</size>
<access>read-write</access>
<interrupt>
<name>TIMER2</name>
@@ -11557,8 +11549,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
<version>522</version>
<description>Real time counter 1.</description>
<baseAddress>0x40011000</baseAddress>
- <groupName>RTC</groupName>
- <size>32</size>
<access>read-write</access>
<interrupt>
<name>RTC1</name>
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
index b48e187281..05a921be37 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
@@ -1,46 +1,40 @@
-
-/****************************************************************************************************//**
- * @file nrf52.h
- *
- * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
- * nrf52 from Nordic Semiconductor.
- *
- * @version V1
- * @date 8. March 2018
- *
- * @note Generated with SVDConv V2.81d
- * from CMSIS SVD File 'nrf52.svd' Version 1,
+/*
+ * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*
- * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- *
- *******************************************************************************************************/
+ * @file nrf52.h
+ * @brief CMSIS HeaderFile
+ * @version 1
+ * @date 06. June 2018
+ * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:38
+ * from File 'nrf52.svd',
+ * last modified on Wednesday, 06.06.2018 13:21:34
+ */
@@ -48,10 +42,12 @@
* @{
*/
+
/** @addtogroup nrf52
* @{
*/
+
#ifndef NRF52_H
#define NRF52_H
@@ -60,2032 +56,2386 @@ extern "C" {
#endif
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
- and No Match */
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
- related Fault */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */
- POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
- RADIO_IRQn = 1, /*!< 1 RADIO */
- UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
- SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
- SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
- NFCT_IRQn = 5, /*!< 5 NFCT */
- GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
- SAADC_IRQn = 7, /*!< 7 SAADC */
- TIMER0_IRQn = 8, /*!< 8 TIMER0 */
- TIMER1_IRQn = 9, /*!< 9 TIMER1 */
- TIMER2_IRQn = 10, /*!< 10 TIMER2 */
- RTC0_IRQn = 11, /*!< 11 RTC0 */
- TEMP_IRQn = 12, /*!< 12 TEMP */
- RNG_IRQn = 13, /*!< 13 RNG */
- ECB_IRQn = 14, /*!< 14 ECB */
- CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
- WDT_IRQn = 16, /*!< 16 WDT */
- RTC1_IRQn = 17, /*!< 17 RTC1 */
- QDEC_IRQn = 18, /*!< 18 QDEC */
- COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
- SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
- SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
- SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
- SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
- SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
- SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
- TIMER3_IRQn = 26, /*!< 26 TIMER3 */
- TIMER4_IRQn = 27, /*!< 27 TIMER4 */
- PWM0_IRQn = 28, /*!< 28 PWM0 */
- PDM_IRQn = 29, /*!< 29 PDM */
- MWU_IRQn = 32, /*!< 32 MWU */
- PWM1_IRQn = 33, /*!< 33 PWM1 */
- PWM2_IRQn = 34, /*!< 34 PWM2 */
- SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
- RTC2_IRQn = 36, /*!< 36 RTC2 */
- I2S_IRQn = 37, /*!< 37 I2S */
- FPU_IRQn = 38 /*!< 38 FPU */
-} IRQn_Type;
-
-
/** @addtogroup Configuration_of_CMSIS
* @{
*/
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
-#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-/** @} */ /* End of group Configuration_of_CMSIS */
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-#include "system_nrf52.h" /*!< nrf52 System */
+typedef enum {
+/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+ NFCT_IRQn = 5, /*!< 5 NFCT */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ SAADC_IRQn = 7, /*!< 7 SAADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
+ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
+ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
+ SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
+ SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
+ SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
+ SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
+ TIMER3_IRQn = 26, /*!< 26 TIMER3 */
+ TIMER4_IRQn = 27, /*!< 27 TIMER4 */
+ PWM0_IRQn = 28, /*!< 28 PWM0 */
+ PDM_IRQn = 29, /*!< 29 PDM */
+ MWU_IRQn = 32, /*!< 32 MWU */
+ PWM1_IRQn = 33, /*!< 33 PWM1 */
+ PWM2_IRQn = 34, /*!< 34 PWM2 */
+ SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
+ RTC2_IRQn = 36, /*!< 36 RTC2 */
+ I2S_IRQn = 37, /*!< 37 I2S */
+ FPU_IRQn = 38 /*!< 38 FPU */
+} IRQn_Type;
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_nrf52.h" /*!< nrf52 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
-#elif defined(__ICCARM__)
+#elif defined (__ICCARM__)
#pragma language=extended
-#elif defined(__GNUC__)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
#pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief FICR_INFO [INFO] (Device info)
+ */
typedef struct {
- __I uint32_t PART; /*!< Part code */
- __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */
- __I uint32_t PACKAGE; /*!< Package option */
- __I uint32_t RAM; /*!< RAM variant */
- __I uint32_t FLASH; /*!< Flash variant */
- __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */
-} FICR_INFO_Type;
+ __IM uint32_t PART; /*!< (@ 0x00000000) Part code */
+ __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production
+ configuration */
+ __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
+ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
+ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
+ __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */
+} FICR_INFO_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients)
+ */
typedef struct {
- __I uint32_t A0; /*!< Slope definition A0. */
- __I uint32_t A1; /*!< Slope definition A1. */
- __I uint32_t A2; /*!< Slope definition A2. */
- __I uint32_t A3; /*!< Slope definition A3. */
- __I uint32_t A4; /*!< Slope definition A4. */
- __I uint32_t A5; /*!< Slope definition A5. */
- __I uint32_t B0; /*!< y-intercept B0. */
- __I uint32_t B1; /*!< y-intercept B1. */
- __I uint32_t B2; /*!< y-intercept B2. */
- __I uint32_t B3; /*!< y-intercept B3. */
- __I uint32_t B4; /*!< y-intercept B4. */
- __I uint32_t B5; /*!< y-intercept B5. */
- __I uint32_t T0; /*!< Segment end T0. */
- __I uint32_t T1; /*!< Segment end T1. */
- __I uint32_t T2; /*!< Segment end T2. */
- __I uint32_t T3; /*!< Segment end T3. */
- __I uint32_t T4; /*!< Segment end T4. */
-} FICR_TEMP_Type;
+ __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */
+ __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */
+ __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */
+ __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */
+ __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */
+ __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */
+ __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */
+ __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */
+ __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */
+ __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */
+ __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */
+ __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */
+ __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */
+ __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */
+ __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */
+ __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */
+ __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */
+} FICR_TEMP_Type; /*!< Size = 68 (0x44) */
+
+/**
+ * @brief FICR_NFC [NFC] (Unspecified)
+ */
typedef struct {
- __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to
- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
- __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to
- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
- __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to
- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
- __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to
- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
-} FICR_NFC_Type;
+ __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST and NFCID1_LAST. */
+ __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read
+ these values to populate NFCID1_3RD_LAST,
+ NFCID1_2ND_LAST and NFCID1_LAST. */
+} FICR_NFC_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief POWER_RAM [RAM] (Unspecified)
+ */
typedef struct {
- __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */
- __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */
- __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */
- __I uint32_t RESERVED0;
-} POWER_RAM_Type;
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set
+ register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear
+ register */
+ __IM uint32_t RESERVED;
+} POWER_RAM_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief UARTE_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t RTS; /*!< Pin select for RTS signal */
- __IO uint32_t TXD; /*!< Pin select for TXD signal */
- __IO uint32_t CTS; /*!< Pin select for CTS signal */
- __IO uint32_t RXD; /*!< Pin select for RXD signal */
-} UARTE_PSEL_Type;
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */
+} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
-} UARTE_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
-} UARTE_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK */
- __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
- __IO uint32_t MISO; /*!< Pin select for MISO signal */
-} SPIM_PSEL_Type;
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} SPIM_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} SPIM_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIS_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK */
- __IO uint32_t MISO; /*!< Pin select for MISO signal */
- __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
- __IO uint32_t CSN; /*!< Pin select for CSN signal */
-} SPIS_PSEL_Type;
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */
+} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIS_RXD [RXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RXD data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */
-} SPIS_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
+} SPIS_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIS_TXD [TXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< TXD data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */
-} SPIS_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
+} SPIS_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief TWIM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCL; /*!< Pin select for SCL signal */
- __IO uint32_t SDA; /*!< Pin select for SDA signal */
-} TWIM_PSEL_Type;
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} TWIM_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} TWIM_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief TWIS_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCL; /*!< Pin select for SCL signal */
- __IO uint32_t SDA; /*!< Pin select for SDA signal */
-} TWIS_PSEL_Type;
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RXD Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */
-} TWIS_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
+} TWIS_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< TXD Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */
-} TWIS_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
+} TWIS_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPI_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK */
- __IO uint32_t MOSI; /*!< Pin select for MOSI */
- __IO uint32_t MISO; /*!< Pin select for MISO */
-} SPI_PSEL_Type;
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */
+} SPI_PSEL_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified)
+ */
typedef struct {
- __IO uint32_t RX; /*!< Result of last incoming frames */
-} NFCT_FRAMESTATUS_Type;
+ __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */
+} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief NFCT_TXD [TXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */
- __IO uint32_t AMOUNT; /*!< Size of outgoing frame */
-} NFCT_TXD_Type;
+ __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */
+ __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */
+} NFCT_TXD_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief NFCT_RXD [RXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */
- __I uint32_t AMOUNT; /*!< Size of last incoming frame */
-} NFCT_RXD_Type;
+ __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */
+} NFCT_RXD_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified)
+ */
typedef struct {
- __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
- __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
-} SAADC_EVENTS_CH_Type;
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal
+ or above CH[0].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal
+ or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief SAADC_CH [CH] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */
- __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */
- __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */
- __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
- a channel */
-} SAADC_CH_Type;
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection
+ for CH[0] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection
+ for CH[0] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for
+ CH[0] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event
+ monitoring a channel */
+} SAADC_CH_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */
- __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */
-} SAADC_RESULT_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last
+ START */
+} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief QDEC_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t LED; /*!< Pin select for LED signal */
- __IO uint32_t A; /*!< Pin select for A signal */
- __IO uint32_t B; /*!< Pin select for B signal */
-} QDEC_PSEL_Type;
+ __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */
+ __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */
+ __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */
+} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief PWM_SEQ [SEQ] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of this
- sequence */
- __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in this
- sequence */
- __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between
- samples loaded into compare register */
- __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */
- __I uint32_t RESERVED1[4];
-} PWM_SEQ_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in
+ Data RAM of this sequence */
+ __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty
+ cycles) in this sequence */
+ __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional
+ PWM periods between samples loaded into
+ compare register */
+ __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the
+ sequence */
+ __IM uint32_t RESERVED[4];
+} PWM_SEQ_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief PWM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
- 0 */
-} PWM_PSEL_Type;
+ __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select
+ for PWM channel 0 */
+} PWM_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief PDM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */
- __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */
-} PDM_PSEL_Type;
+ __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */
+ __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */
+} PDM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PDM_SAMPLE [SAMPLE] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */
- __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */
-} PDM_SAMPLE_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with
+ EasyDMA */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
+ mode */
+} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
+ */
typedef struct {
- __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */
- __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */
-} PPI_TASKS_CHG_Type;
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group
+ 0 */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group
+ 0 */
+} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_CH [CH] (PPI Channel)
+ */
typedef struct {
- __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */
- __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
-} PPI_CH_Type;
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */
+} PPI_CH_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_FORK [FORK] (Fork)
+ */
typedef struct {
- __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
-} PPI_FORK_Type;
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */
+} PPI_FORK_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified)
+ */
typedef struct {
- __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */
- __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */
-} MWU_EVENTS_REGION_Type;
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region
+ 0 detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region
+ 0 detected */
+} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified)
+ */
typedef struct {
- __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0
- detected */
- __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */
-} MWU_EVENTS_PREGION_Type;
+ __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral
+ region 0 detected */
+ __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral
+ region 0 detected */
+} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief MWU_PERREGION [PERREGION] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region
- 0, write access detected while corresponding subregion was enabled
- for watching */
- __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region
- 0, read access detected while corresponding subregion was enabled
- for watching */
-} MWU_PERREGION_Type;
+ __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt
+ in region 0, write access detected while
+ corresponding subregion was enabled for
+ watching */
+ __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt
+ in region 0, read access detected while
+ corresponding subregion was enabled for
+ watching */
+} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief MWU_REGION [REGION] (Unspecified)
+ */
typedef struct {
- __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */
- __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */
- __I uint32_t RESERVED2[2];
-} MWU_REGION_Type;
+ __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region
+ 0 */
+ __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region
+ 0 */
+ __IM uint32_t RESERVED[2];
+} MWU_REGION_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief MWU_PREGION [PREGION] (Unspecified)
+ */
typedef struct {
- __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */
- __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */
- __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */
- __I uint32_t RESERVED3;
-} MWU_PREGION_Type;
+ __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */
+ __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */
+ __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region
+ 0 */
+ __IM uint32_t RESERVED;
+} MWU_PREGION_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief I2S_CONFIG [CONFIG] (Unspecified)
+ */
typedef struct {
- __IO uint32_t MODE; /*!< I2S mode. */
- __IO uint32_t RXEN; /*!< Reception (RX) enable. */
- __IO uint32_t TXEN; /*!< Transmission (TX) enable. */
- __IO uint32_t MCKEN; /*!< Master clock generator enable. */
- __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */
- __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */
- __IO uint32_t SWIDTH; /*!< Sample width. */
- __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */
- __IO uint32_t FORMAT; /*!< Frame format. */
- __IO uint32_t CHANNELS; /*!< Enable channels. */
-} I2S_CONFIG_Type;
+ __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */
+ __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */
+ __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */
+ __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */
+ __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */
+ __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */
+ __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */
+ __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */
+ __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */
+ __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */
+} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */
+
+/**
+ * @brief I2S_RXD [RXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Receive buffer RAM start address. */
-} I2S_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */
+} I2S_RXD_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief I2S_TXD [TXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */
-} I2S_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */
+} I2S_TXD_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief I2S_RXTXD [RXTXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */
-} I2S_RXTXD_Type;
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */
+} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */
+
+/**
+ * @brief I2S_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t MCK; /*!< Pin select for MCK signal. */
- __IO uint32_t SCK; /*!< Pin select for SCK signal. */
- __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */
- __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */
- __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */
-} I2S_PSEL_Type;
+ __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */
+ __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */
+ __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */
+ __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */
+ __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */
+} I2S_PSEL_Type; /*!< Size = 20 (0x14) */
-/* ================================================================================ */
-/* ================ FICR ================ */
-/* ================================================================================ */
+/** @} */ /* End of group Device_Peripheral_clusters */
-/**
- * @brief Factory Information Configuration Registers (FICR)
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
*/
-typedef struct { /*!< FICR Structure */
- __I uint32_t RESERVED0[4];
- __I uint32_t CODEPAGESIZE; /*!< Code memory page size */
- __I uint32_t CODESIZE; /*!< Code memory size */
- __I uint32_t RESERVED1[18];
- __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */
- __I uint32_t RESERVED2[6];
- __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */
- __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */
- __I uint32_t DEVICEADDRTYPE; /*!< Device address type */
- __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */
- __I uint32_t RESERVED3[21];
- FICR_INFO_Type INFO; /*!< Device info */
- __I uint32_t RESERVED4[185];
- FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */
- __I uint32_t RESERVED5[2];
- FICR_NFC_Type NFC; /*!< Unspecified */
-} NRF_FICR_Type;
-/* ================================================================================ */
-/* ================ UICR ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ FICR ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Factory Information Configuration Registers (FICR)
+ */
+
+typedef struct { /*!< (@ 0x10000000) FICR Structure */
+ __IM uint32_t RESERVED[4];
+ __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */
+ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */
+ __IM uint32_t RESERVED1[18];
+ __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */
+ __IM uint32_t RESERVED2[6];
+ __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word
+ 0 */
+ __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word
+ 0 */
+ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */
+ __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */
+ __IM uint32_t RESERVED3[21];
+ __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */
+ __IM uint32_t RESERVED4[185];
+ __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization
+ coefficients */
+ __IM uint32_t RESERVED5[2];
+ __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */
+} NRF_FICR_Type; /*!< Size = 1120 (0x460) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UICR ================ */
+/* =========================================================================================================================== */
/**
* @brief User Information Configuration Registers (UICR)
*/
-typedef struct { /*!< UICR Structure */
- __IO uint32_t UNUSED0; /*!< Unspecified */
- __IO uint32_t UNUSED1; /*!< Unspecified */
- __IO uint32_t UNUSED2; /*!< Unspecified */
- __I uint32_t RESERVED0;
- __IO uint32_t UNUSED3; /*!< Unspecified */
- __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */
- __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */
- __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */
- __I uint32_t RESERVED1[64];
- __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see
- POWER chapter for details) */
- __IO uint32_t APPROTECT; /*!< Access Port protection */
- __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna
- or GPIO */
-} NRF_UICR_Type;
+typedef struct { /*!< (@ 0x10001000) UICR Structure */
+ __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */
+ __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */
+ __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */
+ __IM uint32_t RESERVED;
+ __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */
+ __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic
+ firmware design */
+ __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic
+ hardware design */
+ __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */
+ __IM uint32_t RESERVED1[64];
+ __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET
+ function (see POWER chapter for details) */
+ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */
+ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality:
+ NFC antenna or GPIO */
+} NRF_UICR_Type; /*!< Size = 528 (0x210) */
+
-/* ================================================================================ */
-/* ================ BPROT ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ BPROT ================ */
+/* =========================================================================================================================== */
/**
* @brief Block Protect (BPROT)
*/
-typedef struct { /*!< BPROT Structure */
- __I uint32_t RESERVED0[384];
- __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */
- __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */
- __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */
- __IO uint32_t UNUSED0; /*!< Unspecified */
- __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */
- __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */
-} NRF_BPROT_Type;
+typedef struct { /*!< (@ 0x40000000) BPROT Structure */
+ __IM uint32_t RESERVED[384];
+ __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */
+ __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */
+ __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface
+ mode */
+ __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */
+ __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */
+ __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */
+} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */
-/* ================================================================================ */
-/* ================ POWER ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ POWER ================ */
+/* =========================================================================================================================== */
/**
* @brief Power control (POWER)
*/
-typedef struct { /*!< POWER Structure */
- __I uint32_t RESERVED0[30];
- __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */
- __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */
- __I uint32_t RESERVED1[34];
- __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */
- __I uint32_t RESERVED2[2];
- __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */
- __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */
- __I uint32_t RESERVED3[122];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED4[61];
- __IO uint32_t RESETREAS; /*!< Reset reason */
- __I uint32_t RESERVED5[9];
- __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */
- __I uint32_t RESERVED6[53];
- __O uint32_t SYSTEMOFF; /*!< System OFF register */
- __I uint32_t RESERVED7[3];
- __IO uint32_t POFCON; /*!< Power failure comparator configuration */
- __I uint32_t RESERVED8[2];
- __IO uint32_t GPREGRET; /*!< General purpose retention register */
- __IO uint32_t GPREGRET2; /*!< General purpose retention register */
- __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is
- retained) */
- __I uint32_t RESERVED9[11];
- __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is
- retained) */
- __I uint32_t RESERVED10[8];
- __IO uint32_t DCDCEN; /*!< DC/DC enable register */
- __I uint32_t RESERVED11[225];
- POWER_RAM_Type RAM[8]; /*!< Unspecified */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================ CLOCK ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40000000) POWER Structure */
+ __IM uint32_t RESERVED[30];
+ __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */
+ __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */
+ __IM uint32_t RESERVED1[34];
+ __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */
+ __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */
+ __IM uint32_t RESERVED3[122];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[61];
+ __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */
+ __IM uint32_t RESERVED5[9];
+ __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */
+ __IM uint32_t RESERVED6[53];
+ __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */
+ __IM uint32_t RESERVED8[2];
+ __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */
+ __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */
+ __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this
+ register is retained) */
+ __IM uint32_t RESERVED9[11];
+ __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this
+ register is retained) */
+ __IM uint32_t RESERVED10[8];
+ __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */
+ __IM uint32_t RESERVED11[225];
+ __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */
+} NRF_POWER_Type; /*!< Size = 2432 (0x980) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ CLOCK ================ */
+/* =========================================================================================================================== */
/**
* @brief Clock control (CLOCK)
*/
-typedef struct { /*!< CLOCK Structure */
- __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */
- __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */
- __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */
- __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */
- __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */
- __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */
- __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */
- __I uint32_t RESERVED0[57];
- __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */
- __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */
- __I uint32_t RESERVED1;
- __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */
- __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */
- __I uint32_t RESERVED2[124];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[63];
- __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */
- __I uint32_t HFCLKSTAT; /*!< HFCLK status */
- __I uint32_t RESERVED4;
- __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */
- __I uint32_t LFCLKSTAT; /*!< LFCLK status */
- __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
- __I uint32_t RESERVED5[62];
- __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
- __I uint32_t RESERVED6[7];
- __IO uint32_t CTIV; /*!< Calibration timer interval */
- __I uint32_t RESERVED7[8];
- __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================ RADIO ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40000000) CLOCK Structure */
+ __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */
+ __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */
+ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */
+ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */
+ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */
+ __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */
+ __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */
+ __IM uint32_t RESERVED[57];
+ __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */
+ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */
+ __IM uint32_t RESERVED1;
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */
+ __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */
+ __IM uint32_t RESERVED2[124];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[63];
+ __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been
+ triggered */
+ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been
+ triggered */
+ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */
+ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART
+ task was triggered */
+ __IM uint32_t RESERVED5[62];
+ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */
+ __IM uint32_t RESERVED6[7];
+ __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */
+ __IM uint32_t RESERVED7[8];
+ __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */
+} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RADIO ================ */
+/* =========================================================================================================================== */
/**
* @brief 2.4 GHz Radio (RADIO)
*/
-typedef struct { /*!< RADIO Structure */
- __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */
- __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */
- __O uint32_t TASKS_START; /*!< Start RADIO */
- __O uint32_t TASKS_STOP; /*!< Stop RADIO */
- __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */
- __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal
- strength. */
- __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */
- __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */
- __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */
- __I uint32_t RESERVED0[55];
- __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */
- __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */
- __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */
- __IO uint32_t EVENTS_END; /*!< Packet sent or received */
- __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */
- __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */
- __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */
- __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */
- __I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */
- __I uint32_t RESERVED2;
- __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */
- __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */
- __I uint32_t RESERVED3[50];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED4[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED5[61];
- __I uint32_t CRCSTATUS; /*!< CRC status */
- __I uint32_t RESERVED6;
- __I uint32_t RXMATCH; /*!< Received address */
- __I uint32_t RXCRC; /*!< CRC field of previously received packet */
- __I uint32_t DAI; /*!< Device address match index */
- __I uint32_t RESERVED7[60];
- __IO uint32_t PACKETPTR; /*!< Packet pointer */
- __IO uint32_t FREQUENCY; /*!< Frequency */
- __IO uint32_t TXPOWER; /*!< Output power */
- __IO uint32_t MODE; /*!< Data rate and modulation */
- __IO uint32_t PCNF0; /*!< Packet configuration register 0 */
- __IO uint32_t PCNF1; /*!< Packet configuration register 1 */
- __IO uint32_t BASE0; /*!< Base address 0 */
- __IO uint32_t BASE1; /*!< Base address 1 */
- __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */
- __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */
- __IO uint32_t TXADDRESS; /*!< Transmit address select */
- __IO uint32_t RXADDRESSES; /*!< Receive address select */
- __IO uint32_t CRCCNF; /*!< CRC configuration */
- __IO uint32_t CRCPOLY; /*!< CRC polynomial */
- __IO uint32_t CRCINIT; /*!< CRC initial value */
- __IO uint32_t UNUSED0; /*!< Unspecified */
- __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */
- __I uint32_t RSSISAMPLE; /*!< RSSI sample */
- __I uint32_t RESERVED8;
- __I uint32_t STATE; /*!< Current radio state */
- __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */
- __I uint32_t RESERVED9[2];
- __IO uint32_t BCC; /*!< Bit counter compare */
- __I uint32_t RESERVED10[39];
- __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */
- __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */
- __IO uint32_t DACNF; /*!< Device address match configuration */
- __I uint32_t RESERVED11[3];
- __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */
- __I uint32_t RESERVED12[618];
- __IO uint32_t POWER; /*!< Peripheral power control */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================ UARTE ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief UART with EasyDMA (UARTE)
- */
-
-typedef struct { /*!< UARTE Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
- __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
- __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
- __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
- __I uint32_t RESERVED0[7];
- __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */
- __I uint32_t RESERVED1[52];
- __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
- __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
- __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to
- Data RAM) */
- __I uint32_t RESERVED2;
- __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */
- __I uint32_t RESERVED3[2];
- __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
- __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */
- __IO uint32_t EVENTS_ERROR; /*!< Error detected */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */
- __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */
- __I uint32_t RESERVED6;
- __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */
- __I uint32_t RESERVED7[41];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED8[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED9[93];
- __IO uint32_t ERRORSRC; /*!< Error source */
- __I uint32_t RESERVED10[31];
- __IO uint32_t ENABLE; /*!< Enable UART */
- __I uint32_t RESERVED11;
- UARTE_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED12[3];
- __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */
- __I uint32_t RESERVED13[3];
- UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */
- __I uint32_t RESERVED14;
- UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */
- __I uint32_t RESERVED15[7];
- __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
-} NRF_UARTE_Type;
-
-
-/* ================================================================================ */
-/* ================ UART ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Universal Asynchronous Receiver/Transmitter (UART)
- */
-
-typedef struct { /*!< UART Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
- __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
- __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
- __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
- __I uint32_t RESERVED0[3];
- __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */
- __I uint32_t RESERVED1[56];
- __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
- __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
- __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */
- __I uint32_t RESERVED2[4];
- __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
- __I uint32_t RESERVED3;
- __IO uint32_t EVENTS_ERROR; /*!< Error detected */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
- __I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED6[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED7[93];
- __IO uint32_t ERRORSRC; /*!< Error source */
- __I uint32_t RESERVED8[31];
- __IO uint32_t ENABLE; /*!< Enable UART */
- __I uint32_t RESERVED9;
- __IO uint32_t PSELRTS; /*!< Pin select for RTS */
- __IO uint32_t PSELTXD; /*!< Pin select for TXD */
- __IO uint32_t PSELCTS; /*!< Pin select for CTS */
- __IO uint32_t PSELRXD; /*!< Pin select for RXD */
- __I uint32_t RXD; /*!< RXD register */
- __O uint32_t TXD; /*!< TXD register */
- __I uint32_t RESERVED10;
- __IO uint32_t BAUDRATE; /*!< Baud rate */
- __I uint32_t RESERVED11[17];
- __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
- */
-
-typedef struct { /*!< SPIM Structure */
- __I uint32_t RESERVED0[4];
- __O uint32_t TASKS_START; /*!< Start SPI transaction */
- __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */
- __I uint32_t RESERVED1;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */
- __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */
- __I uint32_t RESERVED2[56];
- __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */
- __I uint32_t RESERVED3[2];
- __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
- __I uint32_t RESERVED4;
- __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */
- __I uint32_t RESERVED6[10];
- __IO uint32_t EVENTS_STARTED; /*!< Transaction started */
- __I uint32_t RESERVED7[44];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED8[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED9[125];
- __IO uint32_t ENABLE; /*!< Enable SPIM */
- __I uint32_t RESERVED10;
- SPIM_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED11[4];
- __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */
- __I uint32_t RESERVED12[3];
- SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
- SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
- __IO uint32_t CONFIG; /*!< Configuration register */
- __I uint32_t RESERVED13[26];
- __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read
- of the TXD buffer. */
-} NRF_SPIM_Type;
-
-
-/* ================================================================================ */
-/* ================ SPIS ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief SPI Slave 0 (SPIS)
- */
-
-typedef struct { /*!< SPIS Structure */
- __I uint32_t RESERVED0[9];
- __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */
- __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */
- __I uint32_t RESERVED1[54];
- __IO uint32_t EVENTS_END; /*!< Granted transaction completed */
- __I uint32_t RESERVED2[2];
- __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
- __I uint32_t RESERVED3[5];
- __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */
- __I uint32_t RESERVED4[53];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED5[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED6[61];
- __I uint32_t SEMSTAT; /*!< Semaphore status register */
- __I uint32_t RESERVED7[15];
- __IO uint32_t STATUS; /*!< Status from last transaction */
- __I uint32_t RESERVED8[47];
- __IO uint32_t ENABLE; /*!< Enable SPI slave */
- __I uint32_t RESERVED9;
- SPIS_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED10[7];
- SPIS_RXD_Type RXD; /*!< Unspecified */
- __I uint32_t RESERVED11;
- SPIS_TXD_Type TXD; /*!< Unspecified */
- __I uint32_t RESERVED12;
- __IO uint32_t CONFIG; /*!< Configuration register */
- __I uint32_t RESERVED13;
- __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored
- transaction. */
- __I uint32_t RESERVED14[24];
- __IO uint32_t ORC; /*!< Over-read character */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================ TWIM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
- */
-
-typedef struct { /*!< TWIM Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
- __I uint32_t RESERVED1[2];
- __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is
- not suspended. */
- __I uint32_t RESERVED2;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
- __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
- __I uint32_t RESERVED3[56];
- __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_ERROR; /*!< TWI error */
- __I uint32_t RESERVED5[8];
- __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been
- issued, TWI traffic is now suspended. */
- __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
- __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
- __I uint32_t RESERVED6[2];
- __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */
- __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */
- __I uint32_t RESERVED7[39];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED8[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED9[110];
- __IO uint32_t ERRORSRC; /*!< Error source */
- __I uint32_t RESERVED10[14];
- __IO uint32_t ENABLE; /*!< Enable TWIM */
- __I uint32_t RESERVED11;
- TWIM_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED12[5];
- __IO uint32_t FREQUENCY; /*!< TWI frequency */
- __I uint32_t RESERVED13[3];
- TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
- TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
- __I uint32_t RESERVED14[13];
- __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
-} NRF_TWIM_Type;
-
-
-/* ================================================================================ */
-/* ================ TWIS ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
- */
-
-typedef struct { /*!< TWIS Structure */
- __I uint32_t RESERVED0[5];
- __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
- __I uint32_t RESERVED1;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
- __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
- __I uint32_t RESERVED2[3];
- __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */
- __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */
- __I uint32_t RESERVED3[51];
- __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
- __I uint32_t RESERVED4[7];
- __IO uint32_t EVENTS_ERROR; /*!< TWI error */
- __I uint32_t RESERVED5[9];
- __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
- __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
- __I uint32_t RESERVED6[4];
- __IO uint32_t EVENTS_WRITE; /*!< Write command received */
- __IO uint32_t EVENTS_READ; /*!< Read command received */
- __I uint32_t RESERVED7[37];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED8[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED9[113];
- __IO uint32_t ERRORSRC; /*!< Error source */
- __I uint32_t MATCH; /*!< Status register indicating which address had a match */
- __I uint32_t RESERVED10[10];
- __IO uint32_t ENABLE; /*!< Enable TWIS */
- __I uint32_t RESERVED11;
- TWIS_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED12[9];
- TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */
- __I uint32_t RESERVED13;
- TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */
- __I uint32_t RESERVED14[14];
- __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */
- __I uint32_t RESERVED15;
- __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */
- __I uint32_t RESERVED16[10];
- __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read
- of the transmit buffer. */
-} NRF_TWIS_Type;
-
-
-/* ================================================================================ */
-/* ================ SPI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Serial Peripheral Interface 0 (SPI)
- */
-
-typedef struct { /*!< SPI Structure */
- __I uint32_t RESERVED0[66];
- __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */
- __I uint32_t RESERVED1[126];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[125];
- __IO uint32_t ENABLE; /*!< Enable SPI */
- __I uint32_t RESERVED3;
- SPI_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED4;
- __I uint32_t RXD; /*!< RXD register */
- __IO uint32_t TXD; /*!< TXD register */
- __I uint32_t RESERVED5;
- __IO uint32_t FREQUENCY; /*!< SPI frequency */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CONFIG; /*!< Configuration register */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================ TWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief I2C compatible Two-Wire Interface 0 (TWI)
- */
-
-typedef struct { /*!< TWI Structure */
- __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
- __I uint32_t RESERVED1[2];
- __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
- __I uint32_t RESERVED2;
- __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
- __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
- __I uint32_t RESERVED3[56];
- __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
- __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */
- __I uint32_t RESERVED4[4];
- __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */
- __I uint32_t RESERVED5;
- __IO uint32_t EVENTS_ERROR; /*!< TWI error */
- __I uint32_t RESERVED6[4];
- __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or
- received */
- __I uint32_t RESERVED7[3];
- __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */
- __I uint32_t RESERVED8[45];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED9[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED10[110];
- __IO uint32_t ERRORSRC; /*!< Error source */
- __I uint32_t RESERVED11[14];
- __IO uint32_t ENABLE; /*!< Enable TWI */
- __I uint32_t RESERVED12;
- __IO uint32_t PSELSCL; /*!< Pin select for SCL */
- __IO uint32_t PSELSDA; /*!< Pin select for SDA */
- __I uint32_t RESERVED13[2];
- __I uint32_t RXD; /*!< RXD register */
- __IO uint32_t TXD; /*!< TXD register */
- __I uint32_t RESERVED14;
- __IO uint32_t FREQUENCY; /*!< TWI frequency */
- __I uint32_t RESERVED15[24];
- __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================ NFCT ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40001000) RADIO Structure */
+ __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */
+ __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */
+ __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of
+ the receive signal strength. */
+ __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */
+ __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */
+ __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */
+ __IM uint32_t RESERVED[55];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */
+ __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */
+ __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */
+ __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */
+ __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received
+ packet */
+ __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last
+ received packet */
+ __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */
+ __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */
+ __IM uint32_t RESERVED3[50];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED4[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED5[61];
+ __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */
+ __IM uint32_t RESERVED6;
+ __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */
+ __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */
+ __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */
+ __IM uint32_t RESERVED7[60];
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */
+ __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */
+ __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */
+ __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */
+ __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */
+ __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */
+ __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */
+ __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */
+ __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */
+ __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */
+ __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */
+ __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */
+ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */
+ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */
+ __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */
+ __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */
+ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */
+ __IM uint32_t RESERVED8;
+ __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */
+ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */
+ __IM uint32_t RESERVED9[2];
+ __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */
+ __IM uint32_t RESERVED10[39];
+ __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base
+ segment 0 */
+ __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix
+ 0 */
+ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */
+ __IM uint32_t RESERVED11[3];
+ __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */
+ __IM uint32_t RESERVED12[618];
+ __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */
+} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UARTE0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief UART with EasyDMA (UARTE0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[7];
+ __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */
+ __IM uint32_t RESERVED1[52];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet
+ transferred to Data RAM) */
+ __IM uint32_t RESERVED2;
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */
+ __IM uint32_t RESERVED6;
+ __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */
+ __IM uint32_t RESERVED7[41];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
+ __IM uint32_t RESERVED10[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED11;
+ __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[3];
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source
+ selected. */
+ __IM uint32_t RESERVED13[3];
+ __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED14;
+ __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED15[7];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ UART0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Universal Asynchronous Receiver/Transmitter (UART0)
+ */
+
+typedef struct { /*!< (@ 0x40002000) UART0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */
+ __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */
+ __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */
+ __IM uint32_t RESERVED1[56];
+ __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */
+ __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */
+ __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */
+ __IM uint32_t RESERVED2[4];
+ __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */
+ __IM uint32_t RESERVED5[46];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED6[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED7[93];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */
+ __IM uint32_t RESERVED8[31];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
+ __IM uint32_t RESERVED9;
+ __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */
+ __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */
+ __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */
+ __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED10;
+ __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */
+ __IM uint32_t RESERVED11[17];
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */
+} NRF_UART_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */
+ __IM uint32_t RESERVED6[10];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */
+ __IM uint32_t RESERVED7[44];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED8[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */
+ __IM uint32_t RESERVED10;
+ __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED11[4];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK
+ source selected. */
+ __IM uint32_t RESERVED12[3];
+ __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED13[26];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in
+ case and over-read of the TXD buffer. */
+} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief SPI Slave 0 (SPIS0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */
+ __IM uint32_t RESERVED[9];
+ __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */
+ __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave
+ to acquire it */
+ __IM uint32_t RESERVED1[54];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */
+ __IM uint32_t RESERVED2[2];
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */
+ __IM uint32_t RESERVED4[53];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED6[61];
+ __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */
+ __IM uint32_t RESERVED7[15];
+ __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */
+ __IM uint32_t RESERVED8[47];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */
+ __IM uint32_t RESERVED9;
+ __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED10[7];
+ __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */
+ __IM uint32_t RESERVED11;
+ __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+ __IM uint32_t RESERVED13;
+ __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case
+ of an ignored transaction. */
+ __IM uint32_t RESERVED14[24];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */
+} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the
+ TWI master is not suspended. */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND
+ task has been issued, TWI traffic is now
+ suspended. */
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[2];
+ __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */
+ __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last
+ byte */
+ __IM uint32_t RESERVED7[39];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED10[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */
+ __IM uint32_t RESERVED11;
+ __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[5];
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */
+ __IM uint32_t RESERVED13[3];
+ __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED14[13];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWIS0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */
+ __IM uint32_t RESERVED[5];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED2[3];
+ __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */
+ __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */
+ __IM uint32_t RESERVED3[51];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IM uint32_t RESERVED4[7];
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED5[9];
+ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
+ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */
+ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */
+ __IM uint32_t RESERVED7[37];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED8[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED9[113];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */
+ __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had
+ a match */
+ __IM uint32_t RESERVED10[10];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */
+ __IM uint32_t RESERVED11;
+ __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED12[9];
+ __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */
+ __IM uint32_t RESERVED13;
+ __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */
+ __IM uint32_t RESERVED14[14];
+ __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address
+ 0 */
+ __IM uint32_t RESERVED15;
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match
+ mechanism */
+ __IM uint32_t RESERVED16[10];
+ __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case
+ of an over-read of the transmit buffer. */
+} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SPI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Serial Peripheral Interface 0 (SPI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) SPI0 Structure */
+ __IM uint32_t RESERVED[66];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */
+ __IM uint32_t RESERVED1[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */
+ __IM uint32_t RESERVED3;
+ __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */
+ __IM uint32_t RESERVED4;
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */
+} NRF_SPI_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TWI0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief I2C compatible Two-Wire Interface 0 (TWI0)
+ */
+
+typedef struct { /*!< (@ 0x40003000) TWI0 Structure */
+ __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */
+ __IM uint32_t RESERVED1[2];
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */
+ __IM uint32_t RESERVED2;
+ __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */
+ __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */
+ __IM uint32_t RESERVED3[56];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */
+ __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
+ __IM uint32_t RESERVED6[4];
+ __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte
+ that is sent or received */
+ __IM uint32_t RESERVED7[3];
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */
+ __IM uint32_t RESERVED8[45];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED9[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED10[110];
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */
+ __IM uint32_t RESERVED11[14];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */
+ __IM uint32_t RESERVED12;
+ __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */
+ __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */
+ __IM uint32_t RESERVED13[2];
+ __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */
+ __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */
+ __IM uint32_t RESERVED15[24];
+ __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */
+} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NFCT ================ */
+/* =========================================================================================================================== */
/**
* @brief NFC-A compatible radio (NFCT)
*/
-typedef struct { /*!< NFCT Structure */
- __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change
- state to activated */
- __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */
- __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */
- __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */
- __I uint32_t RESERVED0[3];
- __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */
- __I uint32_t RESERVED1;
- __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */
- __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */
- __I uint32_t RESERVED2[53];
- __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */
- __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */
- __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */
- __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */
- __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */
- __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */
- __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred
- to RAM, and EasyDMA has ended accessing the RX buffer */
- __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details
- on the source of the error. */
- __I uint32_t RESERVED3[2];
- __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
- details on the source of the error. */
- __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
- __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended
- accessing the TX buffer */
- __I uint32_t RESERVED4;
- __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */
- __I uint32_t RESERVED5[3];
- __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */
- __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */
- __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */
- __I uint32_t RESERVED6[43];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED7[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED8[62];
- __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */
- __I uint32_t RESERVED9;
- NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */
- __I uint32_t RESERVED10[8];
- __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */
- __I uint32_t RESERVED11[2];
- __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */
- __I uint32_t RESERVED12[49];
- __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */
- __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */
- __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */
- __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */
- __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data
- RAM */
- NFCT_TXD_Type TXD; /*!< Unspecified */
- NFCT_RXD_Type RXD; /*!< Unspecified */
- __I uint32_t RESERVED13[26];
- __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */
- __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */
- __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */
- __I uint32_t RESERVED14;
- __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */
- __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */
-} NRF_NFCT_Type;
-
-
-/* ================================================================================ */
-/* ================ GPIOTE ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40005000) NFCT Structure */
+ __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing
+ frames, change state to activated */
+ __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */
+ __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to
+ sense mode */
+ __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change
+ state to transmit */
+ __IM uint32_t RESERVED[3];
+ __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */
+ __IM uint32_t RESERVED1;
+ __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */
+ __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */
+ __IM uint32_t RESERVED2[53];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send
+ frames */
+ __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */
+ __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */
+ __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted
+ frame */
+ __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air
+ symbol of a frame */
+ __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received
+ frame */
+ __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity)
+ and transferred to RAM, and EasyDMA has
+ ended accessing the RX buffer */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register
+ contains details on the source of the error. */
+ __IM uint32_t RESERVED3[2];
+ __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX
+ register contains details on the source
+ of the error. */
+ __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN)
+ in Data RAM full. */
+ __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA
+ has ended accessing the TX buffer */
+ __IM uint32_t RESERVED4;
+ __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */
+ __IM uint32_t RESERVED5[3];
+ __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */
+ __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */
+ __IM uint32_t RESERVED6[43];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED7[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED8[62];
+ __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */
+ __IM uint32_t RESERVED9;
+ __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */
+ __IM uint32_t RESERVED10[8];
+ __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */
+ __IM uint32_t RESERVED11[2];
+ __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */
+ __IM uint32_t RESERVED12[49];
+ __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */
+ __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */
+ __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */
+ __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in
+ Data RAM */
+ __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage
+ buffer in Data RAM */
+ __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */
+ __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */
+ __IM uint32_t RESERVED13[26];
+ __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */
+ __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */
+ __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */
+ __IM uint32_t RESERVED14;
+ __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */
+ __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */
+} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ GPIOTE ================ */
+/* =========================================================================================================================== */
/**
* @brief GPIO Tasks and Events (GPIOTE)
*/
-typedef struct { /*!< GPIOTE Structure */
- __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified
- in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
- __I uint32_t RESERVED0[4];
- __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified
- in CONFIG[0].PSEL. Action on pin is to set it high. */
- __I uint32_t RESERVED1[4];
- __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified
- in CONFIG[0].PSEL. Action on pin is to set it low. */
- __I uint32_t RESERVED2[32];
- __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified
- in CONFIG[0].PSEL */
- __I uint32_t RESERVED3[23];
- __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism
- enabled */
- __I uint32_t RESERVED4[97];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED5[129];
- __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n]
- and CLR[n] tasks and IN[n] event */
-} NRF_GPIOTE_Type;
-
-
-/* ================================================================================ */
-/* ================ SAADC ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */
+ __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to
+ pin specified in CONFIG[0].PSEL. Action
+ on pin is configured in CONFIG[0].POLARITY. */
+ __IM uint32_t RESERVED[4];
+ __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to
+ pin specified in CONFIG[0].PSEL. Action
+ on pin is to set it high. */
+ __IM uint32_t RESERVED1[4];
+ __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to
+ pin specified in CONFIG[0].PSEL. Action
+ on pin is to set it low. */
+ __IM uint32_t RESERVED2[32];
+ __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from
+ pin specified in CONFIG[0].PSEL */
+ __IM uint32_t RESERVED3[23];
+ __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins
+ with SENSE mechanism enabled */
+ __IM uint32_t RESERVED4[97];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED5[129];
+ __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for
+ OUT[n], SET[n] and CLR[n] tasks and IN[n]
+ event */
+} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SAADC ================ */
+/* =========================================================================================================================== */
/**
* @brief Analog to Digital Converter (SAADC)
*/
-typedef struct { /*!< SAADC Structure */
- __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */
- __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */
- __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */
- __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */
- __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */
- __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode,
- multiple conversions might be needed for a result to be transferred
- to RAM. */
- __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */
- __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */
- __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */
- SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */
- __I uint32_t RESERVED1[106];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[61];
- __I uint32_t STATUS; /*!< Status */
- __I uint32_t RESERVED3[63];
- __IO uint32_t ENABLE; /*!< Enable or disable ADC */
- __I uint32_t RESERVED4[3];
- SAADC_CH_Type CH[8]; /*!< Unspecified */
- __I uint32_t RESERVED5[24];
- __IO uint32_t RESOLUTION; /*!< Resolution configuration */
- __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined
- with SCAN. The RESOLUTION is applied before averaging, thus
- for high OVERSAMPLE a higher RESOLUTION should be used. */
- __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */
- __I uint32_t RESERVED6[12];
- SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */
-} NRF_SAADC_Type;
-
-
-/* ================================================================================ */
-/* ================ TIMER ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Timer/Counter 0 (TIMER)
- */
-
-typedef struct { /*!< TIMER Structure */
- __O uint32_t TASKS_START; /*!< Start Timer */
- __O uint32_t TASKS_STOP; /*!< Stop Timer */
- __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */
- __O uint32_t TASKS_CLEAR; /*!< Clear time */
- __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */
- __I uint32_t RESERVED0[11];
- __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */
- __I uint32_t RESERVED1[58];
- __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */
- __I uint32_t RESERVED2[42];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED3[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED4[126];
- __IO uint32_t MODE; /*!< Timer mode selection */
- __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */
- __I uint32_t RESERVED5;
- __IO uint32_t PRESCALER; /*!< Timer prescaler register */
- __I uint32_t RESERVED6[11];
- __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================ RTC ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Real time counter 0 (RTC)
- */
-
-typedef struct { /*!< RTC Structure */
- __O uint32_t TASKS_START; /*!< Start RTC COUNTER */
- __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */
- __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */
- __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */
- __I uint32_t RESERVED0[60];
- __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */
- __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */
- __I uint32_t RESERVED1[14];
- __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */
- __I uint32_t RESERVED2[109];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[13];
- __IO uint32_t EVTEN; /*!< Enable or disable event routing */
- __IO uint32_t EVTENSET; /*!< Enable event routing */
- __IO uint32_t EVTENCLR; /*!< Disable event routing */
- __I uint32_t RESERVED4[110];
- __I uint32_t COUNTER; /*!< Current COUNTER value */
- __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
- be written when RTC is stopped */
- __I uint32_t RESERVED5[13];
- __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================ TEMP ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40007000) SAADC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in
+ RAM */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels
+ are sampled */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */
+ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */
+ __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending
+ on the mode, multiple conversions might
+ be needed for a result to be transferred
+ to RAM. */
+ __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */
+ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */
+ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */
+ __IM uint32_t RESERVED1[106];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */
+ __IM uint32_t RESERVED4[3];
+ __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */
+ __IM uint32_t RESERVED5[24];
+ __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */
+ __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should
+ not be combined with SCAN. The RESOLUTION
+ is applied before averaging, thus for high
+ OVERSAMPLE a higher RESOLUTION should be
+ used. */
+ __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */
+ __IM uint32_t RESERVED6[12];
+ __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */
+} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TIMER0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Timer/Counter 0 (TIMER0)
+ */
+
+typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */
+ __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */
+ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */
+ __IM uint32_t RESERVED[11];
+ __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value
+ to CC[0] register */
+ __IM uint32_t RESERVED1[58];
+ __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0]
+ match */
+ __IM uint32_t RESERVED2[42];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED3[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[126];
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */
+ __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */
+ __IM uint32_t RESERVED6[11];
+ __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register
+ 0 */
+} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RTC0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Real time counter 0 (RTC0)
+ */
+
+typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */
+ __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */
+ __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */
+ __IM uint32_t RESERVED[60];
+ __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */
+ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */
+ __IM uint32_t RESERVED1[14];
+ __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0]
+ match */
+ __IM uint32_t RESERVED2[109];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[13];
+ __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */
+ __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */
+ __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */
+ __IM uint32_t RESERVED4[110];
+ __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu
+ t be written when RTC is stopped */
+ __IM uint32_t RESERVED5[13];
+ __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */
+} NRF_RTC_Type; /*!< Size = 1360 (0x550) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ TEMP ================ */
+/* =========================================================================================================================== */
/**
* @brief Temperature Sensor (TEMP)
*/
-typedef struct { /*!< TEMP Structure */
- __O uint32_t TASKS_START; /*!< Start temperature measurement */
- __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[127];
- __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */
- __I uint32_t RESERVED3[5];
- __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */
- __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */
- __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */
- __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */
- __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */
- __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */
- __I uint32_t RESERVED4[2];
- __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */
- __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */
- __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */
- __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */
- __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */
- __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */
- __I uint32_t RESERVED5[2];
- __IO uint32_t T0; /*!< End point of 1st piece wise linear function */
- __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */
- __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */
- __IO uint32_t T3; /*!< End point of 4th piece wise linear function */
- __IO uint32_t T4; /*!< End point of 5th piece wise linear function */
-} NRF_TEMP_Type;
-
-
-/* ================================================================================ */
-/* ================ RNG ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000C000) TEMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[127];
+ __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */
+ __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */
+ __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */
+ __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */
+ __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */
+ __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */
+ __IM uint32_t RESERVED4[2];
+ __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */
+ __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */
+ __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */
+ __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */
+ __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */
+ __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */
+ __IM uint32_t RESERVED5[2];
+ __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */
+ __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */
+ __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */
+ __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */
+ __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */
+} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ RNG ================ */
+/* =========================================================================================================================== */
/**
* @brief Random Number Generator (RNG)
*/
-typedef struct { /*!< RNG Structure */
- __O uint32_t TASKS_START; /*!< Task starting the random number generator */
- __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to
- the VALUE register */
- __I uint32_t RESERVED1[63];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[126];
- __IO uint32_t CONFIG; /*!< Configuration register */
- __I uint32_t VALUE; /*!< Output random number */
-} NRF_RNG_Type;
+typedef struct { /*!< (@ 0x4000D000) RNG Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number
+ written to the VALUE register */
+ __IM uint32_t RESERVED1[63];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[126];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
+ __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */
+} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */
+
-/* ================================================================================ */
-/* ================ ECB ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ ECB ================ */
+/* =========================================================================================================================== */
/**
* @brief AES ECB Mode Encryption (ECB)
*/
-typedef struct { /*!< ECB Structure */
- __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */
- __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */
- __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to
- an error */
- __I uint32_t RESERVED1[127];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[126];
- __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */
-} NRF_ECB_Type;
+typedef struct { /*!< (@ 0x4000E000) ECB Structure */
+ __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */
+ __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */
+ __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB
+ task or due to an error */
+ __IM uint32_t RESERVED1[127];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */
+} NRF_ECB_Type; /*!< Size = 1288 (0x508) */
-/* ================================================================================ */
-/* ================ CCM ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ CCM ================ */
+/* =========================================================================================================================== */
/**
* @brief AES CCM Mode Encryption (CCM)
*/
-typedef struct { /*!< CCM Structure */
- __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
- itself when completed. */
- __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself
- when completed. */
- __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */
- __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */
- __IO uint32_t EVENTS_ERROR; /*!< CCM error event */
- __I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[61];
- __I uint32_t MICSTATUS; /*!< MIC check result */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable */
- __IO uint32_t MODE; /*!< Operation mode */
- __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */
- __IO uint32_t INPTR; /*!< Input pointer */
- __IO uint32_t OUTPTR; /*!< Output pointer */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================ AAR ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000F000) CCM Structure */
+ __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation
+ will stop by itself when completed. */
+ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will
+ stop by itself when completed. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */
+ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
+ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */
+ __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and
+ NONCE vector */
+ __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
+ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+} NRF_CCM_Type; /*!< Size = 1304 (0x518) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ AAR ================ */
+/* =========================================================================================================================== */
/**
* @brief Accelerated Address Resolver (AAR)
*/
-typedef struct { /*!< AAR Structure */
- __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
- data structure */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */
- __I uint32_t RESERVED1[61];
- __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */
- __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */
- __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */
- __I uint32_t RESERVED2[126];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[61];
- __I uint32_t STATUS; /*!< Resolution status */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable AAR */
- __IO uint32_t NIRK; /*!< Number of IRKs */
- __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */
- __I uint32_t RESERVED5;
- __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================ WDT ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4000F000) AAR Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified
+ in the IRK data structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */
+ __IM uint32_t RESERVED1[61];
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */
+ __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */
+ __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */
+ __IM uint32_t RESERVED2[126];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */
+ __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */
+ __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */
+ __IM uint32_t RESERVED5;
+ __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */
+ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
+} NRF_AAR_Type; /*!< Size = 1304 (0x518) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ WDT ================ */
+/* =========================================================================================================================== */
/**
* @brief Watchdog Timer (WDT)
*/
-typedef struct { /*!< WDT Structure */
- __O uint32_t TASKS_START; /*!< Start the watchdog */
- __I uint32_t RESERVED0[63];
- __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */
- __I uint32_t RESERVED1[128];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[61];
- __I uint32_t RUNSTATUS; /*!< Run status */
- __I uint32_t REQSTATUS; /*!< Request status */
- __I uint32_t RESERVED3[63];
- __IO uint32_t CRV; /*!< Counter reload value */
- __IO uint32_t RREN; /*!< Enable register for reload request registers */
- __IO uint32_t CONFIG; /*!< Configuration register */
- __I uint32_t RESERVED4[60];
- __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */
-} NRF_WDT_Type;
+typedef struct { /*!< (@ 0x40010000) WDT Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */
+ __IM uint32_t RESERVED1[128];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[61];
+ __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */
+ __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */
+ __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */
+ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */
+ __IM uint32_t RESERVED4[60];
+ __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */
+} NRF_WDT_Type; /*!< Size = 1568 (0x620) */
+
-/* ================================================================================ */
-/* ================ QDEC ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ QDEC ================ */
+/* =========================================================================================================================== */
/**
* @brief Quadrature Decoder (QDEC)
*/
-typedef struct { /*!< QDEC Structure */
- __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */
- __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */
- __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */
- __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */
- __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */
- __I uint32_t RESERVED0[59];
- __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to
- the SAMPLE register */
- __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */
- __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */
- __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */
- __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */
- __I uint32_t RESERVED1[59];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[125];
- __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */
- __IO uint32_t LEDPOL; /*!< LED output pin polarity */
- __IO uint32_t SAMPLEPER; /*!< Sample period */
- __I int32_t SAMPLE; /*!< Motion sample value */
- __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
- can be generated */
- __I int32_t ACC; /*!< Register accumulating the valid transitions */
- __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
- task */
- QDEC_PSEL_Type PSEL; /*!< Unspecified */
- __IO uint32_t DBFEN; /*!< Enable input debounce filters */
- __I uint32_t RESERVED4[5];
- __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */
- __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */
- __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
- task */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================ COMP ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40012000) QDEC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */
+ __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */
+ __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */
+ __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */
+ __IM uint32_t RESERVED[59];
+ __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value
+ written to the SAMPLE register */
+ __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */
+ __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */
+ __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */
+ __IM uint32_t RESERVED1[59];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */
+ __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */
+ __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */
+ __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */
+ __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY
+ and DBLRDY events can be generated */
+ __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */
+ __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the
+ READCLRACC or RDCLRACC task */
+ __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */
+ __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */
+ __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected
+ double transitions */
+ __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC
+ or RDCLRDBL task */
+} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ COMP ================ */
+/* =========================================================================================================================== */
/**
* @brief Comparator (COMP)
*/
-typedef struct { /*!< COMP Structure */
- __O uint32_t TASKS_START; /*!< Start comparator */
- __O uint32_t TASKS_STOP; /*!< Stop comparator */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */
- __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
- __IO uint32_t EVENTS_UP; /*!< Upward crossing */
- __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED2[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Compare result */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< COMP enable */
- __IO uint32_t PSEL; /*!< Pin select */
- __IO uint32_t REFSEL; /*!< Reference source select for single-ended mode */
- __IO uint32_t EXTREFSEL; /*!< External reference select */
- __I uint32_t RESERVED5[8];
- __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */
- __IO uint32_t MODE; /*!< Mode configuration */
- __IO uint32_t HYST; /*!< Comparator hysteresis enable */
- __IO uint32_t ISOURCE; /*!< Current source select on analog input */
-} NRF_COMP_Type;
-
-
-/* ================================================================================ */
-/* ================ LPCOMP ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40013000) COMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */
+ __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */
+ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
+ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED2[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */
+ __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */
+ __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */
+ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */
+ __IM uint32_t RESERVED5[8];
+ __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */
+ __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */
+ __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */
+ __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */
+} NRF_COMP_Type; /*!< Size = 1344 (0x540) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ LPCOMP ================ */
+/* =========================================================================================================================== */
/**
* @brief Low Power Comparator (LPCOMP)
*/
-typedef struct { /*!< LPCOMP Structure */
- __O uint32_t TASKS_START; /*!< Start comparator */
- __O uint32_t TASKS_STOP; /*!< Stop comparator */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */
- __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
- __IO uint32_t EVENTS_UP; /*!< Upward crossing */
- __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Compare result */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable LPCOMP */
- __IO uint32_t PSEL; /*!< Input pin select */
- __IO uint32_t REFSEL; /*!< Reference select */
- __IO uint32_t EXTREFSEL; /*!< External reference select */
- __I uint32_t RESERVED5[4];
- __IO uint32_t ANADETECT; /*!< Analog detect configuration */
- __I uint32_t RESERVED6[5];
- __IO uint32_t HYST; /*!< Comparator hysteresis enable */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================ SWI ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Software interrupt 0 (SWI)
- */
-
-typedef struct { /*!< SWI Structure */
- __I uint32_t UNUSED; /*!< Unused. */
-} NRF_SWI_Type;
-
-
-/* ================================================================================ */
-/* ================ EGU ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Event Generator Unit 0 (EGU)
- */
-
-typedef struct { /*!< EGU Structure */
- __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding
- TRIGGERED[0] event */
- __I uint32_t RESERVED0[48];
- __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering
- the corresponding TRIGGER[0] task */
- __I uint32_t RESERVED1[112];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
-} NRF_EGU_Type;
-
-
-/* ================================================================================ */
-/* ================ PWM ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Pulse Width Modulation Unit 0 (PWM)
- */
-
-typedef struct { /*!< PWM Structure */
- __I uint32_t RESERVED0;
- __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current
- PWM period, and stops sequence playback */
- __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all
- enabled channels from sequence 0, and starts playing that sequence
- at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
- PWM generation to start it was not running. */
- __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels
- if DECODER.MODE=NextStep. Does not cause PWM generation to start
- it was not running. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer
- generated */
- __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence
- 0 */
- __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence
- 0, when last value from RAM has been applied to wave counter */
- __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */
- __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times
- defined in LOOP.CNT */
- __I uint32_t RESERVED2[56];
- __IO uint32_t SHORTS; /*!< Shortcut register */
- __I uint32_t RESERVED3[63];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED4[125];
- __IO uint32_t ENABLE; /*!< PWM module enable register */
- __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */
- __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */
- __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */
- __IO uint32_t DECODER; /*!< Configuration of the decoder */
- __IO uint32_t LOOP; /*!< Amount of playback of a loop */
- __I uint32_t RESERVED5[2];
- PWM_SEQ_Type SEQ[2]; /*!< Unspecified */
- PWM_PSEL_Type PSEL; /*!< Unspecified */
-} NRF_PWM_Type;
-
+typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */
+ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */
+ __IM uint32_t RESERVED[61];
+ __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */
+ __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */
+ __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */
+ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[61];
+ __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */
+ __IM uint32_t RESERVED4[63];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */
+ __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */
+ __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */
+ __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */
+ __IM uint32_t RESERVED5[4];
+ __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */
+ __IM uint32_t RESERVED6[5];
+ __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */
+} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ SWI0 ================ */
+/* =========================================================================================================================== */
-/* ================================================================================ */
-/* ================ PDM ================ */
-/* ================================================================================ */
+
+/**
+ * @brief Software interrupt 0 (SWI0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) SWI0 Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_SWI_Type; /*!< Size = 4 (0x4) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ EGU0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Event Generator Unit 0 (EGU0)
+ */
+
+typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
+ __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering
+ the corresponding TRIGGERED[0] event */
+ __IM uint32_t RESERVED[48];
+ __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated
+ by triggering the corresponding TRIGGER[0]
+ task */
+ __IM uint32_t RESERVED1[112];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+} NRF_EGU_Type; /*!< Size = 780 (0x30c) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PWM0 ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Pulse Width Modulation Unit 0 (PWM0)
+ */
+
+typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */
+ __IM uint32_t RESERVED;
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at
+ the end of current PWM period, and stops
+ sequence playback */
+ __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM
+ value on all enabled channels from sequence
+ 0, and starts playing that sequence at the
+ rate defined in SEQ[0]REFRESH and/or DECODER.MODE.
+ Causes PWM generation to start it was not
+ running. */
+ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on
+ all enabled channels if DECODER.MODE=NextStep.
+ Does not cause PWM generation to start it
+ was not running. */
+ __IM uint32_t RESERVED1[60];
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses
+ are no longer generated */
+ __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started
+ on sequence 0 */
+ __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of
+ every sequence 0, when last value from RAM
+ has been applied to wave counter */
+ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */
+ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount
+ of times defined in LOOP.CNT */
+ __IM uint32_t RESERVED2[56];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */
+ __IM uint32_t RESERVED3[63];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED4[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */
+ __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */
+ __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter
+ counts */
+ __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */
+ __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */
+ __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */
+ __IM uint32_t RESERVED5[2];
+ __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */
+ __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_PWM_Type; /*!< Size = 1392 (0x570) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ PDM ================ */
+/* =========================================================================================================================== */
/**
* @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
*/
-typedef struct { /*!< PDM Structure */
- __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */
- __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */
- __I uint32_t RESERVED0[62];
- __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */
- __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */
- __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
- (or the last sample after a STOP task has been received) to
- Data RAM */
- __I uint32_t RESERVED1[125];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED2[125];
- __IO uint32_t ENABLE; /*!< PDM module enable register */
- __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */
- __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */
- __I uint32_t RESERVED3[3];
- __IO uint32_t GAINL; /*!< Left output gain adjustment */
- __IO uint32_t GAINR; /*!< Right output gain adjustment */
- __I uint32_t RESERVED4[8];
- PDM_PSEL_Type PSEL; /*!< Unspecified */
- __I uint32_t RESERVED5[6];
- PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */
-} NRF_PDM_Type;
-
-
-/* ================================================================================ */
-/* ================ NVMC ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x4001D000) PDM Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */
+ __IM uint32_t RESERVED[62];
+ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */
+ __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified
+ by SAMPLE.MAXCNT (or the last sample after
+ a STOP task has been received) to Data RAM */
+ __IM uint32_t RESERVED1[125];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED2[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */
+ __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */
+ __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones'
+ signals */
+ __IM uint32_t RESERVED3[3];
+ __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */
+ __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */
+ __IM uint32_t RESERVED4[8];
+ __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED5[6];
+ __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */
+} NRF_PDM_Type; /*!< Size = 1384 (0x568) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ NVMC ================ */
+/* =========================================================================================================================== */
/**
* @brief Non Volatile Memory Controller (NVMC)
*/
-typedef struct { /*!< NVMC Structure */
- __I uint32_t RESERVED0[256];
- __I uint32_t READY; /*!< Ready flag */
- __I uint32_t RESERVED1[64];
- __IO uint32_t CONFIG; /*!< Configuration register */
+typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
+ __IM uint32_t RESERVED[256];
+ __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */
+ __IM uint32_t RESERVED1[64];
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
union {
- __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area.
- Equivalent to ERASEPAGE. */
- __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */
+ __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */
+ __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
+ page in Code area. Equivalent to ERASEPAGE. */
};
- __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */
- __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area.
- Equivalent to ERASEPAGE. */
- __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */
- __I uint32_t RESERVED2[10];
- __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */
- __I uint32_t RESERVED3;
- __IO uint32_t IHIT; /*!< I-Code cache hit counter. */
- __IO uint32_t IMISS; /*!< I-Code cache miss counter. */
-} NRF_NVMC_Type;
+ __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
+ page in Code area. Equivalent to ERASEPAGE. */
+ __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration
+ Registers */
+ __IM uint32_t RESERVED2[10];
+ __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */
+ __IM uint32_t RESERVED3;
+ __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */
+ __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */
+} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */
+
-/* ================================================================================ */
-/* ================ PPI ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ PPI ================ */
+/* =========================================================================================================================== */
/**
* @brief Programmable Peripheral Interconnect (PPI)
*/
-typedef struct { /*!< PPI Structure */
- PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */
- __I uint32_t RESERVED0[308];
- __IO uint32_t CHEN; /*!< Channel enable register */
- __IO uint32_t CHENSET; /*!< Channel enable set register */
- __IO uint32_t CHENCLR; /*!< Channel enable clear register */
- __I uint32_t RESERVED1;
- PPI_CH_Type CH[20]; /*!< PPI Channel */
- __I uint32_t RESERVED2[148];
- __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */
- __I uint32_t RESERVED3[62];
- PPI_FORK_Type FORK[32]; /*!< Fork */
-} NRF_PPI_Type;
+typedef struct { /*!< (@ 0x4001F000) PPI Structure */
+ __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */
+ __IM uint32_t RESERVED[308];
+ __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */
+ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
+ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
+ __IM uint32_t RESERVED1;
+ __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
+ __IM uint32_t RESERVED2[148];
+ __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */
+ __IM uint32_t RESERVED3[62];
+ __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
+} NRF_PPI_Type; /*!< Size = 2448 (0x990) */
-/* ================================================================================ */
-/* ================ MWU ================ */
-/* ================================================================================ */
+
+/* =========================================================================================================================== */
+/* ================ MWU ================ */
+/* =========================================================================================================================== */
/**
* @brief Memory Watch Unit (MWU)
*/
-typedef struct { /*!< MWU Structure */
- __I uint32_t RESERVED0[64];
- MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */
- __I uint32_t RESERVED1[16];
- MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */
- __I uint32_t RESERVED2[100];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[5];
- __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */
- __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */
- __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */
- __I uint32_t RESERVED4[53];
- MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */
- __I uint32_t RESERVED5[64];
- __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */
- __IO uint32_t REGIONENSET; /*!< Enable regions watch */
- __IO uint32_t REGIONENCLR; /*!< Disable regions watch */
- __I uint32_t RESERVED6[57];
- MWU_REGION_Type REGION[4]; /*!< Unspecified */
- __I uint32_t RESERVED7[32];
- MWU_PREGION_Type PREGION[2]; /*!< Unspecified */
-} NRF_MWU_Type;
-
-
-/* ================================================================================ */
-/* ================ I2S ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40020000) MWU Structure */
+ __IM uint32_t RESERVED[64];
+ __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */
+ __IM uint32_t RESERVED1[16];
+ __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */
+ __IM uint32_t RESERVED2[100];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[5];
+ __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */
+ __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */
+ __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */
+ __IM uint32_t RESERVED4[53];
+ __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */
+ __IM uint32_t RESERVED5[64];
+ __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */
+ __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */
+ __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */
+ __IM uint32_t RESERVED6[57];
+ __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */
+ __IM uint32_t RESERVED7[32];
+ __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */
+} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ I2S ================ */
+/* =========================================================================================================================== */
/**
* @brief Inter-IC Sound (I2S)
*/
-typedef struct { /*!< I2S Structure */
- __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when
- this is enabled. */
- __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
- task will cause the {event:STOPPED} event to be generated. */
- __I uint32_t RESERVED0[63];
- __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers.
- When the I2S module is started and RX is enabled, this event
- will be generated for every RXTXD.MAXCNT words that are received
- on the SDIN pin. */
- __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */
- __I uint32_t RESERVED1[2];
- __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers.
- When the I2S module is started and TX is enabled, this event
- will be generated for every RXTXD.MAXCNT words that are sent
- on the SDOUT pin. */
- __I uint32_t RESERVED2[122];
- __IO uint32_t INTEN; /*!< Enable or disable interrupt */
- __IO uint32_t INTENSET; /*!< Enable interrupt */
- __IO uint32_t INTENCLR; /*!< Disable interrupt */
- __I uint32_t RESERVED3[125];
- __IO uint32_t ENABLE; /*!< Enable I2S module. */
- I2S_CONFIG_Type CONFIG; /*!< Unspecified */
- __I uint32_t RESERVED4[3];
- I2S_RXD_Type RXD; /*!< Unspecified */
- __I uint32_t RESERVED5;
- I2S_TXD_Type TXD; /*!< Unspecified */
- __I uint32_t RESERVED6[3];
- I2S_RXTXD_Type RXTXD; /*!< Unspecified */
- __I uint32_t RESERVED7[3];
- I2S_PSEL_Type PSEL; /*!< Unspecified */
-} NRF_I2S_Type;
-
-
-/* ================================================================================ */
-/* ================ FPU ================ */
-/* ================================================================================ */
+typedef struct { /*!< (@ 0x40025000) I2S Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK
+ generator when this is enabled. */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator.
+ Triggering this task will cause the {event:STOPPED}
+ event to be generated. */
+ __IM uint32_t RESERVED[63];
+ __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and RX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are received
+ on the SDIN pin. */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */
+ __IM uint32_t RESERVED1[2];
+ __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal
+ double-buffers. When the I2S module is started
+ and TX is enabled, this event will be generated
+ for every RXTXD.MAXCNT words that are sent
+ on the SDOUT pin. */
+ __IM uint32_t RESERVED2[122];
+ __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */
+ __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */
+ __IM uint32_t RESERVED4[3];
+ __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */
+ __IM uint32_t RESERVED5;
+ __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */
+ __IM uint32_t RESERVED6[3];
+ __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */
+ __IM uint32_t RESERVED7[3];
+ __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */
+} NRF_I2S_Type; /*!< Size = 1396 (0x574) */
+
+
+
+/* =========================================================================================================================== */
+/* ================ FPU ================ */
+/* =========================================================================================================================== */
/**
* @brief FPU (FPU)
*/
-typedef struct { /*!< FPU Structure */
- __I uint32_t UNUSED; /*!< Unused. */
-} NRF_FPU_Type;
+typedef struct { /*!< (@ 0x40026000) FPU Structure */
+ __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */
+} NRF_FPU_Type; /*!< Size = 4 (0x4) */
+
-/* ================================================================================ */
-/* ================ GPIO ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ P0 ================ */
+/* =========================================================================================================================== */
/**
- * @brief GPIO Port 1 (GPIO)
+ * @brief GPIO Port 1 (P0)
*/
-typedef struct { /*!< GPIO Structure */
- __I uint32_t RESERVED0[321];
- __IO uint32_t OUT; /*!< Write GPIO port */
- __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */
- __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */
- __I uint32_t IN; /*!< Read GPIO port */
- __IO uint32_t DIR; /*!< Direction of GPIO pins */
- __IO uint32_t DIRSET; /*!< DIR set register */
- __IO uint32_t DIRCLR; /*!< DIR clear register */
- __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria
- set in the PIN_CNF[n].SENSE registers */
- __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */
- __I uint32_t RESERVED1[118];
- __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */
-} NRF_GPIO_Type;
+typedef struct { /*!< (@ 0x50000000) P0 Structure */
+ __IM uint32_t RESERVED[321];
+ __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */
+ __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */
+ __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */
+ __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */
+ __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */
+ __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */
+ __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */
+ __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
+ have met the criteria set in the PIN_CNF[n].SENSE
+ registers */
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
+ and LDETECT mode */
+ __IM uint32_t RESERVED1[118];
+ __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO
+ pins */
+} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */
+
+
+/** @} */ /* End of group Device_Peripheral_peripherals */
+
+
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Address Map ================ */
+/* =========================================================================================================================== */
-/* -------------------- End of section using anonymous unions ------------------- */
-#if defined(__CC_ARM)
+/** @addtogroup Device_Peripheral_peripheralAddr
+ * @{
+ */
+
+#define NRF_FICR_BASE 0x10000000UL
+#define NRF_UICR_BASE 0x10001000UL
+#define NRF_BPROT_BASE 0x40000000UL
+#define NRF_POWER_BASE 0x40000000UL
+#define NRF_CLOCK_BASE 0x40000000UL
+#define NRF_RADIO_BASE 0x40001000UL
+#define NRF_UARTE0_BASE 0x40002000UL
+#define NRF_UART0_BASE 0x40002000UL
+#define NRF_SPIM0_BASE 0x40003000UL
+#define NRF_SPIS0_BASE 0x40003000UL
+#define NRF_TWIM0_BASE 0x40003000UL
+#define NRF_TWIS0_BASE 0x40003000UL
+#define NRF_SPI0_BASE 0x40003000UL
+#define NRF_TWI0_BASE 0x40003000UL
+#define NRF_SPIM1_BASE 0x40004000UL
+#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_TWIM1_BASE 0x40004000UL
+#define NRF_TWIS1_BASE 0x40004000UL
+#define NRF_SPI1_BASE 0x40004000UL
+#define NRF_TWI1_BASE 0x40004000UL
+#define NRF_NFCT_BASE 0x40005000UL
+#define NRF_GPIOTE_BASE 0x40006000UL
+#define NRF_SAADC_BASE 0x40007000UL
+#define NRF_TIMER0_BASE 0x40008000UL
+#define NRF_TIMER1_BASE 0x40009000UL
+#define NRF_TIMER2_BASE 0x4000A000UL
+#define NRF_RTC0_BASE 0x4000B000UL
+#define NRF_TEMP_BASE 0x4000C000UL
+#define NRF_RNG_BASE 0x4000D000UL
+#define NRF_ECB_BASE 0x4000E000UL
+#define NRF_CCM_BASE 0x4000F000UL
+#define NRF_AAR_BASE 0x4000F000UL
+#define NRF_WDT_BASE 0x40010000UL
+#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
+#define NRF_COMP_BASE 0x40013000UL
+#define NRF_LPCOMP_BASE 0x40013000UL
+#define NRF_SWI0_BASE 0x40014000UL
+#define NRF_EGU0_BASE 0x40014000UL
+#define NRF_SWI1_BASE 0x40015000UL
+#define NRF_EGU1_BASE 0x40015000UL
+#define NRF_SWI2_BASE 0x40016000UL
+#define NRF_EGU2_BASE 0x40016000UL
+#define NRF_SWI3_BASE 0x40017000UL
+#define NRF_EGU3_BASE 0x40017000UL
+#define NRF_SWI4_BASE 0x40018000UL
+#define NRF_EGU4_BASE 0x40018000UL
+#define NRF_SWI5_BASE 0x40019000UL
+#define NRF_EGU5_BASE 0x40019000UL
+#define NRF_TIMER3_BASE 0x4001A000UL
+#define NRF_TIMER4_BASE 0x4001B000UL
+#define NRF_PWM0_BASE 0x4001C000UL
+#define NRF_PDM_BASE 0x4001D000UL
+#define NRF_NVMC_BASE 0x4001E000UL
+#define NRF_PPI_BASE 0x4001F000UL
+#define NRF_MWU_BASE 0x40020000UL
+#define NRF_PWM1_BASE 0x40021000UL
+#define NRF_PWM2_BASE 0x40022000UL
+#define NRF_SPIM2_BASE 0x40023000UL
+#define NRF_SPIS2_BASE 0x40023000UL
+#define NRF_SPI2_BASE 0x40023000UL
+#define NRF_RTC2_BASE 0x40024000UL
+#define NRF_I2S_BASE 0x40025000UL
+#define NRF_FPU_BASE 0x40026000UL
+#define NRF_P0_BASE 0x50000000UL
+
+/** @} */ /* End of group Device_Peripheral_peripheralAddr */
+
+
+/* =========================================================================================================================== */
+/* ================ Peripheral declaration ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_declaration
+ * @{
+ */
+
+#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE)
+#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE)
+#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE)
+#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE)
+#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE)
+#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE)
+#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE)
+#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE)
+#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE)
+#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE)
+#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE)
+#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE)
+#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE)
+#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE)
+#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE)
+#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE)
+#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE)
+#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE)
+#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE)
+#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE)
+#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE)
+#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE)
+#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE)
+#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE)
+#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE)
+#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE)
+#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE)
+#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE)
+#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE)
+#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE)
+#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
+#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE)
+#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
+#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
+#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE)
+#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE)
+#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
+#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
+#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE)
+#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
+#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE)
+#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE)
+#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE)
+#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE)
+#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE)
+#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE)
+#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE)
+#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE)
+#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE)
+#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE)
+#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE)
+#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE)
+#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE)
+#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE)
+#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE)
+#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE)
+#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE)
+#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE)
+#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE)
+#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE)
+#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE)
+#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE)
+#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE)
+#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
+
+/** @} */ /* End of group Device_Peripheral_declaration */
+
+
+/* ========================================= End of section using anonymous unions ========================================= */
+#if defined (__CC_ARM)
#pragma pop
-#elif defined(__ICCARM__)
+#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
-#elif defined(__GNUC__)
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
+#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
+#elif defined (__TASKING__)
#pragma warning restore
-#else
- #warning Not supported compiler type
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
#endif
-
-
-/* ================================================================================ */
-/* ================ Peripheral memory map ================ */
-/* ================================================================================ */
-
-#define NRF_FICR_BASE 0x10000000UL
-#define NRF_UICR_BASE 0x10001000UL
-#define NRF_BPROT_BASE 0x40000000UL
-#define NRF_POWER_BASE 0x40000000UL
-#define NRF_CLOCK_BASE 0x40000000UL
-#define NRF_RADIO_BASE 0x40001000UL
-#define NRF_UARTE0_BASE 0x40002000UL
-#define NRF_UART0_BASE 0x40002000UL
-#define NRF_SPIM0_BASE 0x40003000UL
-#define NRF_SPIS0_BASE 0x40003000UL
-#define NRF_TWIM0_BASE 0x40003000UL
-#define NRF_TWIS0_BASE 0x40003000UL
-#define NRF_SPI0_BASE 0x40003000UL
-#define NRF_TWI0_BASE 0x40003000UL
-#define NRF_SPIM1_BASE 0x40004000UL
-#define NRF_SPIS1_BASE 0x40004000UL
-#define NRF_TWIM1_BASE 0x40004000UL
-#define NRF_TWIS1_BASE 0x40004000UL
-#define NRF_SPI1_BASE 0x40004000UL
-#define NRF_TWI1_BASE 0x40004000UL
-#define NRF_NFCT_BASE 0x40005000UL
-#define NRF_GPIOTE_BASE 0x40006000UL
-#define NRF_SAADC_BASE 0x40007000UL
-#define NRF_TIMER0_BASE 0x40008000UL
-#define NRF_TIMER1_BASE 0x40009000UL
-#define NRF_TIMER2_BASE 0x4000A000UL
-#define NRF_RTC0_BASE 0x4000B000UL
-#define NRF_TEMP_BASE 0x4000C000UL
-#define NRF_RNG_BASE 0x4000D000UL
-#define NRF_ECB_BASE 0x4000E000UL
-#define NRF_CCM_BASE 0x4000F000UL
-#define NRF_AAR_BASE 0x4000F000UL
-#define NRF_WDT_BASE 0x40010000UL
-#define NRF_RTC1_BASE 0x40011000UL
-#define NRF_QDEC_BASE 0x40012000UL
-#define NRF_COMP_BASE 0x40013000UL
-#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_SWI0_BASE 0x40014000UL
-#define NRF_EGU0_BASE 0x40014000UL
-#define NRF_SWI1_BASE 0x40015000UL
-#define NRF_EGU1_BASE 0x40015000UL
-#define NRF_SWI2_BASE 0x40016000UL
-#define NRF_EGU2_BASE 0x40016000UL
-#define NRF_SWI3_BASE 0x40017000UL
-#define NRF_EGU3_BASE 0x40017000UL
-#define NRF_SWI4_BASE 0x40018000UL
-#define NRF_EGU4_BASE 0x40018000UL
-#define NRF_SWI5_BASE 0x40019000UL
-#define NRF_EGU5_BASE 0x40019000UL
-#define NRF_TIMER3_BASE 0x4001A000UL
-#define NRF_TIMER4_BASE 0x4001B000UL
-#define NRF_PWM0_BASE 0x4001C000UL
-#define NRF_PDM_BASE 0x4001D000UL
-#define NRF_NVMC_BASE 0x4001E000UL
-#define NRF_PPI_BASE 0x4001F000UL
-#define NRF_MWU_BASE 0x40020000UL
-#define NRF_PWM1_BASE 0x40021000UL
-#define NRF_PWM2_BASE 0x40022000UL
-#define NRF_SPIM2_BASE 0x40023000UL
-#define NRF_SPIS2_BASE 0x40023000UL
-#define NRF_SPI2_BASE 0x40023000UL
-#define NRF_RTC2_BASE 0x40024000UL
-#define NRF_I2S_BASE 0x40025000UL
-#define NRF_FPU_BASE 0x40026000UL
-#define NRF_P0_BASE 0x50000000UL
-
-
-/* ================================================================================ */
-/* ================ Peripheral declaration ================ */
-/* ================================================================================ */
-
-#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
-#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
-#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE)
-#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
-#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
-#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
-#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE)
-#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
-#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE)
-#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE)
-#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE)
-#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE)
-#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
-#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
-#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
-#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
-#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE)
-#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE)
-#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
-#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
-#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE)
-#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
-#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE)
-#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
-#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
-#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
-#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
-#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
-#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
-#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
-#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
-#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
-#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
-#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
-#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
-#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
-#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
-#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE)
-#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE)
-#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE)
-#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE)
-#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE)
-#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE)
-#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE)
-#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE)
-#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE)
-#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE)
-#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE)
-#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE)
-#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE)
-#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE)
-#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE)
-#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE)
-#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
-#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
-#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE)
-#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE)
-#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE)
-#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE)
-#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE)
-#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE)
-#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE)
-#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE)
-#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE)
-#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nrf52 */
-/** @} */ /* End of group Nordic Semiconductor */
-
#ifdef __cplusplus
}
#endif
+#endif /* NRF52_H */
+
-#endif /* nrf52_H */
+/** @} */ /* End of group nrf52 */
+/** @} */ /* End of group Nordic Semiconductor */
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
index 3d1c2227bc..e2f3a0bb01 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
@@ -1,4 +1,4 @@
-<?xml version="1.0" encoding="utf-8"?>
+<?xml version="1.0" encoding="utf-8"?>
<!-- File naming: <vendor>_<part/series name>_svd.xml -->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>Nordic Semiconductor</vendor>
@@ -6066,7 +6066,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<enumeratedValue>
<name>Neg30dBm</name>
<description>Deprecated enumerator - -40 dBm</description>
- <value>0xD8</value>
+ <value>0xFF</value>
</enumeratedValue>
<enumeratedValue>
<name>Neg40dBm</name>
@@ -13883,9 +13883,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPIM0">
<name>SPIM1</name>
<description>Serial Peripheral Interface Master with EasyDMA 1</description>
- <groupName>SPIM</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
<value>4</value>
@@ -13894,9 +13892,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPIS0">
<name>SPIS1</name>
<description>SPI Slave 1</description>
- <groupName>SPIS</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM1</alternatePeripheral>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
@@ -13906,9 +13902,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TWIM0">
<name>TWIM1</name>
<description>I2C compatible Two-Wire Master Interface with EasyDMA 1</description>
- <groupName>TWIM</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM1</alternatePeripheral>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
@@ -13918,9 +13912,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TWIS0">
<name>TWIS1</name>
<description>I2C compatible Two-Wire Slave Interface with EasyDMA 1</description>
- <groupName>TWIS</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM1</alternatePeripheral>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
@@ -13930,9 +13922,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPI0">
<name>SPI1</name>
<description>Serial Peripheral Interface 1</description>
- <groupName>SPI</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM1</alternatePeripheral>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
@@ -13942,9 +13932,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TWI0">
<name>TWI1</name>
<description>I2C compatible Two-Wire Interface 1</description>
- <groupName>TWI</groupName>
<baseAddress>0x40004000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM1</alternatePeripheral>
<interrupt>
<name>SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1</name>
@@ -19589,9 +19577,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TIMER0">
<name>TIMER1</name>
<description>Timer/Counter 1</description>
- <groupName>TIMER</groupName>
<baseAddress>0x40009000</baseAddress>
- <size>32</size>
<interrupt>
<name>TIMER1</name>
<value>9</value>
@@ -19600,9 +19586,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TIMER0">
<name>TIMER2</name>
<description>Timer/Counter 2</description>
- <groupName>TIMER</groupName>
<baseAddress>0x4000A000</baseAddress>
- <size>32</size>
<interrupt>
<name>TIMER2</name>
<value>10</value>
@@ -22510,9 +22494,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="RTC0">
<name>RTC1</name>
<description>Real time counter 1</description>
- <groupName>RTC</groupName>
<baseAddress>0x40011000</baseAddress>
- <size>32</size>
<interrupt>
<name>RTC1</name>
<value>17</value>
@@ -26146,9 +26128,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SWI0">
<name>SWI1</name>
<description>Software interrupt 1</description>
- <groupName>SWI</groupName>
<baseAddress>0x40015000</baseAddress>
- <size>32</size>
<interrupt>
<name>SWI1_EGU1</name>
<value>21</value>
@@ -26157,9 +26137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="EGU0">
<name>EGU1</name>
<description>Event Generator Unit 1</description>
- <groupName>EGU</groupName>
<baseAddress>0x40015000</baseAddress>
- <size>32</size>
<alternatePeripheral>SWI1</alternatePeripheral>
<interrupt>
<name>SWI1_EGU1</name>
@@ -26169,9 +26147,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SWI0">
<name>SWI2</name>
<description>Software interrupt 2</description>
- <groupName>SWI</groupName>
<baseAddress>0x40016000</baseAddress>
- <size>32</size>
<interrupt>
<name>SWI2_EGU2</name>
<value>22</value>
@@ -26180,9 +26156,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="EGU0">
<name>EGU2</name>
<description>Event Generator Unit 2</description>
- <groupName>EGU</groupName>
<baseAddress>0x40016000</baseAddress>
- <size>32</size>
<alternatePeripheral>SWI2</alternatePeripheral>
<interrupt>
<name>SWI2_EGU2</name>
@@ -26192,9 +26166,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SWI0">
<name>SWI3</name>
<description>Software interrupt 3</description>
- <groupName>SWI</groupName>
<baseAddress>0x40017000</baseAddress>
- <size>32</size>
<interrupt>
<name>SWI3_EGU3</name>
<value>23</value>
@@ -26203,9 +26175,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="EGU0">
<name>EGU3</name>
<description>Event Generator Unit 3</description>
- <groupName>EGU</groupName>
<baseAddress>0x40017000</baseAddress>
- <size>32</size>
<alternatePeripheral>SWI3</alternatePeripheral>
<interrupt>
<name>SWI3_EGU3</name>
@@ -26215,9 +26185,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SWI0">
<name>SWI4</name>
<description>Software interrupt 4</description>
- <groupName>SWI</groupName>
<baseAddress>0x40018000</baseAddress>
- <size>32</size>
<interrupt>
<name>SWI4_EGU4</name>
<value>24</value>
@@ -26226,9 +26194,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="EGU0">
<name>EGU4</name>
<description>Event Generator Unit 4</description>
- <groupName>EGU</groupName>
<baseAddress>0x40018000</baseAddress>
- <size>32</size>
<alternatePeripheral>SWI4</alternatePeripheral>
<interrupt>
<name>SWI4_EGU4</name>
@@ -26238,9 +26204,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SWI0">
<name>SWI5</name>
<description>Software interrupt 5</description>
- <groupName>SWI</groupName>
<baseAddress>0x40019000</baseAddress>
- <size>32</size>
<interrupt>
<name>SWI5_EGU5</name>
<value>25</value>
@@ -26249,9 +26213,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="EGU0">
<name>EGU5</name>
<description>Event Generator Unit 5</description>
- <groupName>EGU</groupName>
<baseAddress>0x40019000</baseAddress>
- <size>32</size>
<alternatePeripheral>SWI5</alternatePeripheral>
<interrupt>
<name>SWI5_EGU5</name>
@@ -26261,9 +26223,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TIMER0">
<name>TIMER3</name>
<description>Timer/Counter 3</description>
- <groupName>TIMER</groupName>
<baseAddress>0x4001A000</baseAddress>
- <size>32</size>
<interrupt>
<name>TIMER3</name>
<value>26</value>
@@ -26272,9 +26232,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="TIMER0">
<name>TIMER4</name>
<description>Timer/Counter 4</description>
- <groupName>TIMER</groupName>
<baseAddress>0x4001B000</baseAddress>
- <size>32</size>
<interrupt>
<name>TIMER4</name>
<value>27</value>
@@ -35665,9 +35623,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="PWM0">
<name>PWM1</name>
<description>Pulse Width Modulation Unit 1</description>
- <groupName>PWM</groupName>
<baseAddress>0x40021000</baseAddress>
- <size>32</size>
<interrupt>
<name>PWM1</name>
<value>33</value>
@@ -35676,9 +35632,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="PWM0">
<name>PWM2</name>
<description>Pulse Width Modulation Unit 2</description>
- <groupName>PWM</groupName>
<baseAddress>0x40022000</baseAddress>
- <size>32</size>
<interrupt>
<name>PWM2</name>
<value>34</value>
@@ -35687,9 +35641,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPIM0">
<name>SPIM2</name>
<description>Serial Peripheral Interface Master with EasyDMA 2</description>
- <groupName>SPIM</groupName>
<baseAddress>0x40023000</baseAddress>
- <size>32</size>
<interrupt>
<name>SPIM2_SPIS2_SPI2</name>
<value>35</value>
@@ -35698,9 +35650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPIS0">
<name>SPIS2</name>
<description>SPI Slave 2</description>
- <groupName>SPIS</groupName>
<baseAddress>0x40023000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM2</alternatePeripheral>
<interrupt>
<name>SPIM2_SPIS2_SPI2</name>
@@ -35710,9 +35660,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="SPI0">
<name>SPI2</name>
<description>Serial Peripheral Interface 2</description>
- <groupName>SPI</groupName>
<baseAddress>0x40023000</baseAddress>
- <size>32</size>
<alternatePeripheral>SPIM2</alternatePeripheral>
<interrupt>
<name>SPIM2_SPIS2_SPI2</name>
@@ -35722,9 +35670,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<peripheral derivedFrom="RTC0">
<name>RTC2</name>
<description>Real time counter 2</description>
- <groupName>RTC</groupName>
<baseAddress>0x40024000</baseAddress>
- <size>32</size>
<interrupt>
<name>RTC2</name>
<value>36</value>
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h
index c42d770464..168c0406c1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h
@@ -1,46 +1,40 @@
-
-/****************************************************************************************************//**
- * @file nrf52810.h
- *
- * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
- * nrf52810 from Nordic Semiconductor.
- *
- * @version V1
- * @date 8. March 2018
- *
- * @note Generated with SVDConv V2.81d
- * from CMSIS SVD File 'nrf52810.svd' Version 1,
- *
- * @par Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
+/*
+ * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
*
- *******************************************************************************************************/
+ * @file nrf52810.h
+ * @brief CMSIS HeaderFile
+ * @version 1
+ * @date 06. June 2018
+ * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39
+ * from File 'nrf52810.svd',
+ * last modified on Wednesday, 06.06.2018 13:21:35
+ */
@@ -48,10 +42,12 @@
* @{
*/
+
/** @addtogroup nrf52810
* @{
*/
+
#ifndef NRF52810_H
#define NRF52810_H
@@ -60,1520 +56,1791 @@ extern "C" {
#endif
-/* ------------------------- Interrupt Number Definition ------------------------ */
-
-typedef enum {
-/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
- and No Match */
- BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
- related Fault */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */
-/* --------------------- nrf52810 Specific Interrupt Numbers -------------------- */
- POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
- RADIO_IRQn = 1, /*!< 1 RADIO */
- UARTE0_IRQn = 2, /*!< 2 UARTE0 */
- TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */
- SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */
- GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
- SAADC_IRQn = 7, /*!< 7 SAADC */
- TIMER0_IRQn = 8, /*!< 8 TIMER0 */
- TIMER1_IRQn = 9, /*!< 9 TIMER1 */
- TIMER2_IRQn = 10, /*!< 10 TIMER2 */
- RTC0_IRQn = 11, /*!< 11 RTC0 */
- TEMP_IRQn = 12, /*!< 12 TEMP */
- RNG_IRQn = 13, /*!< 13 RNG */
- ECB_IRQn = 14, /*!< 14 ECB */
- CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
- WDT_IRQn = 16, /*!< 16 WDT */
- RTC1_IRQn = 17, /*!< 17 RTC1 */
- QDEC_IRQn = 18, /*!< 18 QDEC */
- COMP_IRQn = 19, /*!< 19 COMP */
- SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
- SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
- SWI2_IRQn = 22, /*!< 22 SWI2 */
- SWI3_IRQn = 23, /*!< 23 SWI3 */
- SWI4_IRQn = 24, /*!< 24 SWI4 */
- SWI5_IRQn = 25, /*!< 25 SWI5 */
- PWM0_IRQn = 28, /*!< 28 PWM0 */
- PDM_IRQn = 29 /*!< 29 PDM */
-} IRQn_Type;
-
-
/** @addtogroup Configuration_of_CMSIS
* @{
*/
-/* ================================================================================ */
-/* ================ Processor and Core Peripheral Section ================ */
-/* ================================================================================ */
-/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
-#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 0 /*!< FPU present or not */
-/** @} */ /* End of group Configuration_of_CMSIS */
+/* =========================================================================================================================== */
+/* ================ Interrupt Number Definition ================ */
+/* =========================================================================================================================== */
-#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
-#include "system_nrf52810.h" /*!< nrf52810 System */
+typedef enum {
+/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
+ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
+ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
+ and No Match */
+ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+ related Fault */
+ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
+ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
+ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
+ SysTick_IRQn = -1, /*!< -1 System Tick Timer */
+/* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */
+ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
+ RADIO_IRQn = 1, /*!< 1 RADIO */
+ UARTE0_IRQn = 2, /*!< 2 UARTE0 */
+ TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */
+ SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */
+ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
+ SAADC_IRQn = 7, /*!< 7 SAADC */
+ TIMER0_IRQn = 8, /*!< 8 TIMER0 */
+ TIMER1_IRQn = 9, /*!< 9 TIMER1 */
+ TIMER2_IRQn = 10, /*!< 10 TIMER2 */
+ RTC0_IRQn = 11, /*!< 11 RTC0 */
+ TEMP_IRQn = 12, /*!< 12 TEMP */
+ RNG_IRQn = 13, /*!< 13 RNG */
+ ECB_IRQn = 14, /*!< 14 ECB */
+ CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
+ WDT_IRQn = 16, /*!< 16 WDT */
+ RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
+ COMP_IRQn = 19, /*!< 19 COMP */
+ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
+ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
+ SWI2_IRQn = 22, /*!< 22 SWI2 */
+ SWI3_IRQn = 23, /*!< 23 SWI3 */
+ SWI4_IRQn = 24, /*!< 24 SWI4 */
+ SWI5_IRQn = 25, /*!< 25 SWI5 */
+ PWM0_IRQn = 28, /*!< 28 PWM0 */
+ PDM_IRQn = 29 /*!< 29 PDM */
+} IRQn_Type;
-/* ================================================================================ */
-/* ================ Device Specific Peripheral Section ================ */
-/* ================================================================================ */
+/* =========================================================================================================================== */
+/* ================ Processor and Core Peripheral Section ================ */
+/* =========================================================================================================================== */
-/** @addtogroup Device_Peripheral_Registers
- * @{
- */
+/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
+#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __FPU_PRESENT 0 /*!< FPU present or not */
+
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
+#include "system_nrf52810.h" /*!< nrf52810 System */
+
+#ifndef __IM /*!< Fallback for older CMSIS versions */
+ #define __IM __I
+#endif
+#ifndef __OM /*!< Fallback for older CMSIS versions */
+ #define __OM __O
+#endif
+#ifndef __IOM /*!< Fallback for older CMSIS versions */
+ #define __IOM __IO
+#endif
-/* ------------------- Start of section using anonymous unions ------------------ */
-#if defined(__CC_ARM)
+/* ======================================== Start of section using anonymous unions ======================================== */
+#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
-#elif defined(__ICCARM__)
+#elif defined (__ICCARM__)
#pragma language=extended
-#elif defined(__GNUC__)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+ #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
+ #pragma clang diagnostic ignored "-Wnested-anon-types"
+#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
#pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
+/* =========================================================================================================================== */
+/* ================ Device Specific Cluster Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_clusters
+ * @{
+ */
+
+
+/**
+ * @brief FICR_INFO [INFO] (Device info)
+ */
typedef struct {
- __I uint32_t PART; /*!< Part code */
- __I uint32_t VARIANT; /*!< Part variant, hardware version and production configuration */
- __I uint32_t PACKAGE; /*!< Package option */
- __I uint32_t RAM; /*!< RAM variant */
- __I uint32_t FLASH; /*!< Flash variant */
- __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */
-} FICR_INFO_Type;
+ __IM uint32_t PART; /*!< (@ 0x00000000) Part code */
+ __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production
+ configuration */
+ __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */
+ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */
+ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */
+ __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */
+} FICR_INFO_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients)
+ */
typedef struct {
- __I uint32_t A0; /*!< Slope definition A0 */
- __I uint32_t A1; /*!< Slope definition A1 */
- __I uint32_t A2; /*!< Slope definition A2 */
- __I uint32_t A3; /*!< Slope definition A3 */
- __I uint32_t A4; /*!< Slope definition A4 */
- __I uint32_t A5; /*!< Slope definition A5 */
- __I uint32_t B0; /*!< Y-intercept B0 */
- __I uint32_t B1; /*!< Y-intercept B1 */
- __I uint32_t B2; /*!< Y-intercept B2 */
- __I uint32_t B3; /*!< Y-intercept B3 */
- __I uint32_t B4; /*!< Y-intercept B4 */
- __I uint32_t B5; /*!< Y-intercept B5 */
- __I uint32_t T0; /*!< Segment end T0 */
- __I uint32_t T1; /*!< Segment end T1 */
- __I uint32_t T2; /*!< Segment end T2 */
- __I uint32_t T3; /*!< Segment end T3 */
- __I uint32_t T4; /*!< Segment end T4 */
-} FICR_TEMP_Type;
+ __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */
+ __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */
+ __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */
+ __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */
+ __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */
+ __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */
+ __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */
+ __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */
+ __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */
+ __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */
+ __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */
+ __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */
+ __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */
+ __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */
+ __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */
+ __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */
+ __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */
+} FICR_TEMP_Type; /*!< Size = 68 (0x44) */
+
+/**
+ * @brief POWER_RAM [RAM] (Unspecified)
+ */
typedef struct {
- __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */
- __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */
- __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */
- __I uint32_t RESERVED0;
-} POWER_RAM_Type;
+ __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register.
+ The RAM size will vary depending on product
+ variant, and the RAMn register will only
+ be present if the corresponding RAM AHB
+ slave is present on the device. */
+ __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set
+ register */
+ __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear
+ register */
+ __IM uint32_t RESERVED;
+} POWER_RAM_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief UARTE_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t RTS; /*!< Pin select for RTS signal */
- __IO uint32_t TXD; /*!< Pin select for TXD signal */
- __IO uint32_t CTS; /*!< Pin select for CTS signal */
- __IO uint32_t RXD; /*!< Pin select for RXD signal */
-} UARTE_PSEL_Type;
+ __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */
+ __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */
+ __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */
+ __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */
+} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief UARTE_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
-} UARTE_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief UARTE_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
-} UARTE_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+} UARTE_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief TWIM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCL; /*!< Pin select for SCL signal */
- __IO uint32_t SDA; /*!< Pin select for SDA signal */
-} TWIM_PSEL_Type;
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief TWIM_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} TWIM_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief TWIM_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} TWIM_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} TWIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief TWIS_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCL; /*!< Pin select for SCL signal */
- __IO uint32_t SDA; /*!< Pin select for SDA signal */
-} TWIS_PSEL_Type;
+ __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */
+ __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */
+} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief TWIS_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RXD Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */
-} TWIS_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */
+} TWIS_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief TWIS_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< TXD Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */
-} TWIS_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */
+} TWIS_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK */
- __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
- __IO uint32_t MISO; /*!< Pin select for MISO signal */
-} SPIM_PSEL_Type;
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */
+ __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */
+} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIM_RXD [RXD] (RXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} SPIM_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_RXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIM_TXD [TXD] (TXD EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
- __IO uint32_t LIST; /*!< EasyDMA list type */
-} SPIM_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */
+ __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */
+} SPIM_TXD_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIS_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t SCK; /*!< Pin select for SCK */
- __IO uint32_t MISO; /*!< Pin select for MISO signal */
- __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
- __IO uint32_t CSN; /*!< Pin select for CSN signal */
-} SPIS_PSEL_Type;
+ __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */
+ __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */
+ __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */
+ __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */
+} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SPIS_RXD [RXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RXD data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */
-} SPIS_RXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */
+} SPIS_RXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SPIS_TXD [TXD] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< TXD data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
- __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */
-} SPIS_TXD_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */
+} SPIS_TXD_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified)
+ */
typedef struct {
- __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
- __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
-} SAADC_EVENTS_CH_Type;
+ __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last results is equal
+ or above CH[n].LIMIT.HIGH */
+ __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last results is equal
+ or below CH[n].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief SAADC_CH [CH] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */
- __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */
- __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */
- __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
- a channel */
-} SAADC_CH_Type;
+ __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection
+ for CH[n] */
+ __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection
+ for CH[n] */
+ __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for
+ CH[n] */
+ __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event
+ monitoring a channel */
+} SAADC_CH_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Data pointer */
- __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */
- __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */
-} SAADC_RESULT_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */
+ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last
+ START */
+} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief QDEC_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t LED; /*!< Pin select for LED signal */
- __IO uint32_t A; /*!< Pin select for A signal */
- __IO uint32_t B; /*!< Pin select for B signal */
-} QDEC_PSEL_Type;
+ __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */
+ __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */
+ __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */
+} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */
+
+/**
+ * @brief PWM_SEQ [SEQ] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in RAM of this sequence */
- __IO uint32_t CNT; /*!< Description cluster[0]: Number of values (duty cycles) in this
- sequence */
- __IO uint32_t REFRESH; /*!< Description cluster[0]: Number of additional PWM periods between
- samples loaded into compare register */
- __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */
- __I uint32_t RESERVED1[4];
-} PWM_SEQ_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in
+ RAM of this sequence */
+ __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty
+ cycles) in this sequence */
+ __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional
+ PWM periods between samples loaded into
+ compare register */
+ __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the
+ sequence */
+ __IM uint32_t RESERVED[4];
+} PWM_SEQ_Type; /*!< Size = 32 (0x20) */
+
+/**
+ * @brief PWM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
- 0 */
-} PWM_PSEL_Type;
+ __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select
+ for PWM channel n */
+} PWM_PSEL_Type; /*!< Size = 16 (0x10) */
+
+/**
+ * @brief PDM_PSEL [PSEL] (Unspecified)
+ */
typedef struct {
- __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */
- __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */
-} PDM_PSEL_Type;
+ __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */
+ __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */
+} PDM_PSEL_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PDM_SAMPLE [SAMPLE] (Unspecified)
+ */
typedef struct {
- __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */
- __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */
-} PDM_SAMPLE_Type;
+ __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with
+ EasyDMA */
+ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA
+ mode */
+} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
+ */
typedef struct {
- __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */
- __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */
-} PPI_TASKS_CHG_Type;
+ __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group
+ n */
+ __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group
+ n */
+} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_CH [CH] (PPI Channel)
+ */
typedef struct {
- __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */
- __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
-} PPI_CH_Type;
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */
+} PPI_CH_Type; /*!< Size = 8 (0x8) */
+
+/**
+ * @brief PPI_FORK [FORK] (Fork)
+ */
typedef struct {
- __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
-} PPI_FORK_Type;
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */
+} PPI_FORK_Type; /*!< Size = 4 (0x4) */
-/* ================================================================================ */
-/* ================ FICR ================ */
-/* ================================================================================ */
+/** @} */ /* End of group Device_Peripheral_clusters */
-/**
- * @brief Factory information configuration registers (FICR)
+/* =========================================================================================================================== */
+/* ================ Device Specific Peripheral Section ================ */
+/* =========================================================================================================================== */
+
+
+/** @addtogroup Device_Peripheral_peripherals
+ * @{
(This diff was longer than 20,000 lines, and has been truncated...)
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