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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/04/02 11:08:46 UTC
[incubator-nuttx] branch master updated (497d24f -> 27c80f2)
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 497d24f timerexpiration:fix DEADCODE when RR_INTERVAL or SCHED_SPORADIC not select
new 7a209e6 arch/riscv: Align the macro definition in csr.h
new 629d996 arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
new 79aca28 arch/riscv: Remove riscv_sbi.c since it doesn't exist
new be2fee7 arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
new e959775 arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
new 27c80f2 arch/riscv: Rename g_scratch to g_percpu
The 6 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/include/csr.h | 86 +++++++++++-----------
arch/risc-v/include/mode.h | 2 +
arch/risc-v/include/syscall.h | 2 +-
arch/risc-v/src/common/riscv_exception_common.S | 2 +-
arch/risc-v/src/common/riscv_internal.h | 2 +-
.../{riscv_exception_macros.S => riscv_macros.S} | 4 +-
arch/risc-v/src/common/riscv_percpu.c | 15 ++--
arch/risc-v/src/common/riscv_swint.c | 2 +-
arch/risc-v/src/common/supervisor/Make.defs | 4 +-
.../src/common/supervisor/riscv_syscall_dispatch.S | 16 ++--
10 files changed, 69 insertions(+), 66 deletions(-)
rename arch/risc-v/src/common/{riscv_exception_macros.S => riscv_macros.S} (98%)
[incubator-nuttx] 06/06: arch/riscv: Rename g_scratch to g_percpu
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 27c80f2586096d56b3b5407f464dc1aa762fd2b8
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:39:06 2022 +0800
arch/riscv: Rename g_scratch to g_percpu
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/src/common/riscv_percpu.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_percpu.c b/arch/risc-v/src/common/riscv_percpu.c
index 5e45c89..a10164b 100644
--- a/arch/risc-v/src/common/riscv_percpu.c
+++ b/arch/risc-v/src/common/riscv_percpu.c
@@ -44,7 +44,7 @@
* Private Data
****************************************************************************/
-static struct riscv_percpu_s g_scratch[HART_CNT];
+static struct riscv_percpu_s g_percpu[HART_CNT];
/****************************************************************************
* Public Functions
@@ -61,11 +61,11 @@ static struct riscv_percpu_s g_scratch[HART_CNT];
void riscv_percpu_init(void)
{
- int i;
+ uintptr_t i;
for (i = 0; i < HART_CNT; i++)
{
- g_scratch[i].hartid = i;
+ g_percpu[i].hartid = i;
}
}
@@ -88,7 +88,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
/* Set the scratch register value to point to the scratch area */
- WRITE_CSR(CSR_SCRATCH, &g_scratch[hartid]);
+ WRITE_CSR(CSR_SCRATCH, &g_percpu[hartid]);
/* Make sure it sticks */
@@ -111,8 +111,8 @@ uintptr_t riscv_percpu_get_hartid(void)
{
uintptr_t scratch = READ_CSR(CSR_SCRATCH);
- DEBUGASSERT(scratch >= (uintptr_t) &g_scratch &&
- scratch <= (uintptr_t) &g_scratch + sizeof(g_scratch));
+ DEBUGASSERT(scratch >= (uintptr_t) &g_percpu &&
+ scratch < (uintptr_t) &g_percpu + sizeof(g_percpu));
return ((struct riscv_percpu_s *)scratch)->hartid;
}
[incubator-nuttx] 03/06: arch/riscv: Remove riscv_sbi.c since it doesn't exist
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 79aca28bd7ee1a5d095dab24bedf6765c12e2fae
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:13:55 2022 +0800
arch/riscv: Remove riscv_sbi.c since it doesn't exist
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/src/common/supervisor/Make.defs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/risc-v/src/common/supervisor/Make.defs b/arch/risc-v/src/common/supervisor/Make.defs
index 21b4278..e3125b0 100644
--- a/arch/risc-v/src/common/supervisor/Make.defs
+++ b/arch/risc-v/src/common/supervisor/Make.defs
@@ -21,7 +21,7 @@
# If the NuttX kernel runs in S-mode
CMN_ASRCS += riscv_dispatch_syscall.S
-CMN_CSRCS += riscv_sbi.c riscv_perform_syscall.c
+CMN_CSRCS += riscv_perform_syscall.c
CMN_CSRCS += riscv_percpu.c
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common$(DELIM)supervisor}
[incubator-nuttx] 04/06: arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit be2fee7d6effb76de20098097f304ffa3fa346bc
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:16:48 2022 +0800
arch/riscv: Rename riscv_exception_macros.S to riscv_macros.S
since macro defined in this file is also used in the normal context
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/src/common/riscv_exception_common.S | 2 +-
arch/risc-v/src/common/{riscv_exception_macros.S => riscv_macros.S} | 4 ++--
arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index f0603f9..bc2cb9b 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -28,7 +28,7 @@
#include <arch/irq.h>
#include <arch/mode.h>
-#include "riscv_exception_macros.S"
+#include "riscv_macros.S"
/****************************************************************************
* Pre-processor Definitions
diff --git a/arch/risc-v/src/common/riscv_exception_macros.S b/arch/risc-v/src/common/riscv_macros.S
similarity index 98%
rename from arch/risc-v/src/common/riscv_exception_macros.S
rename to arch/risc-v/src/common/riscv_macros.S
index d2f3291..2243698 100644
--- a/arch/risc-v/src/common/riscv_exception_macros.S
+++ b/arch/risc-v/src/common/riscv_macros.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/supervisor/riscv_exception_macros.S
+ * arch/risc-v/src/common/riscv_macros.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,7 +18,7 @@
*
****************************************************************************/
-.file "riscv_exception_macros.S"
+.file "riscv_macros.S"
/****************************************************************************
* Included Files
diff --git a/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S b/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
index ed8a635..791048e 100644
--- a/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
+++ b/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
@@ -27,7 +27,7 @@
#include <nuttx/config.h>
#include <arch/mode.h>
-#include "riscv_exception_macros.S"
+#include "riscv_macros.S"
/****************************************************************************
* Pre-processor Definitions
[incubator-nuttx] 01/06: arch/riscv: Align the macro definition in csr.h
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7a209e6ee89530fdff8e731d7c9e4c58f753ab10
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:09:23 2022 +0800
arch/riscv: Align the macro definition in csr.h
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/include/csr.h | 86 +++++++++++++++++++++++------------------------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/risc-v/include/csr.h b/arch/risc-v/include/csr.h
index ea17adb..e719b2a 100644
--- a/arch/risc-v/include/csr.h
+++ b/arch/risc-v/include/csr.h
@@ -299,51 +299,51 @@
/* In mstatus register */
-#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */
-#define MSTATUS_SIE (0x1 << 1) /* Supervisor Interrupt Enable */
-#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
-#define MSTATUS_SPIE (0x1 << 5) /* Supervisor Previous Interrupt Enable */
-#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
-#define MSTATUS_SPPU (0x0 << 8) /* Supervisor Previous Privilege (u-mode) */
-#define MSTATUS_SPPS (0x1 << 8) /* Supervisor Previous Privilege (s-mode) */
-#define MSTATUS_MPPU (0x0 << 11) /* Machine Previous Privilege (u-mode) */
-#define MSTATUS_MPPS (0x1 << 11) /* Machine Previous Privilege (s-mode) */
-#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
-#define MSTATUS_MPP_MASK (0x3 << 11)
-#define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */
-#define MSTATUS_FS_INIT (0x1 << 13)
-#define MSTATUS_FS_CLEAN (0x2 << 13)
-#define MSTATUS_FS_DIRTY (0x3 << 13)
-#define MSTATUS_MPRV (0x1 << 17) /* Modify Privilege */
-#define MSTATUS_SUM (0x1 << 18) /* S mode access to U mode memory */
-#define MSTATUS_MXR (0x1 << 19) /* Make executable / readable */
-#define MSTATUS_TVM (0x1 << 20) /* Trap access to satp from S mode */
-#define MSTATUS_TW (0x1 << 21) /* Trap WFI instruction from S mode */
-#define MSTATUS_TSR (0x1 << 22) /* Trap supervisor return (sret) */
+#define MSTATUS_UIE (0x1 << 0) /* User Interrupt Enable */
+#define MSTATUS_SIE (0x1 << 1) /* Supervisor Interrupt Enable */
+#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
+#define MSTATUS_SPIE (0x1 << 5) /* Supervisor Previous Interrupt Enable */
+#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
+#define MSTATUS_SPPU (0x0 << 8) /* Supervisor Previous Privilege (u-mode) */
+#define MSTATUS_SPPS (0x1 << 8) /* Supervisor Previous Privilege (s-mode) */
+#define MSTATUS_MPPU (0x0 << 11) /* Machine Previous Privilege (u-mode) */
+#define MSTATUS_MPPS (0x1 << 11) /* Machine Previous Privilege (s-mode) */
+#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
+#define MSTATUS_MPP_MASK (0x3 << 11)
+#define MSTATUS_FS (0x3 << 13) /* Machine Floating-point Status */
+#define MSTATUS_FS_INIT (0x1 << 13)
+#define MSTATUS_FS_CLEAN (0x2 << 13)
+#define MSTATUS_FS_DIRTY (0x3 << 13)
+#define MSTATUS_MPRV (0x1 << 17) /* Modify Privilege */
+#define MSTATUS_SUM (0x1 << 18) /* S mode access to U mode memory */
+#define MSTATUS_MXR (0x1 << 19) /* Make executable / readable */
+#define MSTATUS_TVM (0x1 << 20) /* Trap access to satp from S mode */
+#define MSTATUS_TW (0x1 << 21) /* Trap WFI instruction from S mode */
+#define MSTATUS_TSR (0x1 << 22) /* Trap supervisor return (sret) */
/* Mask of preserved bits for mstatus */
#ifdef CONFIG_ARCH_RV32
-#define MSTATUS_WPRI (0xff << 23 | 0x15)
+#define MSTATUS_WPRI (0xff << 23 | 0x15)
#else
-#define MSTATUS_WPRI (UINT64_C(0x1ffffff) << 38 | UINT64_C(0x1ff) << 23 | 0x15)
+#define MSTATUS_WPRI (UINT64_C(0x1ffffff) << 38 | UINT64_C(0x1ff) << 23 | 0x15)
#endif
/* In mie (machine interrupt enable) register */
-#define MIE_SSIE (0x1 << 1) /* Supervisor Software Interrupt Enable */
-#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
-#define MIE_STIE (0x1 << 5) /* Supervisor Timer Interrupt Enable */
-#define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */
-#define MIE_SEIE (0x1 << 9) /* Supervisor External Interrupt Enable */
-#define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */
+#define MIE_SSIE (0x1 << 1) /* Supervisor Software Interrupt Enable */
+#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
+#define MIE_STIE (0x1 << 5) /* Supervisor Timer Interrupt Enable */
+#define MIE_MTIE (0x1 << 7) /* Machine Timer Interrupt Enable */
+#define MIE_SEIE (0x1 << 9) /* Supervisor External Interrupt Enable */
+#define MIE_MEIE (0x1 << 11) /* Machine External Interrupt Enable */
/* In mip (machine interrupt pending) register */
-#define MIP_SSIP (0x1 << 1)
-#define MIP_STIP (0x1 << 5)
-#define MIP_MTIP (0x1 << 7)
-#define MIP_SEIP (0x1 << 9)
+#define MIP_SSIP (0x1 << 1)
+#define MIP_STIP (0x1 << 5)
+#define MIP_MTIP (0x1 << 7)
+#define MIP_SEIP (0x1 << 9)
/* In sstatus register (which is a view of mstatus) */
@@ -372,16 +372,16 @@
/* In pmpcfg (PMP configuration) register */
-#define PMPCFG_R (1 << 0) /* readable ? */
-#define PMPCFG_W (1 << 1) /* writable ? */
-#define PMPCFG_X (1 << 2) /* executable ? */
-#define PMPCFG_RWX_MASK (7 << 0) /* access rights mask */
-#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
-#define PMPCFG_A_TOR (1 << 3) /* top of range */
-#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
-#define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */
-#define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */
-#define PMPCFG_L (1 << 7) /* locked ? */
+#define PMPCFG_R (1 << 0) /* readable ? */
+#define PMPCFG_W (1 << 1) /* writable ? */
+#define PMPCFG_X (1 << 2) /* executable ? */
+#define PMPCFG_RWX_MASK (7 << 0) /* access rights mask */
+#define PMPCFG_A_OFF (0 << 3) /* null region (disabled) */
+#define PMPCFG_A_TOR (1 << 3) /* top of range */
+#define PMPCFG_A_NA4 (2 << 3) /* naturally aligned four-byte region */
+#define PMPCFG_A_NAPOT (3 << 3) /* naturally aligned power-of-two region */
+#define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */
+#define PMPCFG_L (1 << 7) /* locked ? */
/****************************************************************************
* Public Types
[incubator-nuttx] 02/06: arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 629d9969dd0f62beca4dec5a2719a041f97bee01
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:11:58 2022 +0800
arch/riscv: Rename riscv_syscall_dispatch to riscv_dispatch_syscall
follow other function naming(e.g. riscv_dispatch_irq)
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/include/syscall.h | 2 +-
arch/risc-v/src/common/riscv_internal.h | 2 +-
arch/risc-v/src/common/riscv_swint.c | 2 +-
arch/risc-v/src/common/supervisor/Make.defs | 2 +-
arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S | 14 +++++++-------
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/risc-v/include/syscall.h b/arch/risc-v/include/syscall.h
index 0a212a6..bf16ffe 100644
--- a/arch/risc-v/include/syscall.h
+++ b/arch/risc-v/include/syscall.h
@@ -128,7 +128,7 @@
# define ASM_SYS_CALL \
" addi sp, sp, -16\n" /* Make room */ \
REGSTORE " ra, 0(sp)\n" /* Save ra */ \
- " jal ra, riscv_syscall_dispatch\n" /* Dispatch (modifies ra) */ \
+ " jal ra, riscv_dispatch_syscall\n" /* Dispatch (modifies ra) */ \
REGLOAD " ra, 0(sp)\n" /* Restore ra */ \
" addi sp, sp, 16\n" /* Restore sp */
#else
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index 976a7f6..a19f1f8 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -319,7 +319,7 @@ uintptr_t riscv_mhartid(void);
/* If kernel runs in Supervisor mode, a system call trampoline is needed */
#ifdef CONFIG_ARCH_USE_S_MODE
-void riscv_syscall_dispatch(void) noreturn_function;
+void riscv_dispatch_syscall(void) noreturn_function;
void *riscv_perform_syscall(uintptr_t *regs);
#endif
diff --git a/arch/risc-v/src/common/riscv_swint.c b/arch/risc-v/src/common/riscv_swint.c
index c01866d..982d80a 100644
--- a/arch/risc-v/src/common/riscv_swint.c
+++ b/arch/risc-v/src/common/riscv_swint.c
@@ -129,7 +129,7 @@ static void dispatch_syscall(void)
"mv a2, a0\n" /* a2=Save return value in a0 */
"li a0, 3\n" /* a0=SYS_syscall_return (3) */
#ifdef CONFIG_ARCH_USE_S_MODE
- " j riscv_syscall_dispatch" /* Return from the syscall */
+ "j riscv_dispatch_syscall" /* Return from the syscall */
#else
" ecall" /* Return from the syscall */
#endif
diff --git a/arch/risc-v/src/common/supervisor/Make.defs b/arch/risc-v/src/common/supervisor/Make.defs
index 3146d4e..21b4278 100644
--- a/arch/risc-v/src/common/supervisor/Make.defs
+++ b/arch/risc-v/src/common/supervisor/Make.defs
@@ -20,7 +20,7 @@
# If the NuttX kernel runs in S-mode
-CMN_ASRCS += riscv_syscall_dispatch.S
+CMN_ASRCS += riscv_dispatch_syscall.S
CMN_CSRCS += riscv_sbi.c riscv_perform_syscall.c
CMN_CSRCS += riscv_percpu.c
diff --git a/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S b/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
index 5e2fd2f..ed8a635 100644
--- a/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
+++ b/arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/common/supervisor/riscv_syscall_dispatch.S
+ * arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,7 +18,7 @@
*
****************************************************************************/
-.file "riscv_syscall_dispatch.S"
+.file "riscv_dispatch_syscall.S"
/****************************************************************************
* Included Files
@@ -37,16 +37,16 @@
* Public Symbols
****************************************************************************/
- .globl riscv_syscall_dispatch
+ .globl riscv_dispatch_syscall
/****************************************************************************
- * Name: riscv_syscall_dispatch
+ * Name: riscv_dispatch_syscall
*
* Description:
* Dispatch syscall from kernel
*
* C Function Prototype:
- * void riscv_syscall_dispatch(void);
+ * void riscv_dispatch_syscall(void);
*
* Input Parameters:
* Assumes the context to return is already set up
@@ -59,9 +59,9 @@
*
****************************************************************************/
-.type riscv_syscall_dispatch, function
+.type riscv_dispatch_syscall, function
-riscv_syscall_dispatch:
+riscv_dispatch_syscall:
addi sp, sp, -XCPTCONTEXT_SIZE /* make room */
save_ctx sp /* save current context */
[incubator-nuttx] 05/06: arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e959775397a1b53b2f2a7d436b634a4d5c2a1597
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sat Apr 2 05:37:00 2022 +0800
arch/riscv: Access [m|s]scratch through CSR_SCRATCH macro
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/risc-v/include/mode.h | 2 ++
arch/risc-v/src/common/riscv_percpu.c | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/risc-v/include/mode.h b/arch/risc-v/include/mode.h
index 144fd73..e4b3c40 100644
--- a/arch/risc-v/include/mode.h
+++ b/arch/risc-v/include/mode.h
@@ -37,6 +37,7 @@
/* CSR definitions */
# define CSR_STATUS sstatus /* Global status register */
+# define CSR_SCRATCH sscratch /* Scratch register */
# define CSR_EPC sepc /* Exception program counter */
# define CSR_IE sie /* Interrupt enable register */
# define CSR_CAUSE scause /* Interrupt cause register */
@@ -69,6 +70,7 @@
/* CSR definitions */
# define CSR_STATUS mstatus /* Global status register */
+# define CSR_SCRATCH mscratch /* Scratch register */
# define CSR_EPC mepc /* Exception program counter */
# define CSR_IE mie /* Interrupt enable register */
# define CSR_CAUSE mcause /* Interrupt cause register */
diff --git a/arch/risc-v/src/common/riscv_percpu.c b/arch/risc-v/src/common/riscv_percpu.c
index 25e4ef9..5e45c89 100644
--- a/arch/risc-v/src/common/riscv_percpu.c
+++ b/arch/risc-v/src/common/riscv_percpu.c
@@ -26,6 +26,7 @@
#include <nuttx/irq.h>
#include <arch/barriers.h>
+#include <arch/mode.h>
#include <assert.h>
#include <stdint.h>
@@ -87,7 +88,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
/* Set the scratch register value to point to the scratch area */
- WRITE_CSR(sscratch, &g_scratch[hartid]);
+ WRITE_CSR(CSR_SCRATCH, &g_scratch[hartid]);
/* Make sure it sticks */
@@ -108,7 +109,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
uintptr_t riscv_percpu_get_hartid(void)
{
- uintptr_t scratch = READ_CSR(sscratch);
+ uintptr_t scratch = READ_CSR(CSR_SCRATCH);
DEBUGASSERT(scratch >= (uintptr_t) &g_scratch &&
scratch <= (uintptr_t) &g_scratch + sizeof(g_scratch));