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Posted to commits@mynewt.apache.org by vi...@apache.org on 2016/10/10 19:27:02 UTC
[46/50] [abbrv] incubator-mynewt-core git commit: MYNEWT-391 STM32F4
ADC driver and ADC HAL support
MYNEWT-391 STM32F4 ADC driver and ADC HAL support
- Changing driver to work with config
- Adding deinit gpio to STM32F4 HAL
- Adding support for ADCs to the bsp and adding a default config for
them
- The linked script for the olimex used CCRAM for _ccram_start, we
should be using CCM instead.
- Resolving some compiler warnings.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/82767ae9
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/82767ae9
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/82767ae9
Branch: refs/heads/sterly_refactor
Commit: 82767ae9af389bc15f9769f1a02312923b52443f
Parents: 082a033
Author: Vipul Rahane <vi...@runtime.io>
Authored: Tue Sep 20 18:03:01 2016 -0700
Committer: Vipul Rahane <vi...@runtime.io>
Committed: Thu Sep 22 20:21:03 2016 -0700
----------------------------------------------------------------------
apps/sblinky/pkg.yml | 4 -
apps/sblinky/src/main.c | 176 +++++--
.../include/adc_stm32f4/adc_stm32f4.h | 36 +-
drivers/adc/adc_stm32f4/pkg.yml | 4 +-
drivers/adc/adc_stm32f4/src/adc_stm32f4.c | 522 +++++++++++++++++--
drivers/adc/include/adc/adc.h | 5 +
drivers/adc/pkg.yml | 2 +-
.../olimex_stm32-e407_devboard.ld | 2 +-
hw/bsp/olimex_stm32-e407_devboard/pkg.yml | 33 +-
hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c | 163 ++++++
.../include/mcu/stm32f4xx_mynewt_hal.h | 1 +
hw/mcu/stm/stm32f4xx/pkg.yml | 2 +-
hw/mcu/stm/stm32f4xx/src/hal_gpio.c | 33 +-
hw/mcu/stm/stm32f4xx/src/hal_spi.c | 4 +-
14 files changed, 874 insertions(+), 113 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/apps/sblinky/pkg.yml
----------------------------------------------------------------------
diff --git a/apps/sblinky/pkg.yml b/apps/sblinky/pkg.yml
index 9bc7c96..a1bab7e 100644
--- a/apps/sblinky/pkg.yml
+++ b/apps/sblinky/pkg.yml
@@ -24,12 +24,8 @@ pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
-pkg.req_apis:
- - ADC_HW_IMPL
-
pkg.deps:
- libs/newtmgr
- - hw/mcu/nordic
- drivers/adc
- fs/nffs
- libs/console/full
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/apps/sblinky/src/main.c
----------------------------------------------------------------------
diff --git a/apps/sblinky/src/main.c b/apps/sblinky/src/main.c
index f9799be..280f410 100755
--- a/apps/sblinky/src/main.c
+++ b/apps/sblinky/src/main.c
@@ -32,24 +32,33 @@
#ifdef ARCH_sim
#include <mcu/mcu_sim.h>
#endif
-#include "nrf.h"
-#include "app_util_platform.h"
-#include "app_error.h"
#ifdef NRF51
+#include "nrf.h"
#include <adc_nrf51/adc_nrf51.h>
#include "nrf_drv_adc.h"
+#include "app_util_platform.h"
+#include "app_error.h"
nrf_drv_adc_config_t adc_config = NRF_DRV_ADC_DEFAULT_CONFIG;
nrf_drv_adc_channel_t g_nrf_adc_chan =
NRF_DRV_ADC_DEFAULT_CHANNEL(NRF_ADC_CONFIG_INPUT_2);
#endif
#ifdef NRF52
+#include "nrf.h"
#include <adc_nrf52/adc_nrf52.h>
#include "nrf_drv_saadc.h"
+#include "app_util_platform.h"
+#include "app_error.h"
nrf_drv_saadc_config_t adc_config = NRF_DRV_SAADC_DEFAULT_CONFIG;
#endif
+#ifdef STM32F4
+#include "stm32f4xx_hal_dma.h"
+#include "stm32f4xx_hal_adc.h"
+#include <adc_stm32f4/adc_stm32f4.h>
+#endif
+
#if defined(NRF52) || defined(NRF51)
/* The spi txrx callback */
struct sblinky_spi_cb_arg
@@ -162,7 +171,7 @@ sblinky_spi_irqs_handler(void *arg, int len)
void
sblinky_spi_cfg(int spi_num)
{
- int spi_id;
+ int spi_id = 0;
struct hal_spi_settings my_spi;
#if MYNEWT_VAL(SPI_MASTER)
@@ -189,8 +198,6 @@ sblinky_spi_cfg(int spi_num)
hal_spi_config(spi_id, &my_spi);
}
-struct adc_dev my_dev;
-
#if 0
#define SAADC_SAMPLES_IN_BUFFER (4)
static nrf_saadc_value_t m_buffer_pool[2][SAADC_SAMPLES_IN_BUFFER];
@@ -227,29 +234,40 @@ saadc_test(void)
}
#endif
-#define ADC_NUMBER_SAMPLES (2)
+
+#define ADC_NUMBER_SAMPLES (16)
#define ADC_NUMBER_CHANNELS (1)
+#if MYNEWT_VAL(ADC_3)
+
+#define STM32F4_ADC_DEFAULT_CHAN_CFG {\
+ .Channel = ADC_CHANNEL_4,\
+ .Rank = 1,\
+ .SamplingTime = ADC_SAMPLETIME_144CYCLES,\
+ .Offset = 0\
+}
+
+ADC_ChannelConfTypeDef adc_chan_cfg = STM32F4_ADC_DEFAULT_CHAN_CFG;
+
uint8_t *sample_buffer1;
uint8_t *sample_buffer2;
-int adc_result;
-int my_result_mv;
+int adc3_result;
+int my_result_mv3[ADC_NUMBER_SAMPLES];
int
-adc_read_event(struct adc_dev *dev, void *arg, uint8_t etype,
+adc3_read_event(struct adc_dev *dev, void *arg, uint8_t etype,
void *buffer, int buffer_len)
{
int i;
- //int result;
int rc;
for (i = 0; i < ADC_NUMBER_SAMPLES; i++) {
- rc = adc_buf_read(dev, buffer, buffer_len, i, &adc_result);
+ rc = adc_buf_read(dev, buffer, buffer_len, i, &adc3_result);
if (rc != 0) {
goto err;
}
- my_result_mv = adc_result_mv(dev, 0, adc_result);
+ my_result_mv3[i] = adc_result_mv(dev, ADC_CHANNEL_4, adc3_result);
}
adc_buf_release(dev, buffer, buffer_len);
@@ -258,13 +276,57 @@ adc_read_event(struct adc_dev *dev, void *arg, uint8_t etype,
err:
return (rc);
}
+#endif
+
+#if MYNEWT_VAL(ADC_1)
+
+#define STM32F4_ADC_DEFAULT_CHAN_CFG10 {\
+ .Channel = ADC_CHANNEL_10,\
+ .Rank = 1,\
+ .SamplingTime = ADC_SAMPLETIME_144CYCLES,\
+ .Offset = 0\
+}
+
+ADC_ChannelConfTypeDef adc_chan_cfg10 = STM32F4_ADC_DEFAULT_CHAN_CFG10;
+
+int adc1_result;
+int my_result_mv1[ADC_NUMBER_SAMPLES];
+uint8_t *sample_buffer3;
+uint8_t *sample_buffer4;
+int
+adc1_read_event(struct adc_dev *dev, void *arg, uint8_t etype,
+ void *buffer, int buffer_len)
+{
+ int i;
+ int rc;
+
+ for (i = 0; i < ADC_NUMBER_SAMPLES; i++) {
+ rc = adc_buf_read(dev, buffer, buffer_len, i, &adc1_result);
+ if (rc != 0) {
+ goto err;
+ }
+ my_result_mv1[i] = adc_result_mv(dev, ADC_CHANNEL_10, adc1_result);
+ }
+
+ adc_buf_release(dev, buffer, buffer_len);
+
+ return (0);
+err:
+ return (rc);
+}
+#endif
void
task1_handler(void *arg)
{
- int rc;
struct os_task *t;
- struct adc_dev *adc;
+#if MYNEWT_VAL(ADC_3)
+ struct adc_dev *adc3;
+#endif
+#if MYNEWT_VAL(ADC_1)
+ struct adc_dev *adc1;
+#endif
+
#if MYNEWT_VAL(SPI_MASTER)
int i;
uint8_t last_val;
@@ -281,14 +343,31 @@ task1_handler(void *arg)
g_led_pin = LED_BLINK_PIN;
hal_gpio_init_out(g_led_pin, 1);
- adc = (struct adc_dev *) os_dev_open("adc0", 1, &adc_config);
- assert(adc != NULL);
+#if MYNEWT_VAL(ADC_3)
+ adc3 = (struct adc_dev *) os_dev_open("adc3", 1, NULL);
+ assert(adc3 != NULL);
+#endif
+
+#if MYNEWT_VAL(ADC_1)
+ adc1 = (struct adc_dev *) os_dev_open("adc1", 1, NULL);
+ assert(adc1 != NULL);
+#endif
#ifdef NRF51
- adc_chan_config(adc, 0, &g_nrf_adc_chan);
+ adc_chan_config(adc3, 0, &g_nrf_adc_chan);
#endif
+
#ifdef NRF52
- adc_chan_config(adc, 0, &cc);
+ adc_chan_config(adc3, 0, &cc);
+#endif
+
+#ifdef STM32F4
+#if MYNEWT_VAL(ADC_3)
+ adc_chan_config(adc3, ADC_CHANNEL_4, &adc_chan_cfg);
+#endif
+#if MYNEWT_VAL(ADC_1)
+ adc_chan_config(adc1, ADC_CHANNEL_10, &adc_chan_cfg10);
+#endif
#endif
#if MYNEWT_VAL(SPI_MASTER)
@@ -298,6 +377,7 @@ task1_handler(void *arg)
hal_spi_enable(0);
#if 1
+ int rc;
/* Send some bytes in a non-blocking manner to SPI using tx val */
g_spi_tx_buf[0] = 0xde;
g_spi_tx_buf[1] = 0xad;
@@ -347,30 +427,56 @@ task1_handler(void *arg)
rc = hal_spi_txrx(SPI_SLAVE_ID, g_spi_tx_buf, g_spi_rx_buf, 32);
assert(rc == 0);
#endif
+#if MYNEWT_VAL(ADC_3)
+ sample_buffer1 = malloc(adc_buf_size(adc3, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ sample_buffer2 = malloc(adc_buf_size(adc3, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ memset(sample_buffer1, 0, adc_buf_size(adc3, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ memset(sample_buffer2, 0, adc_buf_size(adc3, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+#endif
- sample_buffer1 = malloc(adc_buf_size(adc, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
- sample_buffer2 = malloc(adc_buf_size(adc, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
- memset(sample_buffer1, 0, adc_buf_size(adc, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
- memset(sample_buffer2, 0, adc_buf_size(adc, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+#if MYNEWT_VAL(ADC_1)
+ sample_buffer3 = malloc(adc_buf_size(adc1, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ sample_buffer4 = malloc(adc_buf_size(adc1, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ memset(sample_buffer3, 0, adc_buf_size(adc1, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ memset(sample_buffer4, 0, adc_buf_size(adc1, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+#endif
#if 1
- adc_buf_set(adc, sample_buffer1, sample_buffer2,
- adc_buf_size(adc, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
- adc_event_handler_set(adc, adc_read_event, (void *) NULL);
+#if MYNEWT_VAL(ADC_3)
+ adc_buf_set(adc3, sample_buffer1, sample_buffer2,
+ adc_buf_size(adc3, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ adc_event_handler_set(adc3, adc3_read_event, NULL);
#endif
-#if 0
- rc = adc_chan_read(adc, 0, &g_result);
- assert(rc == 0);
- g_result_mv = adc_result_mv(adc, 0, g_result);
+#if MYNEWT_VAL(ADC_1)
+ adc_buf_set(adc1, sample_buffer3, sample_buffer4,
+ adc_buf_size(adc1, ADC_NUMBER_CHANNELS, ADC_NUMBER_SAMPLES));
+ adc_event_handler_set(adc1, adc1_read_event, NULL);
+#endif
#endif
while (1) {
t = os_sched_get_current_task();
assert(t->t_func == task1_handler);
- adc_sample(adc);
+#if 0
+ int rc;
+ rc = adc_chan_read(adc, 4, &g_result);
+ assert(rc == 0);
+ g_result_mv = adc_result_mv(adc, 4, g_result);
+#endif
+ int rc;
+ rc = OS_OK;
+
+#if MYNEWT_VAL(ADC_3)
+ rc = adc_sample(adc3);
+ assert(rc == OS_OK);
+#endif
+#if MYNEWT_VAL(ADC_1)
+ rc = adc_sample(adc1);
+ assert(rc == OS_OK);
+#endif
++g_task1_loops;
#if MYNEWT_VAL(SPI_MASTER)
@@ -399,8 +505,13 @@ task1_handler(void *arg)
/* Release semaphore to task 2 */
os_sem_release(&g_test_sem);
}
+#if MYNEWT_VAL(ADC_3)
+ os_dev_close((struct os_dev *) adc3);
+#endif
- os_dev_close((struct os_dev *) adc);
+#if MYNEWT_VAL(ADC_1)
+ os_dev_close((struct os_dev *) adc1);
+#endif
}
void
@@ -478,7 +589,6 @@ main(int argc, char **argv)
/* Initialize the sblinky log. */
log_console_handler_init(&log_console_handler);
log_register("sblinky", &my_log, &log_console_handler);
-
#if 0
saadc_test();
#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h
----------------------------------------------------------------------
diff --git a/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h b/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h
index e5a494f..ad5bc86 100644
--- a/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h
+++ b/drivers/adc/adc_stm32f4/include/adc_stm32f4/adc_stm32f4.h
@@ -22,16 +22,36 @@
#include <adc/adc.h>
+/* Mynewt HAL Port pin mapping */
+#define ADC123_CH0_PIN 0
+#define ADC123_CH1_PIN 1
+#define ADC123_CH2_PIN 2
+#define ADC123_CH3_PIN 3
+#define ADC12_CH4_PIN 4
+#define ADC12_CH5_PIN 5
+#define ADC12_CH6_PIN 6
+#define ADC12_CH7_PIN 7
+#define ADC12_CH8_PIN 16
+#define ADC12_CH9_PIN 17
+#define ADC3_CH4_PIN 86
+#define ADC3_CH5_PIN 87
+#define ADC3_CH6_PIN 88
+#define ADC3_CH7_PIN 89
+#define ADC3_CH8_PIN 90
+#define ADC3_CH9_PIN 83
+#define ADC123_CH10_PIN 32
+#define ADC123_CH11_PIN 33
+#define ADC123_CH12_PIN 34
+#define ADC123_CH13_PIN 35
+#define ADC12_CH14_PIN 36
+#define ADC12_CH15_PIN 37
+#define ADC3_CH14_PIN 84
+#define ADC3_CH15_PIN 85
+
struct stm32f4_adc_dev_cfg {
uint8_t sac_chan_count;
- uint8_t *sac_chans;
- ADC_InitTypeDef sac_init;
-};
-
-struct stm32f4_adc_dev {
- struct adc_dev sad_dev;
- ADC_TypeDef *sad_adc;
- ADC_InitTypeDef *sad_init;
+ void *sac_chans;
+ ADC_HandleTypeDef *sac_adc_handle;
};
int stm32f4_adc_dev_init(struct os_dev *, void *);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/drivers/adc/adc_stm32f4/pkg.yml
----------------------------------------------------------------------
diff --git a/drivers/adc/adc_stm32f4/pkg.yml b/drivers/adc/adc_stm32f4/pkg.yml
index 205dfa8..bb24fd7 100644
--- a/drivers/adc/adc_stm32f4/pkg.yml
+++ b/drivers/adc/adc_stm32f4/pkg.yml
@@ -22,9 +22,9 @@ pkg.description: ADC driver for the STM32F4 series of processors.
pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
-pkg.features:
+pkg.features:
- ADC_STM32F4
-pkg.apis:
+pkg.apis:
- ADC_HW_IMPL
pkg.deps.TEST:
- hw/hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/drivers/adc/adc_stm32f4/src/adc_stm32f4.c
----------------------------------------------------------------------
diff --git a/drivers/adc/adc_stm32f4/src/adc_stm32f4.c b/drivers/adc/adc_stm32f4/src/adc_stm32f4.c
index 95a068e..029c267 100644
--- a/drivers/adc/adc_stm32f4/src/adc_stm32f4.c
+++ b/drivers/adc/adc_stm32f4/src/adc_stm32f4.c
@@ -23,13 +23,371 @@
#include <assert.h>
#include <os/os.h>
#include <bsp/cmsis_nvic.h>
+#include "stm32f4xx_hal_dma.h"
+#include "stm32f4xx_hal_adc.h"
+#include "stm32f4xx_hal_rcc.h"
+#include "stm32f4xx_hal_cortex.h"
+#include "stm32f4xx_hal.h"
+#include "adc_stm32f4/adc_stm32f4.h"
+#include "stm32f4xx_hal_dma.h"
+#include "mcu/stm32f4xx_mynewt_hal.h"
+
+#define STM32F4_IS_DMA_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= DMA_CHANNEL_2)
+
+static DMA_HandleTypeDef *dma_handle[5];
+static struct adc_dev *adc_dma[5];
struct stm32f4_adc_stats {
uint16_t adc_events;
- uint16_t adc_events_failed;
+ uint16_t adc_DMA_xfer_failed;
+ uint16_t adc_DMA_xfer_aborted;
+ uint16_t adc_DMA_xfer_complete;
+ uint16_t adc_error;
};
+
static struct stm32f4_adc_stats stm32f4_adc_stats;
+static void
+stm32f4_adc_clk_enable(ADC_HandleTypeDef *hadc) {
+ uintptr_t adc_addr = (uintptr_t)hadc->Instance;
+
+ switch (adc_addr) {
+ case (uintptr_t)ADC1:
+ __HAL_RCC_ADC1_CLK_ENABLE();
+ break;
+ case (uintptr_t)ADC2:
+ __HAL_RCC_ADC2_CLK_ENABLE();
+ break;
+ case (uintptr_t)ADC3:
+ __HAL_RCC_ADC3_CLK_ENABLE();
+ break;
+ default:
+ assert(0);
+ }
+}
+
+static void
+stm32f4_adc_clk_disable(ADC_HandleTypeDef *hadc) {
+ uintptr_t adc_addr = (uintptr_t)hadc->Instance;
+
+ switch (adc_addr) {
+ case (uintptr_t)ADC1:
+ __HAL_RCC_ADC1_CLK_DISABLE();
+ break;
+ case (uintptr_t)ADC2:
+ __HAL_RCC_ADC2_CLK_DISABLE();
+ break;
+ case (uintptr_t)ADC3:
+ __HAL_RCC_ADC3_CLK_DISABLE();
+ break;
+ default:
+ assert(0);
+ }
+}
+
+static GPIO_InitTypeDef
+stm32f4_resolve_adc_gpio(ADC_HandleTypeDef *adc, uint8_t cnum)
+{
+ uintptr_t adc_addr = (uintptr_t)adc->Instance;
+ uint32_t pin;
+ GPIO_InitTypeDef gpio_td;
+
+ switch (adc_addr) {
+ case (uintptr_t)ADC1:
+ case (uintptr_t)ADC2:
+ switch(cnum) {
+ case ADC_CHANNEL_4:
+ pin = ADC12_CH4_PIN;
+ goto done;
+ case ADC_CHANNEL_5:
+ pin = ADC12_CH5_PIN;
+ goto done;
+ case ADC_CHANNEL_6:
+ pin = ADC12_CH6_PIN;
+ goto done;
+ case ADC_CHANNEL_7:
+ pin = ADC12_CH7_PIN;
+ goto done;
+ case ADC_CHANNEL_8:
+ pin = ADC12_CH8_PIN;
+ goto done;
+ case ADC_CHANNEL_9:
+ pin = ADC12_CH9_PIN;
+ goto done;
+ case ADC_CHANNEL_14:
+ pin = ADC12_CH14_PIN;
+ goto done;
+ case ADC_CHANNEL_15:
+ pin = ADC12_CH15_PIN;
+ goto done;
+ }
+ case (uintptr_t)ADC3:
+ switch(cnum) {
+ case ADC_CHANNEL_0:
+ pin = ADC123_CH0_PIN;
+ goto done;
+ case ADC_CHANNEL_1:
+ pin = ADC123_CH1_PIN;
+ goto done;
+ case ADC_CHANNEL_2:
+ pin = ADC123_CH2_PIN;
+ goto done;
+ case ADC_CHANNEL_3:
+ pin = ADC123_CH3_PIN;
+ goto done;
+ case ADC_CHANNEL_4:
+ pin = ADC3_CH4_PIN;
+ goto done;
+ case ADC_CHANNEL_5:
+ pin = ADC3_CH5_PIN;
+ goto done;
+ case ADC_CHANNEL_6:
+ pin = ADC3_CH6_PIN;
+ goto done;
+ case ADC_CHANNEL_7:
+ pin = ADC3_CH7_PIN;
+ goto done;
+ case ADC_CHANNEL_8:
+ pin = ADC3_CH8_PIN;
+ goto done;
+ case ADC_CHANNEL_9:
+ pin = ADC3_CH9_PIN;
+ goto done;
+ case ADC_CHANNEL_10:
+ pin = ADC123_CH10_PIN;
+ goto done;
+ case ADC_CHANNEL_11:
+ pin = ADC123_CH11_PIN;
+ goto done;
+ case ADC_CHANNEL_12:
+ pin = ADC123_CH12_PIN;
+ goto done;
+ case ADC_CHANNEL_13:
+ pin = ADC123_CH13_PIN;
+ goto done;
+ case ADC_CHANNEL_14:
+ pin = ADC3_CH14_PIN;
+ goto done;
+ case ADC_CHANNEL_15:
+ pin = ADC3_CH15_PIN;
+ goto done;
+ }
+ default:
+ assert(0);
+ }
+done:
+ gpio_td = (GPIO_InitTypeDef){
+ .Pin = pin,
+ .Mode = GPIO_MODE_ANALOG,
+ .Pull = GPIO_NOPULL,
+ .Alternate = pin
+ };
+ return gpio_td;
+}
+
+static IRQn_Type
+stm32f4_resolve_adc_dma_irq(DMA_HandleTypeDef *hdma)
+{
+ uintptr_t stream_addr = (uintptr_t)hdma->Instance;
+
+ assert(STM32F4_IS_DMA_ADC_CHANNEL(hdma->Init.Channel));
+
+ switch(stream_addr) {
+ /* DMA2 */
+ case (uintptr_t)DMA2_Stream0:
+ return DMA2_Stream0_IRQn;
+ case (uintptr_t)DMA2_Stream1:
+ return DMA2_Stream1_IRQn;
+ case (uintptr_t)DMA2_Stream2:
+ return DMA2_Stream2_IRQn;
+ case (uintptr_t)DMA2_Stream3:
+ return DMA2_Stream3_IRQn;
+ case (uintptr_t)DMA2_Stream4:
+ return DMA2_Stream4_IRQn;
+ default:
+ assert(0);
+ }
+}
+
+static void
+dma2_stream0_irq_handler(void)
+{
+ HAL_DMA_IRQHandler(dma_handle[0]);
+}
+
+static void
+dma2_stream1_irq_handler(void)
+{
+ HAL_DMA_IRQHandler(dma_handle[1]);
+}
+
+static void
+dma2_stream2_irq_handler(void)
+{
+ HAL_DMA_IRQHandler(dma_handle[2]);
+}
+
+static void
+dma2_stream3_irq_handler(void)
+{
+ HAL_DMA_IRQHandler(dma_handle[3]);
+}
+
+static void
+dma2_stream4_irq_handler(void)
+{
+ HAL_DMA_IRQHandler(dma_handle[4]);
+}
+
+uint32_t
+stm32f4_resolve_adc_dma_irq_handler(DMA_HandleTypeDef *hdma)
+{
+ switch((uintptr_t)hdma->Instance) {
+ /* DMA2 */
+ case (uintptr_t)DMA2_Stream0:
+ return (uint32_t)&dma2_stream0_irq_handler;
+ case (uintptr_t)DMA2_Stream1:
+ return (uint32_t)&dma2_stream1_irq_handler;
+ case (uintptr_t)DMA2_Stream2:
+ return (uint32_t)&dma2_stream2_irq_handler;
+ case (uintptr_t)DMA2_Stream3:
+ return (uint32_t)&dma2_stream3_irq_handler;
+ case (uintptr_t)DMA2_Stream4:
+ return (uint32_t)&dma2_stream4_irq_handler;
+ default:
+ assert(0);
+ }
+}
+
+static int
+stm32f4_resolve_dma_handle_idx(DMA_HandleTypeDef *hdma)
+{
+ uintptr_t stream_addr = (uintptr_t)hdma->Instance;
+ return ((stream_addr & 0xFF) - ((uintptr_t)DMA2_Stream0_BASE & 0xFF))/0x18;
+}
+
+static void
+stm32f4_xfer_error_cb(DMA_HandleTypeDef *hdma)
+{
+ /* DMA transfer error callback */
+ stm32f4_adc_stats.adc_DMA_xfer_failed++;
+}
+
+static void
+stm32f4_xfer_abort_cb(DMA_HandleTypeDef *hdma)
+{
+ /* DMA transfer Abort callback */
+ stm32f4_adc_stats.adc_DMA_xfer_aborted++;
+}
+
+void
+HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+ stm32f4_adc_stats.adc_error++;
+}
+
+void
+HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+ int rc;
+ struct adc_dev *adc;
+ DMA_HandleTypeDef *hdma;
+
+ assert(hadc);
+ hdma = hadc->DMA_Handle;
+
+ ++stm32f4_adc_stats.adc_DMA_xfer_complete;
+
+ adc = adc_dma[stm32f4_resolve_dma_handle_idx(hdma)];
+
+ rc = adc->ad_event_handler_func(adc, NULL, ADC_EVENT_RESULT, adc->primarybuf,
+ adc->buflen);
+ if (rc) {
+ ++stm32f4_adc_stats.adc_error;
+ }
+}
+
+
+//void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+static void
+stm32f4_adc_dma_init(ADC_HandleTypeDef* hadc)
+{
+
+ DMA_HandleTypeDef *hdma;
+
+ assert(hadc);
+ hdma = hadc->DMA_Handle;
+
+ stm32f4_adc_clk_enable(hadc);
+ __HAL_RCC_DMA2_CLK_ENABLE();
+
+ HAL_DMA_Init(hdma);
+ dma_handle[stm32f4_resolve_dma_handle_idx(hdma)] = hdma;
+
+ if (HAL_DMA_RegisterCallback(hdma, HAL_DMA_XFER_ERROR_CB_ID,
+ stm32f4_xfer_error_cb) != HAL_OK) {
+ assert(0);
+ }
+
+ if (HAL_DMA_RegisterCallback(hdma, HAL_DMA_XFER_ABORT_CB_ID,
+ stm32f4_xfer_abort_cb) != HAL_OK) {
+ assert(0);
+ }
+
+ NVIC_SetPriority(stm32f4_resolve_adc_dma_irq(hdma),
+ NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
+ NVIC_SetVector(stm32f4_resolve_adc_dma_irq(hdma),
+ stm32f4_resolve_adc_dma_irq_handler(hdma));
+ NVIC_EnableIRQ(stm32f4_resolve_adc_dma_irq(hdma));
+
+}
+
+static void
+stm32f4_adc_init(void *arg)
+{
+ struct stm32f4_adc_dev_cfg *adc_config = (struct stm32f4_adc_dev_cfg *)arg;
+ ADC_HandleTypeDef *hadc;
+
+ assert(adc_config);
+
+ hadc = adc_config->sac_adc_handle;
+
+ stm32f4_adc_dma_init(hadc);
+
+ if (HAL_ADC_Init(hadc) != HAL_OK) {
+ assert(0);
+ }
+}
+
+static void
+stm32f4_adc_uninit(struct adc_dev *dev)
+{
+ GPIO_InitTypeDef gpio_td;
+ DMA_HandleTypeDef *hdma;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
+ uint8_t cnum;
+
+ assert(dev);
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
+ hdma = hadc->DMA_Handle;
+ cnum = dev->ad_chans->c_cnum;
+
+ gpio_td = stm32f4_resolve_adc_gpio(hadc, cnum);
+
+ if(hal_gpio_deinit_stm(gpio_td.Pin, &gpio_td)) {
+ assert(0);
+ }
+
+ __HAL_RCC_DMA2_CLK_DISABLE();
+ if (HAL_DMA_DeInit(hdma) != HAL_OK) {
+ assert(0);
+ }
+ stm32f4_adc_clk_disable(hadc);
+
+ NVIC_DisableIRQ(stm32f4_resolve_adc_dma_irq(hdma));
+}
/**
* Open the STM32F4 ADC device
@@ -47,9 +405,14 @@ static struct stm32f4_adc_stats stm32f4_adc_stats;
static int
stm32f4_adc_open(struct os_dev *odev, uint32_t wait, void *arg)
{
+ DMA_HandleTypeDef *hdma;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
struct adc_dev *dev;
int rc;
+ assert(odev);
+ rc = OS_OK;
dev = (struct adc_dev *) odev;
if (os_started()) {
@@ -59,13 +422,22 @@ stm32f4_adc_open(struct os_dev *odev, uint32_t wait, void *arg)
}
}
- if (odev->od_status & OS_DEV_STATUS_OPEN) {
+ if (odev->od_flags & OS_DEV_F_STATUS_OPEN) {
os_mutex_release(&dev->ad_lock);
rc = OS_EBUSY;
goto err;
}
- return (0);
+
+ stm32f4_adc_init(dev->adc_dev_cfg);
+
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
+ hdma = hadc->DMA_Handle;
+
+ adc_dma[stm32f4_resolve_dma_handle_idx(hdma)] = dev;
+
+ return (OS_OK);
err:
return (rc);
}
@@ -85,20 +457,22 @@ stm32f4_adc_close(struct os_dev *odev)
dev = (struct adc_dev *) odev;
+ stm32f4_adc_uninit(dev);
+
if (os_started()) {
os_mutex_release(&dev->ad_lock);
}
- return (0);
+ return (OS_OK);
}
/**
- * Configure an ADC channel on the Nordic ADC.
+ * Configure an ADC channel on the STM32F4 ADC.
*
* @param dev The ADC device to configure
* @param cnum The channel on the ADC device to configure
* @param cfgdata An opaque pointer to channel config, expected to be
- * a nrf_saadc_channel_config_t
+ * a ADC_ChannelConfTypeDef
*
* @return 0 on success, non-zero on failure.
*/
@@ -106,21 +480,38 @@ static int
stm32f4_adc_configure_channel(struct adc_dev *dev, uint8_t cnum,
void *cfgdata)
{
- uint16_t refmv;
- uint8_t res;
int rc;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
+ GPIO_InitTypeDef gpio_td;
+ struct adc_chan_config *chan_cfg;
- /* XXX: Dummy values prior to implementation. */
- res = 16;
- refmv = 2800;
+ assert(dev != NULL && IS_ADC_CHANNEL(cnum));
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
+ chan_cfg = cfg->sac_chans;
- /* Store these values in channel definitions, for conversions to
- * milivolts.
- */
- dev->ad_chans[cnum].c_res = res;
- dev->ad_chans[cnum].c_refmv = refmv;
+ // Enable DMA, ADC and related GPIO ports clock
+ gpio_td = stm32f4_resolve_adc_gpio(hadc, cnum);
+ hal_gpio_init_stm(gpio_td.Pin, &gpio_td);
+
+
+ cfgdata = (ADC_ChannelConfTypeDef *)cfgdata;
+
+ if((rc = HAL_ADC_ConfigChannel(hadc, cfgdata)) != HAL_OK) {
+ goto err;
+ }
+
+ dev->ad_chans[cnum].c_res = chan_cfg->c_res;
+ dev->ad_chans[cnum].c_refmv = chan_cfg->c_refmv;
dev->ad_chans[cnum].c_configured = 1;
+#if 0
+ if (HAL_ADC_Start_IT(hadc) != HAL_OK) {
+ assert(0);
+ }
+#endif
+
return (0);
err:
return (rc);
@@ -129,32 +520,48 @@ err:
/**
* Set buffer to read data into. Implementation of setbuffer handler.
* Sets both the primary and secondary buffers for DMA.
+ *
+ * For our current implementation we are using DMA in circular mode
+ *
*/
static int
stm32f4_adc_set_buffer(struct adc_dev *dev, void *buf1, void *buf2,
- int buf_len)
+ int buflen)
{
int rc;
- rc = OS_EINVAL;
- goto err;
+ rc = OS_OK;
+ buflen /= sizeof(uint16_t);
- return (0);
-err:
- return (rc);
+ assert(dev != NULL && buf1 != NULL);
+
+ dev->primarybuf = buf1;
+ dev->secondarybuf = buf2;
+ dev->buflen = buflen;
+
+ return rc;
}
static int
stm32f4_adc_release_buffer(struct adc_dev *dev, void *buf, int buf_len)
{
- int rc;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
- rc = OS_EINVAL;
- goto err;
+ assert(dev);
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
+
+ HAL_ADC_Stop_DMA(hadc);
+
+ if (dev->primarybuf == buf) {
+ if (dev->secondarybuf) {
+ dev->primarybuf = dev->secondarybuf;
+ dev->secondarybuf = buf;
+ }
+ }
return (0);
-err:
- return (rc);
}
/**
@@ -163,7 +570,24 @@ err:
static int
stm32f4_adc_sample(struct adc_dev *dev)
{
- return (0);
+ int rc;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
+
+ assert(dev != NULL && dev->primarybuf != NULL);
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
+
+ rc = OS_EINVAL;
+
+ if (HAL_ADC_Start_DMA(hadc, dev->primarybuf, dev->buflen) != HAL_OK) {
+ goto err;
+ }
+
+ rc = OS_OK;
+
+err:
+ return rc;
}
/**
@@ -172,57 +596,67 @@ stm32f4_adc_sample(struct adc_dev *dev)
static int
stm32f4_adc_read_channel(struct adc_dev *dev, uint8_t cnum, int *result)
{
- int rc;
+ ADC_HandleTypeDef *hadc;
+ struct stm32f4_adc_dev_cfg *cfg;
- rc = OS_EINVAL;
- goto err;
+ assert(dev != NULL && result != NULL);
+ cfg = dev->adc_dev_cfg;
+ hadc = cfg->sac_adc_handle;
- return (0);
-err:
- return (rc);
+ *result = HAL_ADC_GetValue(hadc);
+
+ return (OS_OK);
}
static int
stm32f4_adc_read_buffer(struct adc_dev *dev, void *buf, int buf_len, int off,
- int *result)
+ int *result)
{
- return (0);
+
+ assert(off < buf_len);
+
+ *result = *((uint32_t *) buf + off);
+
+ return (OS_OK);
}
static int
stm32f4_adc_size_buffer(struct adc_dev *dev, int chans, int samples)
{
- return (0 * chans * samples);
+ return (sizeof(uint32_t) * chans * samples);
}
+#if 0
+void ADC_IRQHandler(void)
+{
+ HAL_ADC_IRQHandler(adc_handle);
+}
+#endif
+
/**
* Callback to initialize an adc_dev structure from the os device
- * initialization callback. This sets up a nrf52_adc_device(), so
+ * initialization callback. This sets up a stm32f4_adc_device(), so
* that subsequent lookups to this device allow us to manipulate it.
*/
int
stm32f4_adc_dev_init(struct os_dev *odev, void *arg)
{
- struct stm32f4_adc_dev *sad;
struct stm32f4_adc_dev_cfg *sac;
struct adc_dev *dev;
struct adc_driver_funcs *af;
- sad = (struct stm32f4_adc_dev *) odev;
sac = (struct stm32f4_adc_dev_cfg *) arg;
- assert(sad != NULL);
assert(sac != NULL);
- dev = (struct adc_dev *) &sad->sad_dev;
+ dev = (struct adc_dev *)odev;
os_mutex_init(&dev->ad_lock);
/* Have a pointer to the init typedef from the configured
* value. This allows non-driver specific items to be configured.
*/
- sad->sad_init = &sac->sac_init;
dev->ad_chans = (void *) sac->sac_chans;
dev->ad_chan_count = sac->sac_chan_count;
@@ -230,6 +664,7 @@ stm32f4_adc_dev_init(struct os_dev *odev, void *arg)
OS_DEV_SETHANDLERS(odev, stm32f4_adc_open, stm32f4_adc_close);
af = &dev->ad_funcs;
+ dev->adc_dev_cfg = arg;
af->af_configure_channel = stm32f4_adc_configure_channel;
af->af_sample = stm32f4_adc_sample;
@@ -242,4 +677,3 @@ stm32f4_adc_dev_init(struct os_dev *odev, void *arg)
return (0);
}
-
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/drivers/adc/include/adc/adc.h
----------------------------------------------------------------------
diff --git a/drivers/adc/include/adc/adc.h b/drivers/adc/include/adc/adc.h
index 01727c0..f0d4ad5 100644
--- a/drivers/adc/include/adc/adc.h
+++ b/drivers/adc/include/adc/adc.h
@@ -146,6 +146,7 @@ struct adc_chan_config {
uint16_t c_refmv;
uint8_t c_res;
uint8_t c_configured;
+ uint8_t c_cnum;
};
struct adc_dev {
@@ -153,9 +154,13 @@ struct adc_dev {
struct os_mutex ad_lock;
struct adc_driver_funcs ad_funcs;
struct adc_chan_config *ad_chans;
+ void *adc_dev_cfg;
int ad_chan_count;
adc_event_handler_func_t ad_event_handler_func;
void *ad_event_handler_arg;
+ void *primarybuf;
+ void *secondarybuf;
+ int buflen;
};
int adc_chan_config(struct adc_dev *, uint8_t, void *);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/drivers/adc/pkg.yml
----------------------------------------------------------------------
diff --git a/drivers/adc/pkg.yml b/drivers/adc/pkg.yml
index 94469bc..bf0205a 100644
--- a/drivers/adc/pkg.yml
+++ b/drivers/adc/pkg.yml
@@ -22,5 +22,5 @@ pkg.description: ADC driver interfaces
pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
-pkg.req_apis:
+pkg.req_apis:
- ADC_HW_IMPL
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld b/hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld
index 4c1541d..b07d869 100755
--- a/hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld
+++ b/hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld
@@ -192,7 +192,7 @@ SECTIONS
__HeapLimit = ORIGIN(RAM) + LENGTH(RAM);
_ram_start = ORIGIN(RAM);
- _ccram_start = ORIGIN(CCRAM);
+ _ccram_start = ORIGIN(CCM);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
index a06aaf0..41c0674 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
+++ b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
@@ -36,13 +36,18 @@ pkg.debugscript: "olimex_stm32-e407_devboard_debug.sh"
pkg.cflags:
# STM SDK files require these defines.
- '-DSTM32F407xx'
-
+ - '-DHAL_ADC_MODULE_ENABLED'
+ - '-DHAL_DMA_MODULE_ENABLED'
pkg.deps:
- hw/mcu/stm/stm32f4xx
- libs/baselibc
-pkg.deps.ADC_0:
- - drivers/adc/adc_nrf52
+pkg.deps.ADC_1:
+ - drivers/adc/adc_stm32f4
+pkg.deps.ADC_2:
+ - drivers/adc/adc_stm32f4
+pkg.deps.ADC_3:
+ - drivers/adc/adc_stm32f4
pkg.deps.UART_0:
- drivers/uart/uart_hal
@@ -55,19 +60,15 @@ pkg.syscfg_defs:
description: 'TBD'
value: 1000000
- ADC_0:
- description: 'TBD'
- value: 0
- ADC_0_RESOLUTION:
- description: 'TBD'
- value: 'SAADC_CONFIG_RESOLUTION'
- ADC_0_OVERSAMPLE:
- description: 'TBD'
- value: 'SAADC_CONFIG_OVERSAMPLE'
- ADC_0_INTERRUPT_PRIORITY:
- description: 'TBD'
- value: 'SAADC_CONFIG_IRQ_PRIORITY'
-
+ ADC_1:
+ description: "ADC_1"
+ value: 1
+ ADC_2:
+ description: "ADC_2"
+ value: 1
+ ADC_3:
+ description: "ADC_3"
+ value: 1
UART_0:
description: 'TBD'
value: 1
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c b/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c
index ec71236..39b0bac 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c
+++ b/hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c
@@ -30,6 +30,10 @@
#include <uart_hal/uart_hal.h>
#include "bsp/bsp.h"
+#include "syscfg/syscfg.h"
+#include "stm32f4xx_hal_dma.h"
+#include "stm32f4xx_hal_adc.h"
+#include <adc_stm32f4/adc_stm32f4.h>
static struct flash_area bsp_flash_areas[] = {
[FLASH_AREA_BOOTLOADER] = {
@@ -62,9 +66,155 @@ static struct flash_area bsp_flash_areas[] = {
static struct uart_dev hal_uart0;
/* XXX should not be here */
+
+#if MYNEWT_VAL(ADC_1)
+struct adc_dev my_dev_adc1;
+#endif
+
struct stm32f4_uart_cfg;
+#if MYNEWT_VAL(ADC_3)
+struct adc_dev my_dev_adc3;
+#endif
+
extern struct stm32f4_uart_cfg *bsp_uart_config(int port);
+/*****************ADC3 Config ***************/
+
+#if MYNEWT_VAL(ADC_3)
+
+ADC_HandleTypeDef adc_handle;
+
+#define STM32F4_DEFAULT_DMA_HANDLE21 {\
+ .Instance = DMA2_Stream1,\
+ .Init.Channel = DMA_CHANNEL_2,\
+ .Init.Direction = DMA_PERIPH_TO_MEMORY,\
+ .Init.PeriphInc = DMA_PINC_DISABLE,\
+ .Init.MemInc = DMA_MINC_ENABLE,\
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\
+ .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\
+ .Init.Mode = DMA_CIRCULAR,\
+ .Init.Priority = DMA_PRIORITY_HIGH,\
+ .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\
+ .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\
+ .Init.MemBurst = DMA_MBURST_SINGLE,\
+ .Init.PeriphBurst = DMA_PBURST_SINGLE,\
+ .Parent = &adc_handle,\
+}
+#endif
+
+#if MYNEWT_VAL(ADC_1)
+/*
+ * adc_handle is defined earlier because the DMA handle's
+ * parent needs to be pointing to the adc_handle
+ */
+ADC_HandleTypeDef adc_handle120;
+
+DMA_HandleTypeDef adc_dma_handle21 = STM32F4_DEFAULT_DMA_HANDLE21;
+
+#define STM32F4_DEFAULT_DMA_HANDLE20 {\
+ .Instance = DMA2_Stream0,\
+ .Init.Channel = DMA_CHANNEL_0,\
+ .Init.Direction = DMA_PERIPH_TO_MEMORY,\
+ .Init.PeriphInc = DMA_PINC_DISABLE,\
+ .Init.MemInc = DMA_MINC_ENABLE,\
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\
+ .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\
+ .Init.Mode = DMA_CIRCULAR,\
+ .Init.Priority = DMA_PRIORITY_HIGH,\
+ .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\
+ .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\
+ .Init.MemBurst = DMA_MBURST_SINGLE,\
+ .Init.PeriphBurst = DMA_PBURST_SINGLE,\
+ .Parent = &adc_handle120,\
+}
+
+DMA_HandleTypeDef adc_dma_handle20 = STM32F4_DEFAULT_DMA_HANDLE20;
+#endif
+
+
+#define STM32F4_ADC_DEFAULT_INIT_TD {\
+ .ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2,\
+ .Resolution = ADC_RESOLUTION12b,\
+ .DataAlign = ADC_DATAALIGN_RIGHT,\
+ .ScanConvMode = DISABLE,\
+ .EOCSelection = DISABLE,\
+ .ContinuousConvMode = ENABLE,\
+ .NbrOfConversion = 2,\
+ .DiscontinuousConvMode = DISABLE,\
+ .NbrOfDiscConversion = 0,\
+ .ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1,\
+ .ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE,\
+ .DMAContinuousRequests = ENABLE\
+}
+
+
+#if MYNEWT_VAL(ADC_3)
+
+#define STM32F4_DEFAULT_ADC_HANDLE {\
+ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\
+ .Instance = ADC3,\
+ .NbrOfCurrentConversionRank = 0,\
+ .DMA_Handle = &adc_dma_handle21,\
+ .Lock = HAL_UNLOCKED,\
+ .State = 0,\
+ .ErrorCode = 0\
+}
+
+ADC_HandleTypeDef adc_handle = STM32F4_DEFAULT_ADC_HANDLE;
+
+#define STM32F4_ADC_DEFAULT_SAC_CHAN {\
+ .c_refmv = 3300,\
+ .c_res = 12,\
+ .c_configured = 1,\
+ .c_cnum = ADC_CHANNEL_4\
+}
+
+struct adc_chan_config def_sac_chan = STM32F4_ADC_DEFAULT_SAC_CHAN;
+
+#define STM32F4_ADC_DEFAULT_CONFIG {\
+ .sac_chan_count = 16,\
+ .sac_chans = &def_sac_chan,\
+ .sac_adc_handle = &adc_handle,\
+}
+
+struct stm32f4_adc_dev_cfg adc_config = STM32F4_ADC_DEFAULT_CONFIG;
+#endif
+
+
+#if MYNEWT_VAL(ADC_1)
+
+/*****************ADC1 Config ***************/
+#define STM32F4_DEFAULT_ADC_HANDLE120 {\
+ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\
+ .Instance = ADC1,\
+ .NbrOfCurrentConversionRank = 0,\
+ .DMA_Handle = &adc_dma_handle20,\
+ .Lock = HAL_UNLOCKED,\
+ .State = 0,\
+ .ErrorCode = 0\
+}
+
+ADC_HandleTypeDef adc_handle120 = STM32F4_DEFAULT_ADC_HANDLE120;
+
+#define STM32F4_ADC_DEFAULT_SAC_CHAN10 {\
+ .c_refmv = 3300,\
+ .c_res = 12,\
+ .c_configured = 1,\
+ .c_cnum = ADC_CHANNEL_10\
+}
+
+struct adc_chan_config def_sac_chan10 = STM32F4_ADC_DEFAULT_SAC_CHAN10;
+
+#define STM32F4_ADC_DEFAULT_CONFIG_1_2_0_10 {\
+ .sac_chan_count = 16,\
+ .sac_chans = &def_sac_chan10,\
+ .sac_adc_handle = &adc_handle120,\
+}
+
+struct stm32f4_adc_dev_cfg adc_config12010 = STM32F4_ADC_DEFAULT_CONFIG_1_2_0_10;
+/*********************************************/
+#endif
+
void _close(int fd);
/*
@@ -97,5 +247,18 @@ bsp_init(void)
rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART,
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)bsp_uart_config(0));
assert(rc == 0);
+#if MYNEWT_VAL(ADC_3)
+ rc = os_dev_create((struct os_dev *) &my_dev_adc3, "adc3",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ stm32f4_adc_dev_init, &adc_config);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(ADC_1)
+ rc = os_dev_create((struct os_dev *) &my_dev_adc1, "adc1",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ stm32f4_adc_dev_init, &adc_config12010);
+ assert(rc == 0);
+#endif
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/mcu/stm/stm32f4xx/include/mcu/stm32f4xx_mynewt_hal.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/include/mcu/stm32f4xx_mynewt_hal.h b/hw/mcu/stm/stm32f4xx/include/mcu/stm32f4xx_mynewt_hal.h
index 33e82c6..c18decd 100644
--- a/hw/mcu/stm/stm32f4xx/include/mcu/stm32f4xx_mynewt_hal.h
+++ b/hw/mcu/stm/stm32f4xx/include/mcu/stm32f4xx_mynewt_hal.h
@@ -42,6 +42,7 @@
int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg);
+int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg);
struct stm32f4_hal_i2c_cfg {
int sda_pin;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/mcu/stm/stm32f4xx/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/pkg.yml b/hw/mcu/stm/stm32f4xx/pkg.yml
index 952c6ab..83c0742 100644
--- a/hw/mcu/stm/stm32f4xx/pkg.yml
+++ b/hw/mcu/stm/stm32f4xx/pkg.yml
@@ -35,5 +35,5 @@ pkg.ign_dirs:
pkg.deps:
- hw/hal
- - libs/cmsis-core
+ - libs/cmsis-core
- compiler/arm-none-eabi-m4
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/src/hal_gpio.c b/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
index 8778229..9fcc3bd 100644
--- a/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
@@ -60,7 +60,7 @@
* - Multiply by 16.
* - Add port pin number.
*
- * Ex: PE11 = (4 * 16) + 11 = 75.
+ * Ex: PD11 = (3 * 16) + 11 = 59.
* PA0 = (0 * 16) + 0 = 0
*/
#define GPIO_INDEX(pin) ((pin) & 0x0F)
@@ -395,6 +395,37 @@ hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg)
}
/**
+ * hal gpio deinit
+ *
+ * Called to deinitialize a gpio.
+ *
+ * @param pin
+ * @param cfg
+ *
+ * @return int
+ */
+int
+hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg)
+{
+ int port;
+ uint32_t mcu_pin_mask;
+
+ /* Is this a valid pin? */
+ port = GPIO_PORT(pin);
+ if (port >= HAL_GPIO_NUM_PORTS) {
+ return -1;
+ }
+
+ mcu_pin_mask = GPIO_MASK(pin);
+ cfg->Pin = mcu_pin_mask;
+
+ /* Initialize pin as an input, setting proper mode */
+ HAL_GPIO_DeInit(portmap[port], cfg->Pin);
+
+ return 0;
+}
+
+/**
* gpio init in
*
* Initializes the specified pin as an input
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/82767ae9/hw/mcu/stm/stm32f4xx/src/hal_spi.c
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/src/hal_spi.c b/hw/mcu/stm/stm32f4xx/src/hal_spi.c
index 314a24a..197cf2c 100644
--- a/hw/mcu/stm/stm32f4xx/src/hal_spi.c
+++ b/hw/mcu/stm/stm32f4xx/src/hal_spi.c
@@ -118,7 +118,7 @@ struct stm32f4_hal_spi *stm32f4_hal_spis[STM32F4_HAL_SPI_MAX] = {
}
int
-hal_spi_init(uint8_t spi_num, void *usercfg)
+hal_spi_init(int spi_num, void *usercfg, uint8_t spi_type)
{
struct stm32f4_hal_spi *spi;
struct stm32f4_hal_spi_cfg *cfg;
@@ -238,7 +238,7 @@ stm32f4_spi_resolve_prescaler(uint8_t spi_num, uint32_t baudrate, uint32_t *pres
}
int
-hal_spi_config(uint8_t spi_num, struct hal_spi_settings *settings)
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
{
struct stm32f4_hal_spi *spi;
SPI_InitTypeDef *init;