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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/01/31 00:51:29 UTC
[incubator-nuttx] branch pr187 updated (1600980 -> fb1b7b0)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch pr187
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 1600980 fix gran_alloc() miss allocation in mm_granalloc.c.
new b6c8804 Access g_current_regs through the macro CURRENT_REGS.
new a2cf03f pic32mz-head.S: Add showprogress macro
new fb1b7b0 arch/mips/pic32mz/pic32mz-lowconsole.c: Wait for the transfert to complet when using up_lowputc.
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/mips/src/common/up_initialize.c | 2 +-
arch/mips/src/common/up_internal.h | 27 +++++++++--
arch/mips/src/common/up_interruptcontext.c | 2 +-
arch/mips/src/mips32/up_assert.c | 2 +-
arch/mips/src/mips32/up_blocktask.c | 2 +-
arch/mips/src/mips32/up_doirq.c | 12 ++---
arch/mips/src/mips32/up_dumpstate.c | 44 ++++++++---------
arch/mips/src/mips32/up_initialstate.c | 4 +-
arch/mips/src/mips32/up_releasepending.c | 2 +-
arch/mips/src/mips32/up_reprioritizertr.c | 2 +-
arch/mips/src/mips32/up_schedulesigaction.c | 18 +++----
arch/mips/src/mips32/up_swint0.c | 16 +++----
arch/mips/src/mips32/up_unblocktask.c | 2 +-
arch/mips/src/pic32mx/pic32mx-decodeirq.c | 18 +++----
arch/mips/src/pic32mx/pic32mx-exception.c | 2 +-
arch/mips/src/pic32mx/pic32mx-irq.c | 4 +-
arch/mips/src/pic32mz/pic32mz-decodeirq.c | 18 +++----
arch/mips/src/pic32mz/pic32mz-exception.c | 2 +-
arch/mips/src/pic32mz/pic32mz-head.S | 74 ++++++++++++++++++++++++-----
arch/mips/src/pic32mz/pic32mz-irq.c | 10 +++-
arch/mips/src/pic32mz/pic32mz-lowconsole.c | 3 ++
21 files changed, 171 insertions(+), 95 deletions(-)
[incubator-nuttx] 01/03: Access g_current_regs through the macro
CURRENT_REGS.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch pr187
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b6c88040e8e0d0bbad8ab4f8df5262f6a298fcfb
Author: Ouss4 <ab...@gmail.com>
AuthorDate: Sun Jan 19 23:53:07 2020 +0000
Access g_current_regs through the macro CURRENT_REGS.
---
arch/mips/src/common/up_initialize.c | 2 +-
arch/mips/src/common/up_internal.h | 27 ++++++++++++++----
arch/mips/src/common/up_interruptcontext.c | 2 +-
arch/mips/src/mips32/up_assert.c | 2 +-
arch/mips/src/mips32/up_blocktask.c | 2 +-
arch/mips/src/mips32/up_doirq.c | 12 ++++----
arch/mips/src/mips32/up_dumpstate.c | 44 ++++++++++++++---------------
arch/mips/src/mips32/up_initialstate.c | 4 +--
arch/mips/src/mips32/up_releasepending.c | 2 +-
arch/mips/src/mips32/up_reprioritizertr.c | 2 +-
arch/mips/src/mips32/up_schedulesigaction.c | 18 ++++++------
arch/mips/src/mips32/up_swint0.c | 16 +++++------
arch/mips/src/mips32/up_unblocktask.c | 2 +-
arch/mips/src/pic32mx/pic32mx-decodeirq.c | 18 ++++++------
arch/mips/src/pic32mx/pic32mx-exception.c | 2 +-
arch/mips/src/pic32mx/pic32mx-irq.c | 4 +--
arch/mips/src/pic32mz/pic32mz-decodeirq.c | 18 ++++++------
arch/mips/src/pic32mz/pic32mz-exception.c | 2 +-
arch/mips/src/pic32mz/pic32mz-irq.c | 10 +++++--
19 files changed, 106 insertions(+), 83 deletions(-)
diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c
index 682d3f0..b60662e 100644
--- a/arch/mips/src/common/up_initialize.c
+++ b/arch/mips/src/common/up_initialize.c
@@ -86,7 +86,7 @@ void up_initialize(void)
{
/* Initialize global variables */
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
/* Add any extra memory fragments to the memory manager */
diff --git a/arch/mips/src/common/up_internal.h b/arch/mips/src/common/up_internal.h
index e8253c1..1c5ff32 100644
--- a/arch/mips/src/common/up_internal.h
+++ b/arch/mips/src/common/up_internal.h
@@ -93,8 +93,8 @@
* only a referenced is passed to get the state from the TCB.
*/
-#define up_savestate(regs) up_copystate(regs, (uint32_t*)g_current_regs)
-#define up_restorestate(regs) (g_current_regs = regs)
+#define up_savestate(regs) up_copystate(regs, (uint32_t*)CURRENT_REGS)
+#define up_restorestate(regs) (CURRENT_REGS = regs)
/****************************************************************************
* Public Types
@@ -109,11 +109,28 @@ typedef void (*up_vector_t)(void);
****************************************************************************/
#ifndef __ASSEMBLY__
-/* This holds a references to the current interrupt level register storage
- * structure. If is non-NULL only during interrupt processing.
+/* g_current_regs holds a references to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs must be through the macro
+ * CURRENT_REGS for portability.
*/
-extern volatile uint32_t *g_current_regs;
+#ifdef CONFIG_SMP
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+int up_cpu_index(void); /* See include/nuttx/arch.h */
+extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+# define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+#else
+
+extern volatile uint32_t *g_current_regs[1];
+# define CURRENT_REGS (g_current_regs[0])
+
+#endif
+
/* This is the beginning of heap as provided from up_head.S. This is the
* first address in DRAM after the loaded program+bss+idle stack. The end
diff --git a/arch/mips/src/common/up_interruptcontext.c b/arch/mips/src/common/up_interruptcontext.c
index 581f254..ab0807e 100644
--- a/arch/mips/src/common/up_interruptcontext.c
+++ b/arch/mips/src/common/up_interruptcontext.c
@@ -66,5 +66,5 @@
bool up_interrupt_context(void)
{
- return g_current_regs != NULL;
+ return CURRENT_REGS != NULL;
}
diff --git a/arch/mips/src/mips32/up_assert.c b/arch/mips/src/mips32/up_assert.c
index 8656f29..8df546f 100644
--- a/arch/mips/src/mips32/up_assert.c
+++ b/arch/mips/src/mips32/up_assert.c
@@ -86,7 +86,7 @@ static void _up_assert(int errorcode)
/* Are we in an interrupt handler or the idle task? */
- if (g_current_regs || running_task()->flink == NULL)
+ if (CURRENT_REGS || running_task()->flink == NULL)
{
up_irq_save();
for (; ; )
diff --git a/arch/mips/src/mips32/up_blocktask.c b/arch/mips/src/mips32/up_blocktask.c
index e9648f2..06668b6 100644
--- a/arch/mips/src/mips32/up_blocktask.c
+++ b/arch/mips/src/mips32/up_blocktask.c
@@ -117,7 +117,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
/* Are we in an interrupt handler? */
- if (g_current_regs)
+ if (CURRENT_REGS)
{
/* Yes, then we have to do things differently.
* Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_doirq.c b/arch/mips/src/mips32/up_doirq.c
index afa17bf..d178be8 100644
--- a/arch/mips/src/mips32/up_doirq.c
+++ b/arch/mips/src/mips32/up_doirq.c
@@ -84,8 +84,8 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* Nested interrupts are not supported
*/
- DEBUGASSERT(g_current_regs == NULL);
- g_current_regs = regs;
+ DEBUGASSERT(CURRENT_REGS == NULL);
+ CURRENT_REGS = regs;
/* Disable further occurrences of this interrupt (until the interrupt
* srouce have been cleared by the driver).
@@ -105,12 +105,12 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* returning from the interrupt.
*/
- if (regs != g_current_regs)
+ if (regs != CURRENT_REGS)
{
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
- up_restorefpu((uint32_t *)g_current_regs);
+ up_restorefpu((uint32_t *)CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
@@ -131,13 +131,13 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* switch occurred during interrupt processing.
*/
- regs = (uint32_t *)g_current_regs;
+ regs = (uint32_t *)CURRENT_REGS;
/* Set g_current_regs to NULL to indicate that we are no longer in an
* interrupt handler.
*/
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
/* Unmask the last interrupt (global interrupts are still disabled) */
diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c
index 59d86ea..e1dce51 100644
--- a/arch/mips/src/mips32/up_dumpstate.c
+++ b/arch/mips/src/mips32/up_dumpstate.c
@@ -100,38 +100,38 @@ static inline void up_registerdump(void)
{
/* Are user registers available from interrupt processing? */
- if (g_current_regs)
+ if (CURRENT_REGS)
{
_alert("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n",
- g_current_regs[REG_MFLO], g_current_regs[REG_MFHI],
- g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
+ CURRENT_REGS[REG_MFLO], CURRENT_REGS[REG_MFHI],
+ CURRENT_REGS[REG_EPC], CURRENT_REGS[REG_STATUS]);
_alert("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n",
- g_current_regs[REG_AT], g_current_regs[REG_V0],
- g_current_regs[REG_V1], g_current_regs[REG_A0],
- g_current_regs[REG_A1], g_current_regs[REG_A2],
- g_current_regs[REG_A3]);
+ CURRENT_REGS[REG_AT], CURRENT_REGS[REG_V0],
+ CURRENT_REGS[REG_V1], CURRENT_REGS[REG_A0],
+ CURRENT_REGS[REG_A1], CURRENT_REGS[REG_A2],
+ CURRENT_REGS[REG_A3]);
_alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x "
"T6:%08x T7:%08x\n",
- g_current_regs[REG_T0], g_current_regs[REG_T1],
- g_current_regs[REG_T2], g_current_regs[REG_T3],
- g_current_regs[REG_T4], g_current_regs[REG_T5],
- g_current_regs[REG_T6], g_current_regs[REG_T7]);
+ CURRENT_REGS[REG_T0], CURRENT_REGS[REG_T1],
+ CURRENT_REGS[REG_T2], CURRENT_REGS[REG_T3],
+ CURRENT_REGS[REG_T4], CURRENT_REGS[REG_T5],
+ CURRENT_REGS[REG_T6], CURRENT_REGS[REG_T7]);
_alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
"S6:%08x S7:%08x\n",
- g_current_regs[REG_S0], g_current_regs[REG_S1],
- g_current_regs[REG_S2], g_current_regs[REG_S3],
- g_current_regs[REG_S4], g_current_regs[REG_S5],
- g_current_regs[REG_S6], g_current_regs[REG_S7]);
+ CURRENT_REGS[REG_S0], CURRENT_REGS[REG_S1],
+ CURRENT_REGS[REG_S2], CURRENT_REGS[REG_S3],
+ CURRENT_REGS[REG_S4], CURRENT_REGS[REG_S5],
+ CURRENT_REGS[REG_S6], CURRENT_REGS[REG_S7]);
#ifdef MIPS32_SAVE_GP
_alert("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n",
- g_current_regs[REG_T8], g_current_regs[REG_T9],
- g_current_regs[REG_GP], g_current_regs[REG_SP],
- g_current_regs[REG_FP], g_current_regs[REG_RA]);
+ CURRENT_REGS[REG_T8], CURRENT_REGS[REG_T9],
+ CURRENT_REGS[REG_GP], CURRENT_REGS[REG_SP],
+ CURRENT_REGS[REG_FP], CURRENT_REGS[REG_RA]);
#else
_alert("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n",
- g_current_regs[REG_T8], g_current_regs[REG_T9],
- g_current_regs[REG_SP], g_current_regs[REG_FP],
- g_current_regs[REG_RA]);
+ CURRENT_REGS[REG_T8], CURRENT_REGS[REG_T9],
+ CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP],
+ CURRENT_REGS[REG_RA]);
#endif
}
}
@@ -202,7 +202,7 @@ void up_dumpstate(void)
sp = g_intstackbase;
_alert("sp: %08x\n", sp);
}
- else if (g_current_regs)
+ else if (CURRENT_REGS)
{
_alert("ERROR: Stack pointer is not within the interrupt stack\n");
up_stackdump(istackbase - istacksize, istackbase);
diff --git a/arch/mips/src/mips32/up_initialstate.c b/arch/mips/src/mips32/up_initialstate.c
index 9ed7939..6ce523c 100644
--- a/arch/mips/src/mips32/up_initialstate.c
+++ b/arch/mips/src/mips32/up_initialstate.c
@@ -63,7 +63,7 @@
* the processor specific portions of the new TCB.
*
* This function must setup the initial architecture registers
- * and/or stack so that execution will begin at tcb->start
+ * and/or stack so that execution will begin at tcb->start
* on the next context switch.
*
****************************************************************************/
@@ -80,7 +80,7 @@ void up_initial_state(struct tcb_s *tcb)
/* Save the initial stack pointer. Hmmm.. the stack is set to the very
* beginning of the stack region. Some functions may want to store data on
* the caller's stack and it might be good to reserve some space. However,
- * only the start function would do that and we have control over that one
+ * only the start function would do that and we have control over that one.
*/
xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c
index 3adb1de..c9d3473 100644
--- a/arch/mips/src/mips32/up_releasepending.c
+++ b/arch/mips/src/mips32/up_releasepending.c
@@ -86,7 +86,7 @@ void up_release_pending(void)
/* Are we operating in interrupt context? */
- if (g_current_regs)
+ if (CURRENT_REGS)
{
/* Yes, then we have to do things differently.
* Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c
index addd44b..d9fdffc 100644
--- a/arch/mips/src/mips32/up_reprioritizertr.c
+++ b/arch/mips/src/mips32/up_reprioritizertr.c
@@ -140,7 +140,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
/* Are we in an interrupt handler? */
- if (g_current_regs)
+ if (CURRENT_REGS)
{
/* Yes, then we have to do things differently.
* Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/mips32/up_schedulesigaction.c b/arch/mips/src/mips32/up_schedulesigaction.c
index b8bf89d..ad31e5e 100644
--- a/arch/mips/src/mips32/up_schedulesigaction.c
+++ b/arch/mips/src/mips32/up_schedulesigaction.c
@@ -107,8 +107,8 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* being delivered to the currently executing task.
*/
- sinfo("rtcb=0x%p g_current_regs=0x%p\n",
- this_task(), g_current_regs);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n",
+ this_task(), CURRENT_REGS);
if (tcb == this_task())
{
@@ -116,7 +116,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* a task is signalling itself for some reason.
*/
- if (!g_current_regs)
+ if (!CURRENT_REGS)
{
/* In this case just deliver the signal now. */
@@ -143,18 +143,18 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/
tcb->xcp.sigdeliver = sigdeliver;
- tcb->xcp.saved_epc = g_current_regs[REG_EPC];
- tcb->xcp.saved_status = g_current_regs[REG_STATUS];
+ tcb->xcp.saved_epc = CURRENT_REGS[REG_EPC];
+ tcb->xcp.saved_status = CURRENT_REGS[REG_STATUS];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
- g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver;
- status = g_current_regs[REG_STATUS];
+ CURRENT_REGS[REG_EPC] = (uint32_t)up_sigdeliver;
+ status = CURRENT_REGS[REG_STATUS];
status &= ~CP0_STATUS_IM_MASK;
status |= CP0_STATUS_IM_SWINTS;
- g_current_regs[REG_STATUS] = status;
+ CURRENT_REGS[REG_STATUS] = status;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
@@ -164,7 +164,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n",
tcb->xcp.saved_epc, tcb->xcp.saved_status,
- g_current_regs[REG_EPC], g_current_regs[REG_STATUS]);
+ CURRENT_REGS[REG_EPC], CURRENT_REGS[REG_STATUS]);
}
}
diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c
index a372007..600dbad 100644
--- a/arch/mips/src/mips32/up_swint0.c
+++ b/arch/mips/src/mips32/up_swint0.c
@@ -138,7 +138,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
uint32_t *regs = (uint32_t *)context;
uint32_t cause;
- DEBUGASSERT(regs && regs == g_current_regs);
+ DEBUGASSERT(regs && regs == CURRENT_REGS);
/* Software interrupt 0 is invoked with REG_A0 (REG_R4) = system call
* command and REG_A1-3 and REG_T0-2 (REG_R5-10) = variable number of
@@ -173,7 +173,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
case SYS_restore_context:
{
DEBUGASSERT(regs[REG_A1] != 0);
- g_current_regs = (uint32_t *)regs[REG_A1];
+ CURRENT_REGS = (uint32_t *)regs[REG_A1];
}
break;
@@ -197,7 +197,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
{
DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
up_copystate((uint32_t *)regs[REG_A1], regs);
- g_current_regs = (uint32_t *)regs[REG_A2];
+ CURRENT_REGS = (uint32_t *)regs[REG_A2];
}
break;
@@ -227,7 +227,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
* the original mode.
*/
- g_current_regs[REG_EPC] = rtcb->xcp.syscall[index].sysreturn;
+ CURRENT_REGS[REG_EPC] = rtcb->xcp.syscall[index].sysreturn;
#error "Missing logic -- need to restore the original mode"
rtcb->xcp.nsyscalls = index;
@@ -254,7 +254,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
/* Verify that the SYS call number is within range */
- DEBUGASSERT(g_current_regs[REG_A0] < SYS_maxsyscall);
+ DEBUGASSERT(CURRENT_REGS[REG_A0] < SYS_maxsyscall);
/* Make sure that we got here that there is a no saved syscall
* return address. We cannot yet handle nested system calls.
@@ -273,7 +273,7 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
/* Offset R0 to account for the reserved values */
- g_current_regs[REG_R0] -= CONFIG_SYS_RESERVED;
+ CURRENT_REGS[REG_R0] -= CONFIG_SYS_RESERVED;
/* Indicate that we are in a syscall handler. */
@@ -288,10 +288,10 @@ int up_swint0(int irq, FAR void *context, FAR void *arg)
/* Report what happened. That might difficult in the case of a context switch */
#ifdef CONFIG_DEBUG_SYSCALL_INFO
- if (regs != g_current_regs)
+ if (regs != CURRENT_REGS)
{
svcinfo("SWInt Return: Context switch!\n");
- up_registerdump((const uint32_t *)g_current_regs);
+ up_registerdump((const uint32_t *)CURRENT_REGS);
}
else
{
diff --git a/arch/mips/src/mips32/up_unblocktask.c b/arch/mips/src/mips32/up_unblocktask.c
index c5ca479..56e6235 100644
--- a/arch/mips/src/mips32/up_unblocktask.c
+++ b/arch/mips/src/mips32/up_unblocktask.c
@@ -100,7 +100,7 @@ void up_unblock_task(struct tcb_s *tcb)
/* Are we in an interrupt handler? */
- if (g_current_regs)
+ if (CURRENT_REGS)
{
/* Yes, then we have to do things differently.
* Just copy the g_current_regs into the OLD rtcb.
diff --git a/arch/mips/src/pic32mx/pic32mx-decodeirq.c b/arch/mips/src/pic32mx/pic32mx-decodeirq.c
index 912cb3c..82c9ec4 100644
--- a/arch/mips/src/pic32mx/pic32mx-decodeirq.c
+++ b/arch/mips/src/pic32mx/pic32mx-decodeirq.c
@@ -105,11 +105,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
*/
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
- savestate = (uint32_t *)g_current_regs;
+ savestate = (uint32_t *)CURRENT_REGS;
#else
- DEBUGASSERT(g_current_regs == NULL);
+ DEBUGASSERT(CURRENT_REGS == NULL);
#endif
- g_current_regs = regs;
+ CURRENT_REGS = regs;
/* Loop while there are pending interrupts with priority greater than zero */
@@ -146,7 +146,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
* switch occurred during interrupt processing.
*/
- regs = (uint32_t *)g_current_regs;
+ regs = (uint32_t *)CURRENT_REGS;
#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
/* Check for a context switch. If a context switch occurred, then
@@ -156,12 +156,12 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
* returning from the interrupt.
*/
- if (regs != g_current_regs)
+ if (regs != CURRENT_REGS)
{
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
- up_restorefpu((uint32_t *)g_current_regs);
+ up_restorefpu((uint32_t *)CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
@@ -186,13 +186,13 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
* of fixing nested context switching. The logic here is insufficient.
*/
- g_current_regs = savestate;
- if (g_current_regs == NULL)
+ CURRENT_REGS = savestate;
+ if (CURRENT_REGS == NULL)
{
board_autoled_off(LED_INIRQ);
}
#else
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
board_autoled_off(LED_INIRQ);
#endif
diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c
index 6117bbb..332c70f 100644
--- a/arch/mips/src/pic32mx/pic32mx-exception.c
+++ b/arch/mips/src/pic32mx/pic32mx-exception.c
@@ -177,7 +177,7 @@ uint32_t *pic32mx_exception(uint32_t *regs)
/* Crash with currents_regs set so that we can dump the register contents. */
- g_current_regs = regs;
+ CURRENT_REGS = regs;
PANIC();
return regs; /* Won't get here */
}
diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c
index a45ccaf..5b4f729 100644
--- a/arch/mips/src/pic32mx/pic32mx-irq.c
+++ b/arch/mips/src/pic32mx/pic32mx-irq.c
@@ -68,7 +68,7 @@
* Public Data
****************************************************************************/
-volatile uint32_t *g_current_regs;
+volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Data
@@ -159,7 +159,7 @@ void up_irqinitialize(void)
/* currents_regs is non-NULL only while processing an interrupt */
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
/* And finally, enable interrupts */
diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
index 03712a4..fa909db 100644
--- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c
+++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
@@ -105,11 +105,11 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
*/
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
- savestate = (uint32_t *)g_current_regs;
+ savestate = (uint32_t *)CURRENT_REGS;
#else
- DEBUGASSERT(g_current_regs == NULL);
+ DEBUGASSERT(CURRENT_REGS == NULL);
#endif
- g_current_regs = regs;
+ CURRENT_REGS = regs;
/* Loop while there are pending interrupts with priority greater than zero */
@@ -146,7 +146,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
* switch occurred during interrupt processing.
*/
- regs = (uint32_t *)g_current_regs;
+ regs = (uint32_t *)CURRENT_REGS;
#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
/* Check for a context switch. If a context switch occurred, then
@@ -156,12 +156,12 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
* returning from the interrupt.
*/
- if (regs != g_current_regs)
+ if (regs != CURRENT_REGS)
{
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
- up_restorefpu((uint32_t *)g_current_regs);
+ up_restorefpu((uint32_t *)CURRENT_REGS);
#endif
#ifdef CONFIG_ARCH_ADDRENV
@@ -186,13 +186,13 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
* of fixing nested context switching. The logic here is insufficient.
*/
- g_current_regs = savestate;
- if (g_current_regs == NULL)
+ CURRENT_REGS = savestate;
+ if (CURRENT_REGS == NULL)
{
board_autoled_off(LED_INIRQ);
}
#else
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
board_autoled_off(LED_INIRQ);
#endif
diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c
index c6ce5ee..433c518 100644
--- a/arch/mips/src/pic32mz/pic32mz-exception.c
+++ b/arch/mips/src/pic32mz/pic32mz-exception.c
@@ -177,7 +177,7 @@ uint32_t *pic32mz_exception(uint32_t *regs)
/* Crash with currents_regs set so that we can dump the register contents. */
- g_current_regs = regs;
+ CURRENT_REGS = regs;
PANIC();
return regs; /* Won't get here */
}
diff --git a/arch/mips/src/pic32mz/pic32mz-irq.c b/arch/mips/src/pic32mz/pic32mz-irq.c
index 999e99a..11a5fb6 100644
--- a/arch/mips/src/pic32mz/pic32mz-irq.c
+++ b/arch/mips/src/pic32mz/pic32mz-irq.c
@@ -73,7 +73,13 @@
* Public Data
****************************************************************************/
-volatile uint32_t *g_current_regs;
+/* g_current_regs holds a references to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Data
@@ -241,7 +247,7 @@ void up_irqinitialize(void)
/* currents_regs is non-NULL only while processing an interrupt */
- g_current_regs = NULL;
+ CURRENT_REGS = NULL;
/* And finally, enable interrupts */
[incubator-nuttx] 02/03: pic32mz-head.S: Add showprogress macro
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch pr187
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a2cf03fba9309cfa347dee4de381c6f30a8ab8fb
Author: Ouss4 <ab...@gmail.com>
AuthorDate: Fri Jan 24 15:02:41 2020 +0000
pic32mz-head.S: Add showprogress macro
---
arch/mips/src/pic32mz/pic32mz-head.S | 74 ++++++++++++++++++++++++++++++------
1 file changed, 62 insertions(+), 12 deletions(-)
diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S
index ad237ae..ae8c02f 100644
--- a/arch/mips/src/pic32mz/pic32mz-head.S
+++ b/arch/mips/src/pic32mz/pic32mz-head.S
@@ -81,25 +81,27 @@
*
* 5) Idle thread stack:
* Start: _ebss
- * End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE
+ * End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE
* 6) Optional interrupt stack
- * Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
- * End(+1): _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+ * Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
+ * End(+1): _ebss + CONFIG_IDLETHREAD_STACKSIZE +
+ (CONFIG_ARCH_INTERRUPTSTACK & ~3)
* 6a) Heap (without interrupt stack)
- * Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE
+ * Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE
* End(+1): to the end of memory
* 6b) Heap (with interrupt stack)
- * Start: _ebss+CONFIG_IDLETHREAD_STACKSIZE+(CONFIG_ARCH_INTERRUPTSTACK & ~3)
+ * Start: _ebss + CONFIG_IDLETHREAD_STACKSIZE +
+ (CONFIG_ARCH_INTERRUPTSTACK & ~3)
* End(+1): to the end of memory
*/
#define PIC32MZ_STACK_BASE _ebss
-#define PIC32MZ_STACK_TOP _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+#define PIC32MZ_STACK_TOP _ebss + CONFIG_IDLETHREAD_STACKSIZE - 4
#if CONFIG_ARCH_INTERRUPTSTACK > 3
# define PIC32MZ_INTSTACK_BASE PIC32MZ_STACK_TOP
# define PIC32MZ_INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~3)
-# define PIC32MZ_INTSTACK_TOP PIC32MZ_STACK_TOP+PIC32MZ_INTSTACK_SIZE
+# define PIC32MZ_INTSTACK_TOP PIC32MZ_STACK_TOP + PIC32MZ_INTSTACK_SIZE
# define PIC32MZ_HEAP_BASE PIC32MZ_INTSTACK_TOP
#else
# define PIC32MZ_HEAP_BASE PIC32MZ_STACK_TOP
@@ -146,6 +148,28 @@
#endif
/****************************************************************************
+ * Assembly Language Macros
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ * Print a character on the UART to show boot status. This macro will
+ * modify t0 and a0.
+ *
+ ****************************************************************************/
+
+ .macro showprogress, code
+#ifdef CONFIG_DEBUG_FEATURES
+ la t0, up_lowputc
+ la a0, \code
+ jalr ra, t0
+ nop
+#endif
+ .endm
+
+/****************************************************************************
* Public Symbols
****************************************************************************/
@@ -170,10 +194,16 @@
.global nx_start
.global pic32mz_exception
.global pic32mz_decodeirq
+ .global pic32mz_lowinit
#ifdef CONFIG_PIC32MZ_NMIHANDLER
.global pic32mz_donmi
#endif
+#ifdef CONFIG_DEBUG_FEATURES
+ .global pic32mz_consoleinit
+ .global up_lowputc
+#endif
+
/* This file contains 32-bit assembly code */
.set nomips16
@@ -441,6 +471,12 @@ __start:
mtc0 t3, PIC32MZ_CP0_SRSCTL /* Restore SRSCtl */
ehb
+ la t0, pic32mz_consoleinit
+ jalr ra, t0
+ nop
+
+ showprogress 'A'
+
#if defined (CONFIG_MIPS32_ICACHE) || defined (CONFIG_MIPS32_DCACHE)
/* Initialize K0 Cache. The cache resets in an indeterminate state.
* We need to clear the tags and invalidate any data.
@@ -456,7 +492,7 @@ __start:
mtc0 zero, PIC32MZ_CP0_TAGLO
ehb
-#ifdef CONFIG_MIPS32_ICACHE
+# ifdef CONFIG_MIPS32_ICACHE
/* Init I-Cache (Copy content of TagLo) */
li t0, PIC32MZ_KSEG0_IBASE
@@ -465,9 +501,9 @@ __start:
addu t0, t0, PIC32MZ_ILINE_SIZE
bne t0, t1, .icacheloop
cache PIC32MZ_INDEXSTORETAG_I, -4(t0)
-#endif
+# endif
-#ifdef CONFIG_MIPS32_DCACHE
+# ifdef CONFIG_MIPS32_DCACHE
/* Init D-Cache (Copy content of TagLo) */
li t0, PIC32MZ_KSEG0_DBASE
@@ -476,12 +512,14 @@ __start:
addu t0, t0, PIC32MZ_DLINE_SIZE
bne t0, t1, .dcacheloop
cache PIC32MZ_INDEXSTORETAG_D, -4(t0)
-#endif
+# endif
/* Force memory synchronization */
sync
+ showprogress 'B'
+
#endif /* CONFIG_MIPS32_ICACHE || CONFIG_MIPS32_DCACHE */
/* Set the cache algorithm.
@@ -496,6 +534,8 @@ __start:
ori t0, K0_CACHE_ALGORITHM
mtc0 t0, PIC32MZ_CP0_CONFIG
+ showprogress 'C'
+
/* Clear uninitialized data sections */
la t0, _sbss
@@ -514,6 +554,8 @@ __start:
bltu t0, t1, .Lbssloop
nop
+ showprogress 'D'
+
/* Copy initialized data from program flash to data memory */
la t0, _data_loaddr
@@ -532,6 +574,8 @@ __start:
bltu t1, t2, .Ldataloop
nop
+ showprogress 'E'
+
/* If there are no RAM functions, skip the next two sections --
* copying RAM functions from program flash to data memory and
* initializing bus matrix registers.
@@ -570,6 +614,9 @@ __start:
la t1, _bmxdupba_address
la t2, PIC32MZ_BMX_DUPBA
sw t1, 0(t2)
+
+ showprogress 'F'
+
.Lnoramfuncs:
#endif
@@ -643,6 +690,9 @@ __start:
or t0, t0, CP0_CONFIG3_ISAONEXC /* Specify microMIPS mode on exceptions */
mtc0 t0, MIPS32_CP0_CONFIG3 /* Update CONFIG3 register */
#endif
+ showprogress 'G'
+
+ showprogress '\n'
/* Start NuttX. We do this via a thunk in the text section so that
* a normal jump and link can be used, enabling the startup code
@@ -768,7 +818,7 @@ __start_nuttx:
/* Perform low level initialization */
la t0, pic32mz_lowinit
- jalr ra, t0
+ jalr ra, t0
nop
/* Call nx_start */
[incubator-nuttx] 03/03: arch/mips/pic32mz/pic32mz-lowconsole.c:
Wait for the transfert to complet when using up_lowputc.
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch pr187
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit fb1b7b0dc7dfe50f7d21c1bdb0463be86c1b11e3
Author: Ouss4 <ab...@gmail.com>
AuthorDate: Fri Jan 31 00:52:38 2020 +0000
arch/mips/pic32mz/pic32mz-lowconsole.c: Wait for the transfert to
complet when using up_lowputc.
---
arch/mips/src/pic32mz/pic32mz-lowconsole.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/src/pic32mz/pic32mz-lowconsole.c b/arch/mips/src/pic32mz/pic32mz-lowconsole.c
index 21b8125..6c3fa90 100644
--- a/arch/mips/src/pic32mz/pic32mz-lowconsole.c
+++ b/arch/mips/src/pic32mz/pic32mz-lowconsole.c
@@ -493,5 +493,8 @@ void up_lowputc(char ch)
pic32mz_putreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_TXREG_OFFSET,
(uint32_t)ch);
+
+ while ((pic32mz_getreg(PIC32MZ_CONSOLE_BASE, PIC32MZ_UART_STA_OFFSET) &
+ UART_STA_UTRMT) == 0);
#endif
}