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Posted to commits@mynewt.apache.org by st...@apache.org on 2016/08/04 23:15:14 UTC
incubator-mynewt-core git commit: re-enable compilation for all nrf52
based devboards. focus on nrf51 implementation next.
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/sterly_refactor 8ab78a812 -> a2345669a
re-enable compilation for all nrf52 based devboards. focus on nrf51 implementation next.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/a2345669
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/a2345669
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/a2345669
Branch: refs/heads/sterly_refactor
Commit: a2345669ae00a9b044883683c5aacc549e9638fd
Parents: 8ab78a8
Author: Sterling Hughes <st...@apache.org>
Authored: Thu Aug 4 16:15:05 2016 -0700
Committer: Sterling Hughes <st...@apache.org>
Committed: Thu Aug 4 16:15:05 2016 -0700
----------------------------------------------------------------------
hw/bsp/arduino_primo_nrf52/include/bsp/boards.h | 0
.../include/bsp/cmsis_nvic.h | 2 +-
.../include/bsp/nrf_drv_config.h | 464 +++++++++++++++++++
hw/bsp/arduino_primo_nrf52/pkg.yml | 3 +-
hw/bsp/arduino_primo_nrf52/src/system_nrf52.c | 68 +--
hw/bsp/bmd300eval/include/bsp/boards.h | 0
hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h | 2 +-
hw/bsp/bmd300eval/include/bsp/nrf_drv_config.h | 464 +++++++++++++++++++
hw/bsp/bmd300eval/pkg.yml | 3 +-
hw/bsp/bmd300eval/src/system_nrf52.c | 68 +--
hw/bsp/nrf52pdk/include/bsp/boards.h | 0
hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h | 2 +-
hw/bsp/nrf52pdk/include/bsp/nrf_drv_config.h | 464 +++++++++++++++++++
hw/bsp/nrf52pdk/pkg.yml | 3 +-
hw/bsp/nrf52pdk/src/system_nrf52.c | 68 +--
hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c | 1 +
16 files changed, 1504 insertions(+), 108 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/arduino_primo_nrf52/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/include/bsp/boards.h b/hw/bsp/arduino_primo_nrf52/include/bsp/boards.h
new file mode 100644
index 0000000..e69de29
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/arduino_primo_nrf52/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/include/bsp/cmsis_nvic.h b/hw/bsp/arduino_primo_nrf52/include/bsp/cmsis_nvic.h
index 6f07f11..856f7d0 100644
--- a/hw/bsp/arduino_primo_nrf52/include/bsp/cmsis_nvic.h
+++ b/hw/bsp/arduino_primo_nrf52/include/bsp/cmsis_nvic.h
@@ -12,7 +12,7 @@
#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
-#include "mcu/nrf52.h"
+#include "nrf52.h"
#ifdef __cplusplus
extern "C" {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/arduino_primo_nrf52/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/include/bsp/nrf_drv_config.h b/hw/bsp/arduino_primo_nrf52/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..d90fc99
--- /dev/null
+++ b/hw/bsp/arduino_primo_nrf52/include/bsp/nrf_drv_config.h
@@ -0,0 +1,464 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+
+#define SPI0_CONFIG_SCK_PIN 2
+#define SPI0_CONFIG_MOSI_PIN 3
+#define SPI0_CONFIG_MISO_PIN 4
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 1
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 2
+#define SPIS0_CONFIG_MOSI_PIN 3
+#define SPIS0_CONFIG_MISO_PIN 4
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 0
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN 2
+#define SPIS1_CONFIG_MOSI_PIN 3
+#define SPIS1_CONFIG_MISO_PIN 4
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 1
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 0
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 1
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 1
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 1
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/arduino_primo_nrf52/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/pkg.yml b/hw/bsp/arduino_primo_nrf52/pkg.yml
index 409ec70..b943ab5 100644
--- a/hw/bsp/arduino_primo_nrf52/pkg.yml
+++ b/hw/bsp/arduino_primo_nrf52/pkg.yml
@@ -33,8 +33,9 @@ pkg.linkerscript: "primo.ld"
pkg.linkerscript.bootloader.OVERWRITE: "boot-primo.ld"
pkg.downloadscript: primo_download.sh
pkg.debugscript: primo_debug.sh
-pkg.cflags: -DNRF52
+pkg.cflags: -DNRF52 -DSPI_MASTER_0_ENABLE
pkg.deps:
+ - hw/mcu/nordic
- hw/mcu/nordic/nrf52xxx
- libs/baselibc
pkg.deps.BLE_DEVICE:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/arduino_primo_nrf52/src/system_nrf52.c
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/system_nrf52.c b/hw/bsp/arduino_primo_nrf52/src/system_nrf52.c
index 5a76c42..86af900 100644
--- a/hw/bsp/arduino_primo_nrf52/src/system_nrf52.c
+++ b/hw/bsp/arduino_primo_nrf52/src/system_nrf52.c
@@ -31,17 +31,17 @@
#include <stdint.h>
#include <stdbool.h>
#include "bsp/cmsis_nvic.h"
-#include "mcu/nrf.h"
-#include "mcu/system_nrf52.h"
+#include "nrf.h"
+#include "system_nrf52.h"
/*lint ++flb "Enter library region" */
-#define __SYSTEM_CLOCK_16M (16000000UL)
-#define __SYSTEM_CLOCK_64M (64000000UL)
+#define __SYSTEM_CLOCK_16M (16000000UL)
+#define __SYSTEM_CLOCK_64M (64000000UL)
-static bool ftpan_32(void);
-static bool ftpan_37(void);
-static bool ftpan_36(void);
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
#if defined ( __CC_ARM )
@@ -59,54 +59,54 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
- /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
+ /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_32()){
+ if (ftpan_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
-
- /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
+
+ /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_37()){
+ if (ftpan_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
-
- /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
+
+ /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_36()){
+ if (ftpan_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
}
- /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
- * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
- SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
-
- /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
- two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
-
+
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
- defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
- if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -119,15 +119,15 @@ void SystemInit(void)
NVIC_SystemReset();
}
#endif
-
- /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
#endif
-
- /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
@@ -148,7 +148,7 @@ static bool ftpan_32(void)
return true;
}
}
-
+
return false;
}
@@ -161,7 +161,7 @@ static bool ftpan_37(void)
return true;
}
}
-
+
return false;
}
@@ -174,7 +174,7 @@ static bool ftpan_36(void)
return true;
}
}
-
+
return false;
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/bmd300eval/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/include/bsp/boards.h b/hw/bsp/bmd300eval/include/bsp/boards.h
new file mode 100644
index 0000000..e69de29
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h b/hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h
index 6f07f11..856f7d0 100644
--- a/hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h
+++ b/hw/bsp/bmd300eval/include/bsp/cmsis_nvic.h
@@ -12,7 +12,7 @@
#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
-#include "mcu/nrf52.h"
+#include "nrf52.h"
#ifdef __cplusplus
extern "C" {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/bmd300eval/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/include/bsp/nrf_drv_config.h b/hw/bsp/bmd300eval/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..d90fc99
--- /dev/null
+++ b/hw/bsp/bmd300eval/include/bsp/nrf_drv_config.h
@@ -0,0 +1,464 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+
+#define SPI0_CONFIG_SCK_PIN 2
+#define SPI0_CONFIG_MOSI_PIN 3
+#define SPI0_CONFIG_MISO_PIN 4
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 1
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 2
+#define SPIS0_CONFIG_MOSI_PIN 3
+#define SPIS0_CONFIG_MISO_PIN 4
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 0
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN 2
+#define SPIS1_CONFIG_MOSI_PIN 3
+#define SPIS1_CONFIG_MISO_PIN 4
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 1
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 0
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 1
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 1
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 1
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/bmd300eval/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/pkg.yml b/hw/bsp/bmd300eval/pkg.yml
index 60d88ff..5cc570d 100644
--- a/hw/bsp/bmd300eval/pkg.yml
+++ b/hw/bsp/bmd300eval/pkg.yml
@@ -32,8 +32,9 @@ pkg.linkerscript: "bmd300eval.ld"
pkg.linkerscript.bootloader.OVERWRITE: "boot-bmd300eval.ld"
pkg.downloadscript: bmd300eval_download.sh
pkg.debugscript: bmd300eval_debug.sh
-pkg.cflags: -DNRF52 -DBSP_HAS_32768_XTAL
+pkg.cflags: -DNRF52 -DBSP_HAS_32768_XTAL -DSPI_MASTER_0_ENABLE
pkg.deps:
+ - hw/mcu/nordic
- hw/mcu/nordic/nrf52xxx
- libs/baselibc
pkg.deps.BLE_DEVICE:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/bmd300eval/src/system_nrf52.c
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/system_nrf52.c b/hw/bsp/bmd300eval/src/system_nrf52.c
index 5a76c42..86af900 100644
--- a/hw/bsp/bmd300eval/src/system_nrf52.c
+++ b/hw/bsp/bmd300eval/src/system_nrf52.c
@@ -31,17 +31,17 @@
#include <stdint.h>
#include <stdbool.h>
#include "bsp/cmsis_nvic.h"
-#include "mcu/nrf.h"
-#include "mcu/system_nrf52.h"
+#include "nrf.h"
+#include "system_nrf52.h"
/*lint ++flb "Enter library region" */
-#define __SYSTEM_CLOCK_16M (16000000UL)
-#define __SYSTEM_CLOCK_64M (64000000UL)
+#define __SYSTEM_CLOCK_16M (16000000UL)
+#define __SYSTEM_CLOCK_64M (64000000UL)
-static bool ftpan_32(void);
-static bool ftpan_37(void);
-static bool ftpan_36(void);
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
#if defined ( __CC_ARM )
@@ -59,54 +59,54 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
- /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
+ /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_32()){
+ if (ftpan_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
-
- /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
+
+ /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_37()){
+ if (ftpan_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
-
- /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
+
+ /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_36()){
+ if (ftpan_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
}
- /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
- * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
- SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
-
- /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
- two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
-
+
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
- defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
- if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -119,15 +119,15 @@ void SystemInit(void)
NVIC_SystemReset();
}
#endif
-
- /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
#endif
-
- /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
@@ -148,7 +148,7 @@ static bool ftpan_32(void)
return true;
}
}
-
+
return false;
}
@@ -161,7 +161,7 @@ static bool ftpan_37(void)
return true;
}
}
-
+
return false;
}
@@ -174,7 +174,7 @@ static bool ftpan_36(void)
return true;
}
}
-
+
return false;
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/nrf52pdk/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52pdk/include/bsp/boards.h b/hw/bsp/nrf52pdk/include/bsp/boards.h
new file mode 100644
index 0000000..e69de29
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h b/hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
index 6f07f11..856f7d0 100644
--- a/hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
+++ b/hw/bsp/nrf52pdk/include/bsp/cmsis_nvic.h
@@ -12,7 +12,7 @@
#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
-#include "mcu/nrf52.h"
+#include "nrf52.h"
#ifdef __cplusplus
extern "C" {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/nrf52pdk/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52pdk/include/bsp/nrf_drv_config.h b/hw/bsp/nrf52pdk/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..d90fc99
--- /dev/null
+++ b/hw/bsp/nrf52pdk/include/bsp/nrf_drv_config.h
@@ -0,0 +1,464 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+
+#define SPI0_CONFIG_SCK_PIN 2
+#define SPI0_CONFIG_MOSI_PIN 3
+#define SPI0_CONFIG_MISO_PIN 4
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 1
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 2
+#define SPIS0_CONFIG_MOSI_PIN 3
+#define SPIS0_CONFIG_MISO_PIN 4
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 0
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN 2
+#define SPIS1_CONFIG_MOSI_PIN 3
+#define SPIS1_CONFIG_MISO_PIN 4
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 1
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 0
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 1
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 1
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 1
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/nrf52pdk/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52pdk/pkg.yml b/hw/bsp/nrf52pdk/pkg.yml
index 6646be7..61afde8 100644
--- a/hw/bsp/nrf52pdk/pkg.yml
+++ b/hw/bsp/nrf52pdk/pkg.yml
@@ -32,8 +32,9 @@ pkg.linkerscript: "nrf52pdk.ld"
pkg.linkerscript.bootloader.OVERWRITE: "boot-nrf52pdk.ld"
pkg.downloadscript: nrf52pdk_download.sh
pkg.debugscript: nrf52pdk_debug.sh
-pkg.cflags: -DNRF52
+pkg.cflags: -DNRF52 -DSPI_MASTER_0_ENABLE
pkg.deps:
+ - hw/mcu/nordic
- hw/mcu/nordic/nrf52xxx
- libs/baselibc
pkg.deps.BLE_DEVICE:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/bsp/nrf52pdk/src/system_nrf52.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52pdk/src/system_nrf52.c b/hw/bsp/nrf52pdk/src/system_nrf52.c
index 5a76c42..86af900 100644
--- a/hw/bsp/nrf52pdk/src/system_nrf52.c
+++ b/hw/bsp/nrf52pdk/src/system_nrf52.c
@@ -31,17 +31,17 @@
#include <stdint.h>
#include <stdbool.h>
#include "bsp/cmsis_nvic.h"
-#include "mcu/nrf.h"
-#include "mcu/system_nrf52.h"
+#include "nrf.h"
+#include "system_nrf52.h"
/*lint ++flb "Enter library region" */
-#define __SYSTEM_CLOCK_16M (16000000UL)
-#define __SYSTEM_CLOCK_64M (64000000UL)
+#define __SYSTEM_CLOCK_16M (16000000UL)
+#define __SYSTEM_CLOCK_64M (64000000UL)
-static bool ftpan_32(void);
-static bool ftpan_37(void);
-static bool ftpan_36(void);
+static bool ftpan_32(void);
+static bool ftpan_37(void);
+static bool ftpan_36(void);
#if defined ( __CC_ARM )
@@ -59,54 +59,54 @@ void SystemCoreClockUpdate(void)
void SystemInit(void)
{
- /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
+ /* Workaround for FTPAN-32 "DIF: Debug session automatically enables TracePort pins" found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_32()){
+ if (ftpan_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
-
- /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
+
+ /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_37()){
+ if (ftpan_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
-
- /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
+
+ /* Workaround for FTPAN-36 "CLOCK: Some registers are not reset when expected." found at Product Anomaly document
for your device located at https://www.nordicsemi.com/ */
- if (ftpan_36()){
+ if (ftpan_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
}
- /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
- * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+ /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+ * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
- SCB->CPACR |= (3UL << 20) | (3UL << 22);
+ SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
-
- /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
- two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+
+ /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+ two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
- while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+ while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
NVIC_SystemReset();
}
#endif
-
+
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
- defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+ defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
- if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+ if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -119,15 +119,15 @@ void SystemInit(void)
NVIC_SystemReset();
}
#endif
-
- /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+
+ /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
#endif
-
- /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+
+ /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
@@ -148,7 +148,7 @@ static bool ftpan_32(void)
return true;
}
}
-
+
return false;
}
@@ -161,7 +161,7 @@ static bool ftpan_37(void)
return true;
}
}
-
+
return false;
}
@@ -174,7 +174,7 @@ static bool ftpan_36(void)
return true;
}
}
-
+
return false;
}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a2345669/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c b/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
index 7ede252..2b5d58f 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_os_tick.c
@@ -37,6 +37,7 @@
#define OS_TICK_COUNTER 1 /* capture current timer value */
#define OS_TICK_PRESCALER 4 /* prescaler to generate 1MHz timer freq */
#define TIMER_LT(__t1, __t2) ((int32_t)((__t1) - (__t2)) < 0)
+#define TIMER_COMPARE_INT_MASK(ccreg) (1UL << ((ccreg) + 16))
#endif
struct hal_os_tick