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Posted to commits@mynewt.apache.org by ut...@apache.org on 2019/09/24 15:36:46 UTC
[mynewt-core] 05/05: [STM32F0] Add syscfg clocking system
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit f971e2d0f9e548ef99ccf4e87d11d84605b309ee
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Wed Sep 4 15:31:23 2019 -0300
[STM32F0] Add syscfg clocking system
---
.../nucleo-f030r8/include/bsp/stm32f0xx_hal_conf.h | 50 +--
hw/bsp/nucleo-f030r8/pkg.yml | 3 +-
hw/bsp/nucleo-f030r8/src/hal_bsp.c | 2 -
hw/bsp/nucleo-f030r8/src/system_stm32f0xx.c | 341 ---------------------
hw/bsp/nucleo-f030r8/syscfg.yml | 10 +-
.../nucleo-f072rb/include/bsp/stm32f0xx_hal_conf.h | 26 +-
hw/bsp/nucleo-f072rb/src/hal_bsp.c | 2 -
hw/bsp/nucleo-f072rb/src/system_stm32f0xx.c | 341 ---------------------
hw/bsp/nucleo-f072rb/syscfg.yml | 11 +-
hw/mcu/stm/stm32f0xx/src/clock_stm32f0xx.c | 232 ++++++++++++++
hw/mcu/stm/stm32f0xx/src/hal_system_clock.c | 47 ---
hw/mcu/stm/stm32f0xx/src/system_stm32f0xx.c | 240 +++++++++++++++
hw/mcu/stm/stm32f0xx/syscfg.yml | 60 +++-
13 files changed, 588 insertions(+), 777 deletions(-)
diff --git a/hw/bsp/nucleo-f030r8/include/bsp/stm32f0xx_hal_conf.h b/hw/bsp/nucleo-f030r8/include/bsp/stm32f0xx_hal_conf.h
old mode 100755
new mode 100644
index 4c4ecdd..759c73c
--- a/hw/bsp/nucleo-f030r8/include/bsp/stm32f0xx_hal_conf.h
+++ b/hw/bsp/nucleo-f030r8/include/bsp/stm32f0xx_hal_conf.h
@@ -33,12 +33,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
#define __STM32F0xx_HAL_CONF_H
+#include <syscfg/syscfg.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -48,10 +50,10 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
/* #define HAL_CAN_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_COMP_MODULE_ENABLED */
@@ -82,15 +84,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
@@ -99,24 +101,24 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator for ADC (HSI14) value.
*/
-#if !defined (HSI14_VALUE)
+#if !defined (HSI14_VALUE)
#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
@@ -125,7 +127,7 @@
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
-#if !defined (HSI48_VALUE)
+#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
@@ -134,8 +136,8 @@
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE ((uint32_t)40000)
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -160,26 +162,26 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
#define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -292,7 +294,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -301,8 +303,8 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/nucleo-f030r8/pkg.yml b/hw/bsp/nucleo-f030r8/pkg.yml
index 6028bbe..dd42775 100644
--- a/hw/bsp/nucleo-f030r8/pkg.yml
+++ b/hw/bsp/nucleo-f030r8/pkg.yml
@@ -6,7 +6,7 @@
# to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance
# with the License. You may obtain a copy of the License at
-#
+#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing,
@@ -42,4 +42,3 @@ pkg.deps.UART_0:
pkg.deps.UART_1:
- "@apache-mynewt-core/hw/drivers/uart/uart_hal"
-
diff --git a/hw/bsp/nucleo-f030r8/src/hal_bsp.c b/hw/bsp/nucleo-f030r8/src/hal_bsp.c
index 30a7e04..9b3eafa 100644
--- a/hw/bsp/nucleo-f030r8/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f030r8/src/hal_bsp.c
@@ -143,8 +143,6 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
- hal_system_clock_start();
-
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart[UART_0_DEV_ID], "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[UART_0_DEV_ID]);
diff --git a/hw/bsp/nucleo-f030r8/src/system_stm32f0xx.c b/hw/bsp/nucleo-f030r8/src/system_stm32f0xx.c
deleted file mode 100755
index 031b3e3..0000000
--- a/hw/bsp/nucleo-f030r8/src/system_stm32f0xx.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F0xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-#include "mcu/cmsis_nvic.h"
-#include "mcu/stm32_hal.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
- /* Reset PREDIV[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
- /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
- /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
- /* Set default USB clock to PLLCLK, since there is no HSI48 */
- RCC->CFGR3 |= (uint32_t)0x00000080U;
-#else
- #warning "No target selected"
-#endif
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000U;
-
- /*
- * No bootloader is used by this port, so do the REMAP here
- */
- STM32_HAL_FLASH_REMAP();
-
- /* Relocate the vector table */
- NVIC_Relocate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
- SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
- {
- /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
- SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
- else
- {
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
- SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
- /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
- STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
- STM32F091xC || STM32F098xx || STM32F030xC */
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-f030r8/syscfg.yml b/hw/bsp/nucleo-f030r8/syscfg.yml
index 25c4d8c..1db4f92 100644
--- a/hw/bsp/nucleo-f030r8/syscfg.yml
+++ b/hw/bsp/nucleo-f030r8/syscfg.yml
@@ -37,6 +37,14 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
- MCU_SYSCLK_PLL_HSI: 0
OS_MAIN_STACK_SIZE: 128
MSYS_1_BLOCK_COUNT: 0
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL12'
+ STM32_CLOCK_PREDIV: 'RCC_PREDIV_DIV1'
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_1'
+ STM32_FLASH_PREFETCH_ENABLE: 1
diff --git a/hw/bsp/nucleo-f072rb/include/bsp/stm32f0xx_hal_conf.h b/hw/bsp/nucleo-f072rb/include/bsp/stm32f0xx_hal_conf.h
index fbde468..4a00682 100644
--- a/hw/bsp/nucleo-f072rb/include/bsp/stm32f0xx_hal_conf.h
+++ b/hw/bsp/nucleo-f072rb/include/bsp/stm32f0xx_hal_conf.h
@@ -33,12 +33,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
#define __STM32F0xx_HAL_CONF_H
+#include <syscfg/syscfg.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -48,7 +50,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
@@ -82,15 +84,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
@@ -99,15 +101,15 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
@@ -166,13 +168,13 @@
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
#define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
@@ -292,7 +294,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
diff --git a/hw/bsp/nucleo-f072rb/src/hal_bsp.c b/hw/bsp/nucleo-f072rb/src/hal_bsp.c
index 706d5c6..ec7f076 100644
--- a/hw/bsp/nucleo-f072rb/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f072rb/src/hal_bsp.c
@@ -151,8 +151,6 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
- hal_system_clock_start();
-
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &hal_uart[UART_0_DEV_ID], "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[UART_0_DEV_ID]);
diff --git a/hw/bsp/nucleo-f072rb/src/system_stm32f0xx.c b/hw/bsp/nucleo-f072rb/src/system_stm32f0xx.c
deleted file mode 100644
index 031b3e3..0000000
--- a/hw/bsp/nucleo-f072rb/src/system_stm32f0xx.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F0xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-#include "mcu/cmsis_nvic.h"
-#include "mcu/stm32_hal.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI48_VALUE */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001U;
-
-#if defined (STM32F051x8) || defined (STM32F058x8)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80CU;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80CU;
-#endif /* STM32F051x8 or STM32F058x8 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
-
- /* Reset PREDIV[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
-
-#if defined (STM32F072xB) || defined (STM32F078xx)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
-#elif defined (STM32F071xB)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
-#elif defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
-#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
- /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
-#elif defined (STM32F051x8) || defined (STM32F058xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
-#elif defined (STM32F042x6) || defined (STM32F048xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
-#elif defined (STM32F070x6) || defined (STM32F070xB)
- /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
- /* Set default USB clock to PLLCLK, since there is no HSI48 */
- RCC->CFGR3 |= (uint32_t)0x00000080U;
-#else
- #warning "No target selected"
-#endif
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000U;
-
- /*
- * No bootloader is used by this port, so do the REMAP here
- */
- STM32_HAL_FLASH_REMAP();
-
- /* Relocate the vector table */
- NVIC_Relocate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
-
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
- SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- }
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
- {
- /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
- SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
- }
-#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
- else
- {
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
- SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
-#else
- /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
- STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
- STM32F091xC || STM32F098xx || STM32F030xC */
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-f072rb/syscfg.yml b/hw/bsp/nucleo-f072rb/syscfg.yml
index 7dd77fd..1d430bf 100644
--- a/hw/bsp/nucleo-f072rb/syscfg.yml
+++ b/hw/bsp/nucleo-f072rb/syscfg.yml
@@ -44,5 +44,14 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
- MCU_SYSCLK_PLL_HSI: 0
MSYS_1_BLOCK_COUNT: 0
+ STM32_CLOCK_HSI: 0
+ STM32_CLOCK_HSI48: 0
+ STM32_CLOCK_HSE: 1
+ STM32_CLOCK_HSE_BYPASS: 1
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL6'
+ STM32_CLOCK_PREDIV: 'RCC_PREDIV_DIV1'
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_1'
+ STM32_FLASH_PREFETCH_ENABLE: 1
diff --git a/hw/mcu/stm/stm32f0xx/src/clock_stm32f0xx.c b/hw/mcu/stm/stm32f0xx/src/clock_stm32f0xx.c
new file mode 100644
index 0000000..b2cf8a3
--- /dev/null
+++ b/hw/mcu/stm/stm32f0xx/src/clock_stm32f0xx.c
@@ -0,0 +1,232 @@
+/*
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "stm32f0xx_hal_pwr_ex.h"
+#include "stm32f0xx_hal_rcc.h"
+#include "stm32f0xx_hal.h"
+#include <assert.h>
+
+/*
+ * This allows an user to have a custom clock configuration by zeroing
+ * every possible clock source in the syscfg.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \
+ MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_HSI48) || \
+ MYNEWT_VAL(STM32_CLOCK_LSI)
+
+/*
+ * HSI is turned on by default, but can be turned off and use HSE/HSI48 instead.
+ */
+#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0) + \
+ (MYNEWT_VAL(STM32_CLOCK_HSI48) != 0)) < 1)
+#error "At least one of HSE, HSI or HSI48 clock sources must be enabled"
+#endif
+
+void
+SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef osc_init;
+ RCC_ClkInitTypeDef clk_init;
+ HAL_StatusTypeDef status;
+
+ /*
+ * Enable Power Control clock
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+
+ /*
+ * LSI is used to clock the independent watchdog and optionally the RTC.
+ * It can be disabled per user request, but is automatically enabled again
+ * when the IWDG is started.
+ *
+ * XXX currently the watchdog is not optional, so there's no point in
+ * disabling LSI through syscfg.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
+#if MYNEWT_VAL(STM32_CLOCK_LSI)
+ osc_init.LSIState = RCC_LSI_ON;
+#else
+ osc_init.LSIState = RCC_LSI_OFF;
+#endif
+
+ /*
+ * LSE is only used to clock the RTC.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
+#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0)
+ osc_init.LSEState = RCC_LSE_OFF;
+#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS)
+ osc_init.LSEState = RCC_LSE_BYPASS;
+#else
+ osc_init.LSEState = RCC_LSE_ON;
+#endif
+
+ /*
+ * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source)
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS)
+ osc_init.HSEState = RCC_HSE_BYPASS;
+#else
+ osc_init.HSEState = RCC_HSE_ON;
+#endif
+#endif
+
+ /*
+ * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is
+ * already turned on by default but a new calibration setting might be
+ * used. If the user chooses to turn it off, it must be turned off after
+ * SYSCLK was updated to use HSE/PLL.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSI)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_ON;
+ /* HSI calibration is not optional when HSI is enabled */
+ osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION);
+
+#if MYNEWT_VAL(STM32_CLOCK_HSI) && \
+ !IS_RCC_CALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION))
+#error "Invalid HSI calibration value"
+#endif
+#endif
+
+#if MYNEWT_VAL(STM32_CLOCK_HSI48)
+#if !defined(RCC_HSI48_SUPPORT)
+#error "HSI48 is not supported on this target"
+#endif
+
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+ osc_init.HSI48State = RCC_HSI48_ON;
+#endif
+
+ /*
+ * Default to HSE or HSI48 as PLL source when multiple high-speed sources
+ * are enabled.
+ *
+ * XXX prefering HSE over HSI48 is just an
+ */
+ osc_init.PLL.PLLState = RCC_PLL_ON;
+#if MYNEWT_VAL(STM32_CLOCK_HSE)
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#elif MYNEWT_VAL(STM32_CLOCK_HSI48)
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
+#else
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+#endif
+
+#if !IS_RCC_PLL_MUL(MYNEWT_VAL(STM32_CLOCK_PLL_MUL))
+#error "PLL MUL value is invalid"
+#endif
+
+ osc_init.PLL.PLLMUL = MYNEWT_VAL(STM32_CLOCK_PLL_MUL);
+
+ /*
+ * 04x/07x/09x implement the divider block after PLLSRC; other families
+ * do it before the signal goes into PLLSRC. When the divider is connected
+ * before the PLLSRC, it is connected only to HSE, and HSI has a
+ * non-optional /2 divider.
+ */
+#if !IS_RCC_PREDIV(MYNEWT_VAL(STM32_CLOCK_PREDIV))
+#error "PLL PREDIV value is invalid"
+#endif
+
+ osc_init.PLL.PREDIV = MYNEWT_VAL(STM32_CLOCK_PREDIV);
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ /*
+ * Select PLL as system clock source and configure the HCLK, PCLK1 and
+ * PCLK2 clocks dividers. HSI and HSE are also valid system clock sources,
+ * although there is no much point in supporting them now.
+ */
+ clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1;
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+
+#if !IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER))
+#error "AHB clock divider is invalid"
+#endif
+
+#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER))
+#error "APB1 clock divider is invalid"
+#endif
+
+#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER))
+#error "APB2 clock divider is invalid"
+#endif
+
+ clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER);
+ clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER);
+
+#if !IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY))
+#error "Flash latency value is invalid"
+#endif
+
+ status = HAL_RCC_ClockConfig(&clk_init, MYNEWT_VAL(STM32_FLASH_LATENCY));
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+#if ((MYNEWT_VAL(STM32_CLOCK_HSI) == 0) || (MYNEWT_VAL(STM32_CLOCK_HSE) == 0) || \
+ (MYNEWT_VAL(STM32_CLOCK_HSI48) == 0))
+ /*
+ * Turn off HSE/HSI/HSI48 oscillator; this must be done at the end because
+ * SYSCLK source has to be updated first.
+ */
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+#if (MYNEWT_VAL(STM32_CLOCK_HSE) == 0)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+ osc_init.HSEState = RCC_HSE_OFF;
+#endif
+#if (MYNEWT_VAL(STM32_CLOCK_HSI) == 0)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_OFF;
+#endif
+#if (MYNEWT_VAL(STM32_CLOCK_HSI48) == 0) && defined(RCC_HSI48_SUPPORT)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+ osc_init.HSI48State = RCC_HSI48_OFF;
+#endif
+
+#endif
+
+ osc_init.PLL.PLLState = RCC_PLL_NONE;
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+#if PREFETCH_ENABLE
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
+}
+#endif
diff --git a/hw/mcu/stm/stm32f0xx/src/hal_system_clock.c b/hw/mcu/stm/stm32f0xx/src/hal_system_clock.c
deleted file mode 100644
index a874ef9..0000000
--- a/hw/mcu/stm/stm32f0xx/src/hal_system_clock.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <hal/hal_system.h>
-#include <mcu/cortex_m0.h>
-#include "stm32f0xx_hal.h"
-#include "stm32f0xx_hal_rcc.h"
-
-void hal_system_clock_start(void) {
-#if MYNEWT_VAL(MCU_SYSCLK_PLL_HSI)
- RCC_OscInitTypeDef osc;
- RCC_ClkInitTypeDef clk;
-
- osc.OscillatorType = RCC_OSCILLATORTYPE_NONE;
- osc.PLL.PLLState = RCC_PLL_ON;
- osc.PLL.PLLSource = RCC_PLLSOURCE_HSI;
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- osc.PLL.PREDIV = RCC_PREDIV_DIV2;
-#endif
- osc.PLL.PLLMUL = RCC_PLL_MUL16;
- osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- assert(HAL_OK == HAL_RCC_OscConfig(&osc));
-
- clk.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
- clk.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- clk.AHBCLKDivider = RCC_SYSCLK_DIV1;
- clk.APB1CLKDivider = RCC_HCLK_DIV2;
- assert(HAL_OK == HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_1));
-#endif
-}
diff --git a/hw/mcu/stm/stm32f0xx/src/system_stm32f0xx.c b/hw/mcu/stm/stm32f0xx/src/system_stm32f0xx.c
new file mode 100644
index 0000000..6344814
--- /dev/null
+++ b/hw/mcu/stm/stm32f0xx/src/system_stm32f0xx.c
@@ -0,0 +1,240 @@
+/*
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "bsp/stm32f0xx_hal_conf.h"
+#include "stm32f0xx.h"
+#include "mcu/cmsis_nvic.h"
+#include "mcu/stm32_hal.h"
+
+/* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock there is no need to
+ call the 2 first functions listed above, since SystemCoreClock variable is
+ updated automatically.
+*/
+uint32_t SystemCoreClock;
+const uint8_t AHBPrescTable[16] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
+};
+const uint8_t APBPrescTable[8] = {
+ 0, 0, 0, 0, 1, 2, 3, 4
+};
+
+/*
+ * XXX BSP specific
+ */
+void SystemClock_Config(void);
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /*
+ * Reset the RCC clock configuration to the default reset state
+ */
+
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001U;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+ RCC->CFGR &= (uint32_t)0xF8FFB80CU;
+#else
+ /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+ RCC->CFGR &= (uint32_t)0x08FFB80CU;
+#endif /* STM32F051x8 or STM32F058x8 */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFFU;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+ /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
+
+ /* Reset PREDIV[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
+#elif defined (STM32F071xB)
+ /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+ /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+ /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+ /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+ /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+ RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
+ /* Set default USB clock to PLLCLK, since there is no HSI48 */
+ RCC->CFGR3 |= (uint32_t)0x00000080U;
+#else
+#warning "No target selected"
+#endif
+
+ /* Reset HSI14 bit */
+ RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000U;
+
+ /* Configure System Clock */
+ SystemClock_Config();
+
+ /* Update SystemCoreClock global variable */
+ SystemCoreClockUpdate();
+
+ /*
+ * TODO: Currently the supported BSPs don't use a bootloader, so
+ * the flash remapping is done here. This should be updated to allow
+ * for bootloader use.
+ */
+ STM32_HAL_FLASH_REMAP();
+
+ /* Relocate the vector table */
+ NVIC_Relocate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp;
+ uint32_t pllmull;
+ uint32_t pllsource;
+ uint32_t predivfactor;
+
+ /*
+ * Get SYSCLK source
+ */
+
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+ switch (tmp) {
+ case RCC_CFGR_SWS_HSE:
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case RCC_CFGR_SWS_PLL:
+ /*
+ * Get PLL clock source and multiplication factor
+ */
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) {
+ /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) \
+ || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+ else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) {
+ /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI48_VALUE / predivfactor) * pllmull;
+ }
+#endif
+ else {
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
+ || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
+ || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
+ SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+#else
+ /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+#endif
+ }
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /*
+ * Compute HCLK clock frequency
+ */
+
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/mcu/stm/stm32f0xx/syscfg.yml b/hw/mcu/stm/stm32f0xx/syscfg.yml
index 0857dbb..bb256f2 100644
--- a/hw/mcu/stm/stm32f0xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f0xx/syscfg.yml
@@ -29,6 +29,62 @@ syscfg.defs:
description: MCUs are of STM32F0xx family
value: 1
+ STM32_CLOCK_LSI:
+ description: Enable low-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_LSE:
+ description: Enable low-speed external clock source (aka RTC xtal)
+ value: 0
+
+ STM32_CLOCK_LSE_BYPASS:
+ description: 0 for 32768 xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSE:
+ description: Enable high-speed external clock source
+ value: 0
+
+ STM32_CLOCK_HSE_BYPASS:
+ description: 0 for xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSI:
+ description: Enable high-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_HSI_CALIBRATION:
+ description: HSI calibration value
+ value: 'RCC_HSICALIBRATION_DEFAULT'
+
+ STM32_CLOCK_HSI48:
+ description: Enable high-speed 48MHz internal clock source
+ value: 0
+
+ STM32_CLOCK_PLL_MUL:
+ description: PLL clock multiplication
+ value: 0
+
+ STM32_CLOCK_PREDIV:
+ description: Clock divider (pre or post PLL)
+ value: 0
+
+ STM32_CLOCK_AHB_DIVIDER:
+ description: AHB prescaler
+ value: 0
+
+ STM32_CLOCK_APB1_DIVIDER:
+ description: APB low-speed prescaler
+ value: 0
+
+ STM32_FLASH_LATENCY:
+ description: Number of wait-states
+ value: 0
+
+ STM32_FLASH_PREFETCH_ENABLE:
+ description: Enable pre-fetch of instructions (when latency > 0)
+ value: 0
+
STM32_HAL_SPI_HAS_FIFO:
description: This MCU has a SPI with FIFO
value: 1
@@ -53,10 +109,6 @@ syscfg.defs:
description: This MCU's Flash sector size in bytes.
value: 2048
- MCU_SYSCLK_PLL_HSI:
- description: Configure PLL as sysclock driven by HSI.
- value: 0
-
I2C_0:
description: 'I2C (TWI) interface 0'
value: 0