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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/04/03 20:20:10 UTC
[incubator-nuttx] 02/03: b-u585i-iot02a: Fix stdclock initialization
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 9d075599063a2cdb493b977d553c4782db3e74b3
Author: Michael Jung <mi...@secore.ly>
AuthorDate: Sun Apr 3 11:58:00 2022 +0200
b-u585i-iot02a: Fix stdclock initialization
Correct the respective defines to initialize the B-U585I-IOT02A clock
tree correctly by means of stm32_stdclockconfig().
---
boards/arm/stm32u5/b-u585i-iot02a/include/board.h | 77 ++++++++---------------
1 file changed, 27 insertions(+), 50 deletions(-)
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
index 81a6972498..3882eb0b48 100644
--- a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
+++ b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
@@ -43,14 +43,14 @@
*
* System Clock source : PLL (MSIS)
* SYSCLK(Hz) : 160000000 Determined by PLL configuration
- * HCLK(Hz) : 160000000 (STM32_RCC_CFGR_HPRE) (Max 160MHz)
- * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 160MHz)
- * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 160MHz)
- * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 160MHz)
- * APB3 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 160MHz)
+ * HCLK(Hz) : 160000000
+ * AHB Prescaler : 1 (STM32_RCC_CFGR2_HPRE) (160MHz)
+ * APB1 Prescaler : 1 (STM32_RCC_CFGR2_PPRE1) (160MHz)
+ * APB2 Prescaler : 1 (STM32_RCC_CFGR2_PPRE2) (160MHz)
+ * APB3 Prescaler : 1 (STM32_RCC_CFGR3_PPRE3) (160MHz)
* MSIS Frequency(Hz) : 4000000 (nominal)
* MSIK Frequency(Hz) : 4000000 (nominal)
- * PLL_MBOOST : 1
+ * PLL_MBOOST : 1 (Embedded power distribution booster)
* PLLM : 1 (STM32_PLLCFG_PLLM)
* PLLN : 80 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
@@ -70,63 +70,35 @@
#define STM32_LSI_FREQUENCY 32000
#define STM32_LSE_FREQUENCY 32768
-#define STM32_BOARD_USEMSI 1
-#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
+#define STM32_BOARD_USEMSIS 1
+#define STM32_BOARD_MSISRANGE RCC_ICSCR1_MSISRANGE_4MHZ
+#define STM32_BOARD_MSIKRANGE RCC_ICSCR1_MSIKRANGE_4MHZ
-/* prescaler common to all PLL inputs */
+/* PLL1 config; we use this to generate our system clock */
-#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
-
-/* 'main' PLL config; we use this to generate our system clock */
-
-#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55)
-#define STM32_PLLCFG_PLLP 0
-#undef STM32_PLLCFG_PLLP_ENABLED
-#define STM32_PLLCFG_PLLQ 0
-#undef STM32_PLLCFG_PLLQ_ENABLED
-#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
-#define STM32_PLLCFG_PLLR_ENABLED
-
-/* 'SAIPLL1' is not used in this application */
-
-#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
-#define STM32_PLLSAI1CFG_PLLP 0
-#undef STM32_PLLSAI1CFG_PLLP_ENABLED
-#define STM32_PLLSAI1CFG_PLLQ 0
-#undef STM32_PLLSAI1CFG_PLLQ_ENABLED
-#define STM32_PLLSAI1CFG_PLLR 0
-#undef STM32_PLLSAI1CFG_PLLR_ENABLED
-
-/* 'SAIPLL2' is not used in this application */
-
-#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
-#define STM32_PLLSAI2CFG_PLLP 0
-#undef STM32_PLLSAI2CFG_PLLP_ENABLED
-#define STM32_PLLSAI2CFG_PLLR 0
-#undef STM32_PLLSAI2CFG_PLLR_ENABLED
+#define STM32_RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(1)
+#define STM32_RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(80)
+#define STM32_RCC_PLL1DIVR_PLL1P 0
+#undef STM32_RCC_PLL1CFGR_PLL1P_ENABLED
+#define STM32_RCC_PLL1DIVR_PLL1Q 0
+#undef STM32_RCC_PLL1CFGR_PLL1Q_ENABLED
+#define STM32_RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R(2)
+#define STM32_RCC_PLL1CFGR_PLL1R_ENABLED
#define STM32_SYSCLK_FREQUENCY 160000000ul
-/* Enable CLK48; get it from HSI48 */
-
-#if defined(CONFIG_STM32U5_USBFS) || defined(CONFIG_STM32U5_RNG)
-# define STM32_USE_CLK48 1
-# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
-# define STM32_HSI48_SYNCSRC SYNCSRC_NONE
-#endif
-
-/* Enable LSE (for the RTC and for MSI autotrimming) */
+/* Enable LSE (for the RTC and for MSIS autotrimming) */
#define STM32_USE_LSE 1
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
-#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
+#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
/* Configure the APB1 prescaler */
-#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
+#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
@@ -138,13 +110,18 @@
/* Configure the APB2 prescaler */
-#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
+#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
+/* Configure the APB3 prescaler */
+
+#define STM32_RCC_CFGR3_PPRE3 RCC_CFGR3_PPRE3_HCLK /* PCLK3 = HCLK / 1 */
+#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
+
/* The timer clock frequencies are automatically defined by hardware. If the
* APB prescaler equals 1, the timer clock frequencies are set to the same
* frequency as that of the APB domain. Otherwise they are set to twice.