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Posted to commits@nuttx.apache.org by gn...@apache.org on 2020/08/23 14:26:18 UTC
[incubator-nuttx] branch master updated (9bf9bb2 -> 7a1342f)
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 9bf9bb2 Changed comments. Proposed structure.
new 4ded03a ESP32: Add support to RNG HW Driver
new 52d7d0c ESP32: Add board config to RNG driver
new 7a1342f Fix coding style and other small issues
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
.../include/xtensa/core_macros.h} | 19 +-
arch/xtensa/src/esp32/Kconfig | 8 +
arch/xtensa/src/esp32/Make.defs | 4 +
arch/xtensa/src/esp32/esp32_clockconfig.c | 25 ++-
arch/xtensa/src/esp32/esp32_clockconfig.h | 10 +-
.../intel64_rng.c => xtensa/src/esp32/esp32_rng.c} | 195 ++++++++++++++-------
.../src/esp32/hardware/wdev_reg.h} | 15 +-
.../esp32-core/configs/{nsh => random}/defconfig | 2 +
.../xtensa/esp32/esp32-core/scripts/esp32_rom.ld | 1 +
9 files changed, 193 insertions(+), 86 deletions(-)
copy arch/{x86_64/include/limits.h => xtensa/include/xtensa/core_macros.h} (74%)
copy arch/{x86_64/src/intel64/intel64_rng.c => xtensa/src/esp32/esp32_rng.c} (50%)
copy arch/{arm/src/eoss3/chip.h => xtensa/src/esp32/hardware/wdev_reg.h} (78%)
copy boards/xtensa/esp32/esp32-core/configs/{nsh => random}/defconfig (96%)
[incubator-nuttx] 02/03: ESP32: Add board config to RNG driver
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 52d7d0cb98a8a34ff6e9407948e57f7ac389afe0
Author: Alan C. Assis <ac...@gmail.com>
AuthorDate: Fri Aug 21 18:32:21 2020 -0300
ESP32: Add board config to RNG driver
---
.../esp32/esp32-core/configs/random/defconfig | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/boards/xtensa/esp32/esp32-core/configs/random/defconfig b/boards/xtensa/esp32/esp32-core/configs/random/defconfig
new file mode 100644
index 0000000..cbdb11b
--- /dev/null
+++ b/boards/xtensa/esp32/esp32-core/configs/random/defconfig
@@ -0,0 +1,51 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="xtensa"
+CONFIG_ARCH_BOARD="esp32-core"
+CONFIG_ARCH_BOARD_ESP32CORE=y
+CONFIG_ARCH_CHIP="esp32"
+CONFIG_ARCH_CHIP_ESP32=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_XTENSA=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUILTIN=y
+CONFIG_ESP32_RNG=y
+CONFIG_ESP32_UART0=y
+CONFIG_EXAMPLES_RANDOM=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=3072
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MAX_TASKS=16
+CONFIG_MM_REGIONS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=114688
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPI=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
[incubator-nuttx] 03/03: Fix coding style and other small issues
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7a1342f503f5a68f6d7d58fb36b7f7038166d7f6
Author: Alan C. Assis <ac...@gmail.com>
AuthorDate: Sun Aug 23 09:01:23 2020 -0300
Fix coding style and other small issues
---
arch/xtensa/include/xtensa/core_macros.h | 2 +-
arch/xtensa/src/esp32/Kconfig | 2 +-
arch/xtensa/src/esp32/esp32_rng.c | 4 +++-
arch/xtensa/src/esp32/hardware/wdev_reg.h | 17 -----------------
4 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/arch/xtensa/include/xtensa/core_macros.h b/arch/xtensa/include/xtensa/core_macros.h
index 5a8c2ad..7c5b16e 100644
--- a/arch/xtensa/include/xtensa/core_macros.h
+++ b/arch/xtensa/include/xtensa/core_macros.h
@@ -33,7 +33,7 @@
****************************************************************************/
#define XTHAL_GET_CCOUNT() ({ int __ccount; \
- __asm__ __volatile__("rsr.ccount %0" : \
+ __asm__ __volatile__("rsr.ccount %0":\
"=a"(__ccount)); __ccount; })
#endif /* __ARCH_XTENSA_INCUDE_XTENSA_CORE_H */
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
index 786596c..eae987e 100644
--- a/arch/xtensa/src/esp32/Kconfig
+++ b/arch/xtensa/src/esp32/Kconfig
@@ -88,7 +88,7 @@ config ESP32_RNG
bool "Random Number Generator (RNG)"
default n
depends on EXPERIMENTAL
- select ARCH_HAVE_RNG
+ select ARCH_HAVE_RNG
---help---
ESP32 supports a RNG that passed on Dieharder test suite.
diff --git a/arch/xtensa/src/esp32/esp32_rng.c b/arch/xtensa/src/esp32/esp32_rng.c
index f0561a1..2af27fd 100644
--- a/arch/xtensa/src/esp32/esp32_rng.c
+++ b/arch/xtensa/src/esp32/esp32_rng.c
@@ -144,7 +144,9 @@ static int esp32_rng_initialize(void)
static bool first_flag = true;
if (false == first_flag)
- return OK;
+ {
+ return OK;
+ }
first_flag = false;
diff --git a/arch/xtensa/src/esp32/hardware/wdev_reg.h b/arch/xtensa/src/esp32/hardware/wdev_reg.h
index c653953..2393416 100644
--- a/arch/xtensa/src/esp32/hardware/wdev_reg.h
+++ b/arch/xtensa/src/esp32/hardware/wdev_reg.h
@@ -18,23 +18,6 @@
*
****************************************************************************/
-/****************************************************************************
- * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ****************************************************************************/
-
#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_WDEV_REG_H
#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_WDEV_REG_H
[incubator-nuttx] 01/03: ESP32: Add support to RNG HW Driver
Posted by gn...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gnutt pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4ded03a673102d246f10cb3140bc590371851b2a
Author: Alan C. Assis <ac...@gmail.com>
AuthorDate: Sat Aug 22 20:55:08 2020 -0300
ESP32: Add support to RNG HW Driver
---
arch/xtensa/include/xtensa/core_macros.h | 39 +++
arch/xtensa/src/esp32/Kconfig | 8 +
arch/xtensa/src/esp32/Make.defs | 4 +
arch/xtensa/src/esp32/esp32_clockconfig.c | 25 +-
arch/xtensa/src/esp32/esp32_clockconfig.h | 10 +-
arch/xtensa/src/esp32/esp32_rng.c | 273 +++++++++++++++++++++
arch/xtensa/src/esp32/hardware/wdev_reg.h | 51 ++++
.../xtensa/esp32/esp32-core/scripts/esp32_rom.ld | 1 +
8 files changed, 405 insertions(+), 6 deletions(-)
diff --git a/arch/xtensa/include/xtensa/core_macros.h b/arch/xtensa/include/xtensa/core_macros.h
new file mode 100644
index 0000000..5a8c2ad
--- /dev/null
+++ b/arch/xtensa/include/xtensa/core_macros.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/xtensa/include/xtensa/core_macros.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCUDE_XTENSA_CORE_MACRO_H
+#define __ARCH_XTENSA_INCUDE_XTENSA_CORE_MACRO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/chip/core-isa.h>
+#include <arch/chip/tie.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define XTHAL_GET_CCOUNT() ({ int __ccount; \
+ __asm__ __volatile__("rsr.ccount %0" : \
+ "=a"(__ccount)); __ccount; })
+
+#endif /* __ARCH_XTENSA_INCUDE_XTENSA_CORE_H */
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
index c6c5834..786596c 100644
--- a/arch/xtensa/src/esp32/Kconfig
+++ b/arch/xtensa/src/esp32/Kconfig
@@ -84,6 +84,14 @@ config ESP32_RMT
---help---
No yet implemented
+config ESP32_RNG
+ bool "Random Number Generator (RNG)"
+ default n
+ depends on EXPERIMENTAL
+ select ARCH_HAVE_RNG
+ ---help---
+ ESP32 supports a RNG that passed on Dieharder test suite.
+
config ESP32_SDIO_SAVE
bool "SDIO Slave"
default n
diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs
index 3216e88..ce750f8 100644
--- a/arch/xtensa/src/esp32/Make.defs
+++ b/arch/xtensa/src/esp32/Make.defs
@@ -119,6 +119,10 @@ ifeq ($(CONFIG_ESP32_UART),y)
CMN_CSRCS += esp32_serial.c
endif
+ifeq ($(CONFIG_ESP32_RNG),y)
+CMN_CSRCS += esp32_rng.c
+endif
+
ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y)
CHIP_CSRCS += esp32_modtext.c
CMN_ASRCS += xtensa_loadstore.S
diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c
index a48e288..ef24715 100644
--- a/arch/xtensa/src/esp32/esp32_clockconfig.c
+++ b/arch/xtensa/src/esp32/esp32_clockconfig.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/xtensa/src/esp32/esp32_clockconfig.C
+ * arch/xtensa/src/esp32/esp32_clockconfig.c
*
* Mofidifed by use in NuttX by:
*
@@ -30,11 +30,20 @@
#include <stdint.h>
#include "xtensa.h"
+#include "xtensa_attr.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_soc.h"
/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
* Private Types
****************************************************************************/
@@ -57,7 +66,8 @@ enum cpu_freq_e
* Private Functions
****************************************************************************/
-extern void ets_delay_us(int delay_us);
+extern uint32_t g_ticks_per_us_pro;
+extern void ets_delay_us(int delay_us);
/****************************************************************************
* Name: esp32_set_cpu_freq
@@ -368,3 +378,14 @@ void esp32_clockconfig(void)
esp32_bbpll_configure(xtal_freq, source_freq_mhz);
esp32_set_cpu_freq(freq_mhz);
}
+
+int IRAM_ATTR esp_clk_cpu_freq(void)
+{
+ return g_ticks_per_us_pro * MHZ;
+}
+
+int IRAM_ATTR esp_clk_apb_freq(void)
+{
+ return MIN(g_ticks_per_us_pro, 80) * MHZ;
+}
+
diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.h b/arch/xtensa/src/esp32/esp32_clockconfig.h
index a552f9b..60e8e59 100644
--- a/arch/xtensa/src/esp32/esp32_clockconfig.h
+++ b/arch/xtensa/src/esp32/esp32_clockconfig.h
@@ -33,10 +33,6 @@
*
****************************************************************************/
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H
@@ -44,6 +40,8 @@
* Included Files
****************************************************************************/
+#include "xtensa_attr.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -60,4 +58,8 @@
void esp32_clockconfig(void);
+int IRAM_ATTR esp_clk_cpu_freq(void);
+
+int IRAM_ATTR esp_clk_apb_freq(void);
+
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */
diff --git a/arch/xtensa/src/esp32/esp32_rng.c b/arch/xtensa/src/esp32/esp32_rng.c
new file mode 100644
index 0000000..f0561a1
--- /dev/null
+++ b/arch/xtensa/src/esp32/esp32_rng.c
@@ -0,0 +1,273 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/esp32_rng.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <debug.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/semaphore.h>
+#include <nuttx/fs/ioctl.h>
+#include <nuttx/drivers/drivers.h>
+
+#include <arch/xtensa/core_macros.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/wdev_reg.h"
+#include "esp32_clockconfig.h"
+
+#if defined(CONFIG_ESP32_RNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int esp32_rng_initialize(void);
+static ssize_t esp32_rng_read(FAR struct file *filep, FAR char *buffer,
+ size_t buflen);
+static int esp32_rng_open(FAR struct file *filep);
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct rng_dev_s
+{
+ uint8_t *rd_buf;
+ sem_t rd_sem; /* semaphore for read RNG data */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct rng_dev_s g_rngdev;
+
+static const struct file_operations g_rngops =
+{
+ .open = esp32_rng_open, /* open */
+ .read = esp32_rng_read, /* read */
+};
+
+/****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32_random
+ ****************************************************************************/
+
+uint32_t IRAM_ATTR esp_random(void)
+{
+ /* The PRNG which implements WDEV_RANDOM register gets 2 bits
+ * of extra entropy from a hardware randomness source every APB clock cycle
+ * (provided WiFi or BT are enabled). To make sure entropy is not drained
+ * faster than it is added, this function needs to wait for at least 16 APB
+ * clock cycles after reading previous word. This implementation may
+ * actually wait a bit longer due to extra time spent in arithmetic and
+ * branch statements.
+ *
+ * As a (probably unncessary) precaution to avoid returning the
+ * RNG state as-is, the result is XORed with additional
+ * WDEV_RND_REG reads while waiting.
+ */
+
+ uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
+
+ static uint32_t last_ccount = 0;
+ uint32_t ccount;
+ uint32_t result = 0;
+
+ do
+ {
+ ccount = XTHAL_GET_CCOUNT();
+ result ^= getreg32(WDEV_RND_REG);
+ }
+ while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
+
+ last_ccount = ccount;
+ return result ^ getreg32(WDEV_RND_REG);
+}
+
+/****************************************************************************
+ * Name: esp32_rng_open
+ ****************************************************************************/
+
+static void esp32_rng_start(void)
+{
+ /* Nothing to do, bootloader already did it */
+}
+
+static void esp32_rng_stop(void)
+{
+ /* Nothing to do */
+}
+
+static int esp32_rng_initialize(void)
+{
+ static bool first_flag = true;
+
+ if (false == first_flag)
+ return OK;
+
+ first_flag = false;
+
+ _info("Initializing RNG\n");
+
+ memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
+
+ nxsem_init(&g_rngdev.rd_sem, 0, 1);
+ nxsem_set_protocol(&g_rngdev.rd_sem, SEM_PRIO_NONE);
+
+ esp32_rng_stop();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32_rng_open
+ ****************************************************************************/
+
+static int esp32_rng_open(FAR struct file *filep)
+{
+ /* O_NONBLOCK is not supported */
+
+ if (filep->f_oflags & O_NONBLOCK)
+ {
+ _err("ESP32 RNG didn't support O_NONBLOCK mode.\n");
+ return -EPERM;
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32_rng_read
+ ****************************************************************************/
+
+static ssize_t esp32_rng_read(FAR struct file *filep, FAR char *buffer,
+ size_t buflen)
+{
+ FAR struct rng_dev_s *priv = (struct rng_dev_s *)&g_rngdev;
+ ssize_t read_len;
+ uint8_t *rd_buf = (uint8_t *)buffer;
+
+ if (nxsem_wait(&priv->rd_sem) != OK)
+ {
+ return -EBUSY;
+ }
+
+ read_len = buflen;
+
+ /* start RNG and Wait until the buffer is filled */
+
+ esp32_rng_start();
+
+ /* Now, got data */
+
+ while (buflen > 0)
+ {
+ uint32_t word = esp_random();
+ uint32_t to_copy = MIN(sizeof(word), buflen);
+
+ memcpy(rd_buf, &word, to_copy);
+ rd_buf += to_copy;
+ buflen -= to_copy;
+ }
+
+ /* Release rd_sem for next read */
+
+ nxsem_post(&priv->rd_sem);
+
+ return read_len;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ * Initialize the RNG hardware and register the /dev/random driver.
+ * Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+ esp32_rng_initialize();
+ register_driver("/dev/random", FAR & g_rngops, 0444, NULL);
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ * Register /dev/urandom
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+#ifndef CONFIG_DEV_RANDOM
+ esp32_rng_initialize();
+#endif
+ register_driver("dev/urandom", FAR & g_rngops, 0444, NULL);
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_ESP32_RNG */
diff --git a/arch/xtensa/src/esp32/hardware/wdev_reg.h b/arch/xtensa/src/esp32/hardware/wdev_reg.h
new file mode 100644
index 0000000..c653953
--- /dev/null
+++ b/arch/xtensa/src/esp32/hardware/wdev_reg.h
@@ -0,0 +1,51 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32/hardware/wdev_reg.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_WDEV_REG_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_WDEV_REG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32_soc.h"
+
+/* Hardware random number generator register */
+
+#define WDEV_RND_REG 0x60035144
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_WDEV_REG_H */
diff --git a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld
index 6541caa..d9278d1 100644
--- a/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld
+++ b/boards/xtensa/esp32/esp32-core/scripts/esp32_rom.ld
@@ -186,6 +186,7 @@ PROVIDE ( ets_isr_mask = 0x400067fc );
PROVIDE ( ets_isr_unmask = 0x40006808 );
PROVIDE ( ets_post = 0x4000673c );
PROVIDE ( ets_printf = 0x40007d54 );
+PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
PROVIDE ( ets_readySet_ = 0x3ffe01f0 );
PROVIDE ( ets_run = 0x400066bc );
PROVIDE ( ets_secure_boot_check = 0x4005cb40 );