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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/08/05 05:58:00 UTC
[incubator-nuttx] branch master updated: arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 93584f8668 arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)
93584f8668 is described below
commit 93584f86680ed03bc429975857ac8b46467c877a
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Aug 3 10:16:09 2022 +0200
arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)
---
arch/arm/src/stm32f0l0g0/Kconfig | 27 ++++++++++++
arch/arm/src/stm32f0l0g0/stm32_spi.c | 79 ++++++++++++++++++++++++++++++++++++
arch/arm/src/stm32f0l0g0/stm32_spi.h | 12 ++++++
3 files changed, 118 insertions(+)
diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig
index f72e0810ee..f18276e02b 100644
--- a/arch/arm/src/stm32f0l0g0/Kconfig
+++ b/arch/arm/src/stm32f0l0g0/Kconfig
@@ -1090,6 +1090,10 @@ config STM32F0L0G0_HAVE_SPI2
bool
default n
+config STM32F0L0G0_HAVE_SPI3
+ bool
+ default n
+
config STM32F0L0G0_HAVE_SAIPLL
bool
default n
@@ -1272,6 +1276,13 @@ config STM32F0L0G0_SPI2
select SPI
select STM32F0L0G0_SPI
+config STM32F0L0G0_SPI3
+ bool "SPI3"
+ default n
+ depends on STM32F0L0G0_HAVE_SPI3
+ select SPI
+ select STM32F0L0G0_SPI
+
config STM32F0L0G0_SYSCFG
bool "SYSCFG"
default y
@@ -2708,6 +2719,14 @@ config STM32F0L0G0_SPI2_DMA
---help---
Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT.
+config STM32F0L0G0_SPI3_DMA
+ bool "SPI3 DMA"
+ default n
+ depends on STM32F0L0G0_SPI3 && !STM32F0L0G0_SPI_INTERRUPTS
+ select STM32F0L0G0_SPI_DMA
+ ---help---
+ Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT.
+
config STM32F0L0G0_SPI1_COMMTYPE
int "SPI1 Operation mode"
default 0
@@ -2724,6 +2743,14 @@ config STM32F0L0G0_SPI2_COMMTYPE
---help---
Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
+config STM32F0L0G0_SPI3_COMMTYPE
+ int "SPI3 Operation mode"
+ default 0
+ range 0 3
+ depends on STM32F0L0G0_SPI3
+ ---help---
+ Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3)
+
endmenu # SPI Configuration
menu "I2C Configuration"
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
index eab982771d..3dce4a00f5 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -134,6 +134,7 @@
#elif defined(CONFIG_STM32F0L0G0_STM32G0)
# define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
# define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
+# define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
#else
# error Unsupported family
#endif
@@ -386,6 +387,60 @@ static struct stm32_spidev_s g_spi2dev =
};
#endif
+#ifdef CONFIG_STM32F0L0G0_SPI3
+static const struct spi_ops_s g_spi3ops =
+{
+ .lock = spi_lock,
+ .select = stm32_spi3select,
+ .setfrequency = spi_setfrequency,
+ .setmode = spi_setmode,
+ .setbits = spi_setbits,
+#ifdef CONFIG_SPI_HWFEATURES
+ .hwfeatures = spi_hwfeatures,
+#endif
+ .status = stm32_spi3status,
+#ifdef CONFIG_SPI_CMDDATA
+ .cmddata = stm32_spi3cmddata,
+#endif
+ .send = spi_send,
+#ifdef CONFIG_SPI_EXCHANGE
+ .exchange = spi_exchange,
+#else
+ .sndblock = spi_sndblock,
+ .recvblock = spi_recvblock,
+#endif
+#ifdef CONFIG_SPI_TRIGGER
+ .trigger = spi_trigger,
+#endif
+#ifdef CONFIG_SPI_CALLBACK
+ .registercallback = stm32_spi3register, /* provided externally */
+#else
+ .registercallback = 0, /* not implemented */
+#endif
+};
+
+static struct stm32_spidev_s g_spi3dev =
+{
+ .spidev =
+ {
+ &g_spi3ops
+ },
+ .spibase = STM32_SPI3_BASE,
+ .spiclock = SPI1_PCLK_FREQUENCY,
+#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
+ .spiirq = STM32_IRQ_SPI3,
+#endif
+#ifdef CONFIG_STM32F0L0G0_SPI3_DMA
+ .rxch = DMACHAN_SPI3_RX,
+ .txch = DMACHAN_SPI3_TX,
+#endif
+#ifdef CONFIG_PM
+ .pm_cb.prepare = spi_pm_prepare,
+#endif
+ .config = CONFIG_STM32F0L0G0_SPI3_COMMTYPE,
+};
+#endif
+
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -2028,6 +2083,30 @@ struct spi_dev_s *stm32_spibus_initialize(int bus)
}
}
else
+#endif
+#ifdef CONFIG_STM32F0L0G0_SPI3
+ if (bus == 3)
+ {
+ /* Select SPI3 */
+
+ priv = &g_spi3dev;
+
+ /* Only configure if the bus is not already configured */
+
+ if (!priv->initialized)
+ {
+ /* Configure SPI3 pins: SCK, MISO, and MOSI */
+
+ stm32_configgpio(GPIO_SPI3_SCK);
+ stm32_configgpio(GPIO_SPI3_MOSI);
+
+ if (priv->config == FULL_DUPLEX || priv->config == SIMPLEX_RX)
+ {
+ stm32_configgpio(GPIO_SPI3_MISO);
+ }
+ }
+ }
+ else
#endif
{
spierr("ERROR: Unsupported SPI bus: %d\n", bus);
diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h
index 2ceb1c0348..bfbc594e3c 100644
--- a/arch/arm/src/stm32f0l0g0/stm32_spi.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.h
@@ -116,6 +116,13 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
+#ifdef CONFIG_STM32F0L0G0_SPI3
+void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected);
+uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid);
+int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
+#endif
+
/****************************************************************************
* Name: stm32_spi1/2/...register
*
@@ -146,6 +153,11 @@ int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
+
+#ifdef CONFIG_STM32F0L0G0_SPI3
+int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
+ void *arg);
+#endif
#endif
#undef EXTERN