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Posted to commits@nuttx.apache.org by pr...@apache.org on 2021/02/21 13:29:49 UTC
[incubator-nuttx] branch master updated (706740b -> 067da56)
This is an automated email from the ASF dual-hosted git repository.
protobits pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 706740b boards: raspberrypi-pico: Introduce rp2040_reset.c to support reboot
new 4a42998 esp32-c3: Add the GPIO driver.
new 1082279 esp32c3: Add GPIO IRQ support.
new 067da56 esp32c3: Some cosmetics and style fixes.
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/include/esp32c3/chip.h | 14 +
arch/risc-v/include/esp32c3/irq.h | 20 +-
arch/risc-v/src/esp32c3/Kconfig | 5 +
arch/risc-v/src/esp32c3/Make.defs | 2 +-
.../src/esp32c3/esp32c3_gpio.c} | 399 +-
.../src/esp32c3/esp32c3_gpio.h} | 152 +-
arch/risc-v/src/esp32c3/esp32c3_irq.c | 7 +
arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h | 5314 ++++++++++++++++++++
.../src/esp32c3/hardware/esp32c3_gpio_sigmap.h | 196 +
arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h | 310 ++
boards/risc-v/esp32c3/esp32c3-devkit/README.txt | 19 +
.../esp32c3-devkit/configs/{nsh => gpio}/defconfig | 5 +
.../risc-v/esp32c3/esp32c3-devkit/include/board.h | 5 +
boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile | 4 +
.../esp32c3/esp32c3-devkit/src/esp32c3-devkit.h | 8 +
.../esp32c3/esp32c3-devkit/src/esp32c3_bringup.c | 9 +
.../esp32c3/esp32c3-devkit/src/esp32c3_gpio.c} | 125 +-
17 files changed, 6197 insertions(+), 397 deletions(-)
copy arch/{xtensa/src/esp32/esp32_gpio.c => risc-v/src/esp32c3/esp32c3_gpio.c} (53%)
copy arch/{xtensa/src/esp32/esp32_gpio.h => risc-v/src/esp32c3/esp32c3_gpio.h} (63%)
create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h
create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
copy boards/risc-v/esp32c3/esp32c3-devkit/configs/{nsh => gpio}/defconfig (90%)
copy boards/{xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c => risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c} (69%)
[incubator-nuttx] 02/03: esp32c3: Add GPIO IRQ support.
Posted by pr...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
protobits pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 10822799fbc28d08806d76f39d264b2d0241b518
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Thu Feb 18 13:26:28 2021 +0100
esp32c3: Add GPIO IRQ support.
The GPIO example was also extended to include testing an interrupt pin.
Co-authored-by: Abdelatif Guettouche <ab...@espressif.com>
Co-authored-by: Alan Carvalho <al...@espressif.com>
---
arch/risc-v/include/esp32c3/irq.h | 20 ++-
arch/risc-v/src/esp32c3/Kconfig | 5 +
arch/risc-v/src/esp32c3/esp32c3_gpio.c | 181 ++++++++++++++++++++-
arch/risc-v/src/esp32c3/esp32c3_gpio.h | 54 ++++++
arch/risc-v/src/esp32c3/esp32c3_irq.c | 7 +
arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h | 41 ++++-
boards/risc-v/esp32c3/esp32c3-devkit/README.txt | 10 +-
.../esp32c3/esp32c3-devkit/configs/gpio/defconfig | 22 +--
.../risc-v/esp32c3/esp32c3-devkit/include/board.h | 1 +
.../esp32c3/esp32c3-devkit/src/esp32c3_gpio.c | 162 +++++++++++++++++-
10 files changed, 472 insertions(+), 31 deletions(-)
diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h
index 2326fc9..e200c73 100644
--- a/arch/risc-v/include/esp32c3/irq.h
+++ b/arch/risc-v/include/esp32c3/irq.h
@@ -132,6 +132,7 @@
/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */
#define ESP32C3_IRQ_ECALL_M 0
+#define RISCV_NIRQ_INTERRUPTS 1 /* Number of RISC-V dispatched interrupts. */
#define ESP32C3_IRQ_FIRSTPERIPH 1 /* First peripheral IRQ number */
/* Peripheral IRQs */
@@ -201,9 +202,24 @@
#define ESP32C3_NIRQ_PERIPH ESP32C3_NPERIPHERALS
-/* Total number of IRQs: Number of peripheral IRQs + 1 for ecall. */
+/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
+ * as a second level of decoding: The first level dispatches to the GPIO
+ * interrupt handler. The second to the decoded GPIO interrupt handler.
+ */
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+# define ESP32C3_NIRQ_GPIO 22
+# define ESP32C3_FIRST_GPIOIRQ (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH)
+# define ESP32C3_LAST_GPIOIRQ (ESP32C3_FIRST_GPIOIRQ + ESP32C3_NIRQ_GPIO - 1)
+# define ESP32C3_PIN2IRQ(p) ((p) + ESP32C3_FIRST_GPIOIRQ)
+# define ESP32C3_IRQ2PIN(i) ((i) - ESP32C3_FIRST_GPIOIRQ)
+#else
+# define ESP32C3_NIRQ_GPIO 0
+#endif
+
+/* Total number of IRQs: ecall + Number of peripheral IRQs + GPIOs IRQs. */
-#define NR_IRQS (ESP32C3_NIRQ_PERIPH + 1)
+#define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH + ESP32C3_NIRQ_GPIO)
/****************************************************************************
* Inline functions
diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig
index d5a15a9..950fc37 100644
--- a/arch/risc-v/src/esp32c3/Kconfig
+++ b/arch/risc-v/src/esp32c3/Kconfig
@@ -104,6 +104,11 @@ config ESP32C3_CPU_FREQ_MHZ
menu "ESP32-C3 Peripheral Support"
+config ESP32C3_GPIO_IRQ
+ bool "GPIO pin interrupts"
+ ---help---
+ Enable support for interrupting GPIO pins
+
config ESP32C3_UART0
bool "UART0"
default y
diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.c b/arch/risc-v/src/esp32c3/esp32c3_gpio.c
index 6b15822..36e923d 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_gpio.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_gpio.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc/src/esp32c3/esp32c3_gpio.c
+ * arch/risc-v/src/esp32c3/esp32c3_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -35,12 +35,76 @@
#include <arch/esp32c3/chip.h>
#include "riscv_arch.h"
+#include "esp32c3_irq.h"
#include "hardware/esp32c3_iomux.h"
#include "hardware/esp32c3_gpio.h"
#include "esp32c3_gpio.h"
/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+static int g_gpio_cpuint;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_dispatch
+ *
+ * Description:
+ * Second level dispatch for GPIO interrupt handling.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs)
+{
+ int i;
+ int ndx = 0;
+
+ /* Check set bits in the status register */
+
+ while ((i = __builtin_ffs(status)))
+ {
+ ndx += i;
+ irq_dispatch(irq + ndx - 1, regs);
+ status >>= i;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: gpio_interrupt
+ *
+ * Description:
+ * GPIO interrupt handler.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+static int gpio_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+ uint32_t status;
+
+ /* Read and clear the lower GPIO interrupt status */
+
+ status = getreg32(GPIO_STATUS_REG);
+ putreg32(status, GPIO_STATUS_W1TC_REG);
+
+ /* Dispatch pending interrupts in the lower GPIO status register */
+
+ gpio_dispatch(ESP32C3_FIRST_GPIOIRQ, status, (uint32_t *)context);
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
* Public Functions
****************************************************************************/
@@ -230,3 +294,118 @@ void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
putreg32(regval, regaddr);
}
+/****************************************************************************
+ * Name: esp32c3_gpioirqinitialize
+ *
+ * Description:
+ * Initialize logic to support a second level of interrupt decoding for
+ * GPIO pins.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqinitialize(void)
+{
+ int ret;
+
+ /* Allocate a level-sensitive, priority 1 CPU interrupt */
+
+ g_gpio_cpuint = esp32c3_request_irq(ESP32C3_PERIPH_GPIO, 1,
+ ESP32C3_INT_LEVEL);
+ DEBUGASSERT(g_gpio_cpuint > 0);
+
+ up_disable_irq(g_gpio_cpuint);
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(ESP32C3_IRQ_GPIO, gpio_interrupt, NULL);
+ if (ret == OK)
+ {
+ up_enable_irq(g_gpio_cpuint);
+ }
+ else
+ {
+ gpioerr("ERROR: GPIO interrupt not attached!\n");
+ }
+
+ gpioinfo("GPIO interrupt (%d) attached.\n", g_gpio_cpuint);
+}
+#endif
+
+/****************************************************************************
+ * Name: esp32c3_gpioirqenable
+ *
+ * Description:
+ * Enable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ int pin;
+
+ DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ);
+
+ /* Convert the IRQ number to a pin number */
+
+ pin = ESP32C3_IRQ2PIN(irq);
+
+ /* Disable the GPIO interrupt during the configuration. */
+
+ up_disable_irq(g_gpio_cpuint);
+
+ /* Get the address of the GPIO PIN register for this pin */
+
+ regaddr = GPIO_REG(pin);
+ regval = getreg32(regaddr);
+ regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
+
+ /* Set the pin ENA field. */
+
+ regval |= (1 << GPIO_PIN0_INT_ENA_S);
+ regval |= (intrtype << GPIO_PIN_INT_TYPE_S);
+ putreg32(regval, regaddr);
+
+ /* Configuration done. Re-enable the GPIO interrupt. */
+
+ up_enable_irq(g_gpio_cpuint);
+}
+#endif
+
+/****************************************************************************
+ * Name: esp32c3_gpioirqdisable
+ *
+ * Description:
+ * Disable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqdisable(int irq)
+{
+ uintptr_t regaddr;
+ uint32_t regval;
+ int pin;
+
+ DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ);
+
+ /* Convert the IRQ number to a pin number */
+
+ pin = ESP32C3_IRQ2PIN(irq);
+
+ /* Get the address of the GPIO PIN register for this pin */
+
+ up_disable_irq(g_gpio_cpuint);
+
+ regaddr = GPIO_REG(pin);
+ regval = getreg32(regaddr);
+ regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
+ putreg32(regval, regaddr);
+
+ up_enable_irq(g_gpio_cpuint);
+}
+#endif
+
diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
index 0a4423a..a7a2ced 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_gpio.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
@@ -76,6 +76,15 @@
# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
+/* Interrupt type used with esp32c3_gpioirqenable() */
+
+#define DISABLED 0x00
+#define RISING 0x01
+#define FALLING 0x02
+#define CHANGE 0x03
+#define ONLOW 0x04
+#define ONHIGH 0x05
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -85,6 +94,7 @@
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
+typedef uint8_t gpio_intrtype_t;
/****************************************************************************
* Public Data
@@ -159,6 +169,50 @@ void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv);
+/****************************************************************************
+ * Name: esp32c3_gpioirqinitialize
+ *
+ * Description:
+ * Initialize logic to support a second level of interrupt decoding for
+ * GPIO pins.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqinitialize(void);
+#else
+# define esp32c3_gpioirqinitialize()
+#endif
+
+
+/****************************************************************************
+ * Name: esp32c3_gpioirqenable
+ *
+ * Description:
+ * Enable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype);
+#else
+# define esp32c3_gpioirqenable(irq,intrtype)
+#endif
+
+/****************************************************************************
+ * Name: esp32c3_gpioirqdisable
+ *
+ * Description:
+ * Disable the interrupt for specified GPIO IRQ
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+void esp32c3_gpioirqdisable(int irq);
+#else
+# define esp32c3_gpioirqdisable(irq)
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c
index 2ebc5e1..f57ed77 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_irq.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c
@@ -40,6 +40,7 @@
#include "esp32c3.h"
#include "esp32c3_attr.h"
+#include "esp32c3_gpio.h"
#include "esp32c3_irq.h"
@@ -96,6 +97,12 @@ void up_irqinitialize(void)
irq_attach(ESP32C3_IRQ_ECALL_M, up_swint, NULL);
+#ifdef CONFIG_ESP32C3_GPIO_IRQ
+ /* Initialize GPIO interrupt support */
+
+ esp32c3_gpioirqinitialize();
+#endif
+
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
index 662282c..e4391fc 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
@@ -33,6 +33,26 @@
#define GPIO_REG(io_num) (GPIO_PIN0_REG + ((io_num) * 0x4))
+#define GPIO_PIN_INT_ENA 0x0000001F
+#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S))
+#define GPIO_PIN_INT_ENA_V 0x0000001F
+#define GPIO_PIN_INT_ENA_S 13
+
+#define GPIO_PIN_CONFIG 0x00000003
+#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S))
+#define GPIO_PIN_CONFIG_V 0x00000003
+#define GPIO_PIN_CONFIG_S 11
+
+#define GPIO_PIN_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN_WAKEUP_ENABLE_S 10
+
+#define GPIO_PIN_INT_TYPE 0x00000007
+#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S))
+#define GPIO_PIN_INT_TYPE_V 0x00000007
+#define GPIO_PIN_INT_TYPE_S 7
+
#define GPIO_PIN_CONFIG_MSB 12
#define GPIO_PIN_CONFIG_LSB 11
#define GPIO_PIN_CONFIG_MASK 0x00001800
@@ -53,13 +73,20 @@
#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
-#define GPIO_PAD_DRIVER_ENABLE 1
-#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
-#define GPIO_PIN_PAD_DRIVER_MSB 2
-#define GPIO_PIN_PAD_DRIVER_LSB 2
-#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
-#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+#define GPIO_PIN_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN_SYNC1_BYPASS_S 3
+
+#define GPIO_PIN_PAD_DRIVER (BIT(2))
+#define GPIO_PIN_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN_PAD_DRIVER_V 0x1
+#define GPIO_PIN_PAD_DRIVER_S 2
+
+#define GPIO_PIN_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN_SYNC2_BYPASS_S 0
#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
index 23dc3cb..b847f7a 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
@@ -80,7 +80,9 @@ Configurations
gpio
____
- This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs.
+ This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and
+ GPIO9 as an interrupt pin.
+
At the nsh, we can turn the outputs on and off with the following:
nsh> gpio -o 1 /dev/gpout0
nsh> gpio -o 1 /dev/gpout1
@@ -88,6 +90,12 @@ Configurations
nsh> gpio -o 0 /dev/gpout0
nsh> gpio -o 0 /dev/gpout1
+ We can use the interrupt pin to send a signal when the interrupt fires:
+ nsh> gpio -w 14 /dev/gpint2
+
+ The pin is configured as a rising edge interrupt, so after issuing the
+ above command, connect it to 3.3V.
+
Building and flashing
=====================
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig
index a28b2fa..feca198 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig
@@ -17,18 +17,14 @@ CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
CONFIG_ARCH_INTERRUPTSTACK=1536
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BINFMT_DISABLE=y
CONFIG_BOARD_LOOPSPERMSEC=15000
CONFIG_BUILTIN=y
CONFIG_DEV_GPIO=y
CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_MQUEUE=y
+CONFIG_ESP32C3_GPIO_IRQ=y
CONFIG_EXAMPLES_GPIO=y
-CONFIG_EXAMPLES_HELLO=y
-CONFIG_EXAMPLES_HELLO_STACKSIZE=1024
CONFIG_FS_PROCFS=y
CONFIG_IDLETHREAD_STACKSIZE=2048
-CONFIG_INPUT=y
CONFIG_INTELHEX_BINARY=y
CONFIG_LIBC_PERROR_STDOUT=y
CONFIG_LIBC_STRERROR=y
@@ -36,30 +32,18 @@ CONFIG_MAX_TASKS=8
CONFIG_NFILE_DESCRIPTORS=6
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DISABLE_CD=y
-CONFIG_NSH_DISABLE_CP=y
-CONFIG_NSH_DISABLE_IFUPDOWN=y
-CONFIG_NSH_DISABLE_MKDIR=y
-CONFIG_NSH_DISABLE_RM=y
-CONFIG_NSH_DISABLE_RMDIR=y
-CONFIG_NSH_DISABLE_UMOUNT=y
-CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
CONFIG_NSH_STRERROR=y
CONFIG_PREALLOC_TIMERS=0
-CONFIG_PTHREAD_STACK_DEFAULT=1536
-CONFIG_RAM_SIZE=16384
-CONFIG_RAM_START=0x80000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_START_DAY=29
CONFIG_START_MONTH=11
CONFIG_START_YEAR=2019
-CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYSTEM_NSH=y
CONFIG_TASK_NAME_SIZE=12
CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
-CONFIG_TESTING_GETPRIME=y
CONFIG_UART0_SERIAL_CONSOLE=y
-CONFIG_USERMAIN_STACKSIZE=1536
CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
index 1d0432f..07d6e4c 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
@@ -32,6 +32,7 @@
/* GPIO pins used by the GPIO Subsystem */
#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */
+#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */
#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
index 3844e9b..c4095bb 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
@@ -30,6 +30,9 @@
#include <assert.h>
#include <debug.h>
+#include <nuttx/irq.h>
+#include <arch/irq.h>
+
#include <nuttx/ioexpander/gpio.h>
#include <arch/board/board.h>
@@ -38,6 +41,8 @@
#include "esp32c3_gpio.h"
#include "hardware/esp32c3_gpio_sigmap.h"
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -47,7 +52,15 @@
#define GPIO_OUT1 1
#define GPIO_OUT2 2
-#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+#if !defined(CONFIG_ESP32C3_GPIO_IRQ) && BOARD_NGPIOINT > 0
+# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled"
+#endif
+
+/* Interrupt pins. GPIO9 is used as an example, any other inputs could be
+ * used.
+ */
+
+#define GPIO_IRQPIN 9
/****************************************************************************
* Private Types
@@ -59,6 +72,12 @@ struct esp32c3gpio_dev_s
uint8_t id;
};
+struct esp32c3gpint_dev_s
+{
+ struct esp32c3gpio_dev_s esp32c3gpio;
+ pin_interrupt_t callback;
+};
+
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@@ -68,6 +87,13 @@ static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value);
static int gpout_write(FAR struct gpio_dev_s *dev, bool value);
#endif
+#if BOARD_NGPIOINT > 0
+static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value);
+static int gpint_attach(FAR struct gpio_dev_s *dev,
+ pin_interrupt_t callback);
+static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable);
+#endif
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -91,6 +117,25 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
static struct esp32c3gpio_dev_s g_gpout[BOARD_NGPIOOUT];
#endif
+#if BOARD_NGPIOINT > 0
+static const struct gpio_operations_s gpint_ops =
+{
+ .go_read = gpint_read,
+ .go_write = NULL,
+ .go_attach = gpint_attach,
+ .go_enable = gpint_enable,
+};
+
+/* This array maps the GPIO pins used as INTERRUPT INPUTS */
+
+static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] =
+{
+ GPIO_IRQPIN,
+};
+
+static struct esp32c3gpint_dev_s g_gpint[BOARD_NGPIOINT];
+#endif
+
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -132,6 +177,103 @@ static int gpout_write(FAR struct gpio_dev_s *dev, bool value)
#endif
/****************************************************************************
+ * Name: esp32c3gpio_interrupt
+ ****************************************************************************/
+
+#if BOARD_NGPIOINT > 0
+static int esp32c3gpio_interrupt(int irq, void *context, void *arg)
+{
+ FAR struct esp32c3gpint_dev_s *esp32c3gpint =
+ (FAR struct esp32c3gpint_dev_s *)arg;
+
+ DEBUGASSERT(esp32c3gpint != NULL && esp32c3gpint->callback != NULL);
+ gpioinfo("Interrupt! callback=%p\n", esp32c3gpint->callback);
+
+ esp32c3gpint->callback(&esp32c3gpint->esp32c3gpio.gpio,
+ esp32c3gpint->esp32c3gpio.id);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: gpint_read
+ ****************************************************************************/
+
+static int gpint_read(FAR struct gpio_dev_s *dev, FAR bool *value)
+{
+ FAR struct esp32c3gpint_dev_s *esp32c3gpint =
+ (FAR struct esp32c3gpint_dev_s *)dev;
+
+ DEBUGASSERT(esp32c3gpint != NULL && value != NULL);
+ DEBUGASSERT(esp32c3gpint->esp32c3gpio.id < BOARD_NGPIOINT);
+ gpioinfo("Reading int pin...\n");
+
+ *value = esp32c3_gpioread(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: gpint_attach
+ ****************************************************************************/
+
+static int gpint_attach(FAR struct gpio_dev_s *dev,
+ pin_interrupt_t callback)
+{
+ FAR struct esp32c3gpint_dev_s *esp32c3gpint =
+ (FAR struct esp32c3gpint_dev_s *)dev;
+ int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]);
+ int ret;
+
+ gpioinfo("Attaching the callback\n");
+
+ /* Make sure the interrupt is disabled */
+
+ esp32c3_gpioirqdisable(irq);
+ ret = irq_attach(irq,
+ esp32c3gpio_interrupt,
+ &g_gpint[esp32c3gpint->esp32c3gpio.id]);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret);
+ return ret;
+ }
+
+ gpioinfo("Attach %p\n", callback);
+ esp32c3gpint->callback = callback;
+ return OK;
+}
+
+/****************************************************************************
+ * Name: gpint_enable
+ ****************************************************************************/
+
+static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable)
+{
+ FAR struct esp32c3gpint_dev_s *esp32c3gpint =
+ (FAR struct esp32c3gpint_dev_s *)dev;
+ int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]);
+
+ if (enable)
+ {
+ if (esp32c3gpint->callback != NULL)
+ {
+ gpioinfo("Enabling the interrupt\n");
+
+ /* Configure the interrupt for rising edge */
+
+ esp32c3_gpioirqenable(irq, RISING);
+ }
+ }
+ else
+ {
+ gpioinfo("Disable the interrupt\n");
+ esp32c3_gpioirqdisable(irq);
+ }
+
+ return OK;
+}
+#endif
+
+/****************************************************************************
* Public Functions
****************************************************************************/
@@ -164,6 +306,24 @@ int esp32c3_gpio_init(void)
}
#endif
+#if BOARD_NGPIOINT > 0
+ for (i = 0; i < BOARD_NGPIOINT; i++)
+ {
+ /* Setup and register the GPIO pin */
+
+ g_gpint[i].esp32c3gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN;
+ g_gpint[i].esp32c3gpio.gpio.gp_ops = &gpint_ops;
+ g_gpint[i].esp32c3gpio.id = i;
+ gpio_pin_register(&g_gpint[i].esp32c3gpio.gpio, pincount);
+
+ /* Configure the pins that will be used as interrupt input */
+
+ esp32c3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN);
+
+ pincount++;
+ }
+#endif
+
return OK;
}
#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */
[incubator-nuttx] 03/03: esp32c3: Some cosmetics and style fixes.
Posted by pr...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
protobits pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 067da56d0c424aec2f84d2335d688bb74ab7116d
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Thu Feb 18 13:49:43 2021 +0100
esp32c3: Some cosmetics and style fixes.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/esp32c3/esp32c3_gpio.h | 1 -
arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h | 4 +-
arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h | 346 ++++++++++-----------
.../esp32c3/esp32c3-devkit/src/esp32c3-devkit.h | 1 -
.../esp32c3/esp32c3-devkit/src/esp32c3_gpio.c | 2 +-
5 files changed, 176 insertions(+), 178 deletions(-)
diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
index a7a2ced..91632ec 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_gpio.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
@@ -184,7 +184,6 @@ void esp32c3_gpioirqinitialize(void);
# define esp32c3_gpioirqinitialize()
#endif
-
/****************************************************************************
* Name: esp32c3_gpioirqenable
*
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
index e4391fc..5a7f705 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
@@ -33,9 +33,9 @@
#define GPIO_REG(io_num) (GPIO_PIN0_REG + ((io_num) * 0x4))
-#define GPIO_PIN_INT_ENA 0x0000001F
+#define GPIO_PIN_INT_ENA 0x0000001f
#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S))
-#define GPIO_PIN_INT_ENA_V 0x0000001F
+#define GPIO_PIN_INT_ENA_V 0x0000001f
#define GPIO_PIN_INT_ENA_S 13
#define GPIO_PIN_CONFIG 0x00000003
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
index 9d057b7..8682afb 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
@@ -35,82 +35,82 @@
/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as
* FUNC_pinname_function below)
*/
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
@@ -123,14 +123,14 @@
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
@@ -155,8 +155,8 @@
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
-#define FUNC_GPIO_GPIO 1
-#define PIN_FUNC_GPIO 1
+#define FUNC_GPIO_GPIO 1
+#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
@@ -183,127 +183,127 @@
#define MAX_PAD_GPIO_NUM 22
#define MAX_GPIO_NUM 22
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL (REG_IO_MUX_BASE + 0x00)
-#define PAD_POWER_SEL BIT(15)
-#define PAD_POWER_SEL_V 0x1
-#define PAD_POWER_SEL_M BIT(15)
-#define PAD_POWER_SEL_S 15
-
-#define PAD_POWER_SWITCH_DELAY 0x7
-#define PAD_POWER_SWITCH_DELAY_V 0x7
-#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S 12
-
-#define CLK_OUT3 0xf
-#define CLK_OUT3_V CLK_OUT3
-#define CLK_OUT3_S 8
-#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2 0xf
-#define CLK_OUT2_V CLK_OUT2
-#define CLK_OUT2_S 4
-#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1 0xf
-#define CLK_OUT1_V CLK_OUT1
-#define CLK_OUT1_S 0
-#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
-
-#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x04)
-#define FUNC_XTAL_32K_P_GPIO0 1
-#define FUNC_XTAL_32K_P_GPIO0_0 0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x08)
-#define FUNC_XTAL_32K_N_GPIO1 1
-#define FUNC_XTAL_32K_N_GPIO1_0 0
-
-#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0c)
-#define FUNC_GPIO2_FSPIQ 2
-#define FUNC_GPIO2_GPIO2 1
-#define FUNC_GPIO2_GPIO2_0 0
-
-#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
-#define FUNC_GPIO3_GPIO3 1
-#define FUNC_GPIO3_GPIO3_0 0
-
-#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTMS_FSPIHD 2
-#define FUNC_MTMS_GPIO4 1
-#define FUNC_MTMS_MTMS 0
-
-#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDI_FSPIWP 2
-#define FUNC_MTDI_GPIO5 1
-#define FUNC_MTDI_MTDI 0
-
-#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1c)
-#define FUNC_MTCK_FSPICLK 2
-#define FUNC_MTCK_GPIO6 1
-#define FUNC_MTCK_MTCK 0
-
-#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
-#define FUNC_MTDO_FSPID 2
-#define FUNC_MTDO_GPIO7 1
-#define FUNC_MTDO_MTDO 0
-
-#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_GPIO8 1
-#define FUNC_GPIO8_GPIO8_0 0
-
-#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_GPIO9 1
-#define FUNC_GPIO9_GPIO9_0 0
-
-#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2c)
-#define FUNC_GPIO10_FSPICS0 2
-#define FUNC_GPIO10_GPIO10 1
-#define FUNC_GPIO10_GPIO10_0 0
-
-#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x30)
-#define FUNC_VDD_SPI_GPIO11 1
-#define FUNC_VDD_SPI_GPIO11_0 0
-
-#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x34)
-#define FUNC_SPIHD_GPIO12 1
-#define FUNC_SPIHD_SPIHD 0
-
-#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x38)
-#define FUNC_SPIWP_GPIO13 1
-#define FUNC_SPIWP_SPIWP 0
-
-#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x3c)
-#define FUNC_SPICS0_GPIO14 1
-#define FUNC_SPICS0_SPICS0 0
-
-#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x40)
-#define FUNC_SPICLK_GPIO15 1
-#define FUNC_SPICLK_SPICLK 0
-
-#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x44)
-#define FUNC_SPID_GPIO16 1
-#define FUNC_SPID_SPID 0
-
-#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x48)
-#define FUNC_SPIQ_GPIO17 1
-#define FUNC_SPIQ_SPIQ 0
-
-#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE + 0x4c)
-#define FUNC_GPIO18_GPIO18 1
-#define FUNC_GPIO18_GPIO18_0 0
-
-#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE + 0x50)
-#define FUNC_GPIO19_GPIO19 1
-#define FUNC_GPIO19_GPIO19_0 0
-
-#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x54)
-#define FUNC_U0RXD_GPIO20 1
-#define FUNC_U0RXD_U0RXD 0
-
-#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x58)
-#define FUNC_U0TXD_GPIO21 1
-#define FUNC_U0TXD_U0TXD 0
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL (REG_IO_MUX_BASE + 0x00)
+#define PAD_POWER_SEL BIT(15)
+#define PAD_POWER_SEL_V 0x1
+#define PAD_POWER_SEL_M BIT(15)
+#define PAD_POWER_SEL_S 15
+
+#define PAD_POWER_SWITCH_DELAY 0x7
+#define PAD_POWER_SWITCH_DELAY_V 0x7
+#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S 12
+
+#define CLK_OUT3 0xf
+#define CLK_OUT3_V CLK_OUT3
+#define CLK_OUT3_S 8
+#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2 0xf
+#define CLK_OUT2_V CLK_OUT2
+#define CLK_OUT2_S 4
+#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1 0xf
+#define CLK_OUT1_V CLK_OUT1
+#define CLK_OUT1_S 0
+#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x04)
+#define FUNC_XTAL_32K_P_GPIO0 1
+#define FUNC_XTAL_32K_P_GPIO0_0 0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x08)
+#define FUNC_XTAL_32K_N_GPIO1 1
+#define FUNC_XTAL_32K_N_GPIO1_0 0
+
+#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0c)
+#define FUNC_GPIO2_FSPIQ 2
+#define FUNC_GPIO2_GPIO2 1
+#define FUNC_GPIO2_GPIO2_0 0
+
+#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3 1
+#define FUNC_GPIO3_GPIO3_0 0
+
+#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTMS_FSPIHD 2
+#define FUNC_MTMS_GPIO4 1
+#define FUNC_MTMS_MTMS 0
+
+#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPIWP 2
+#define FUNC_MTDI_GPIO5 1
+#define FUNC_MTDI_MTDI 0
+
+#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1c)
+#define FUNC_MTCK_FSPICLK 2
+#define FUNC_MTCK_GPIO6 1
+#define FUNC_MTCK_MTCK 0
+
+#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
+#define FUNC_MTDO_FSPID 2
+#define FUNC_MTDO_GPIO7 1
+#define FUNC_MTDO_MTDO 0
+
+#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8 1
+#define FUNC_GPIO8_GPIO8_0 0
+
+#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9 1
+#define FUNC_GPIO9_GPIO9_0 0
+
+#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2c)
+#define FUNC_GPIO10_FSPICS0 2
+#define FUNC_GPIO10_GPIO10 1
+#define FUNC_GPIO10_GPIO10_0 0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x30)
+#define FUNC_VDD_SPI_GPIO11 1
+#define FUNC_VDD_SPI_GPIO11_0 0
+
+#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x34)
+#define FUNC_SPIHD_GPIO12 1
+#define FUNC_SPIHD_SPIHD 0
+
+#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x38)
+#define FUNC_SPIWP_GPIO13 1
+#define FUNC_SPIWP_SPIWP 0
+
+#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x3c)
+#define FUNC_SPICS0_GPIO14 1
+#define FUNC_SPICS0_SPICS0 0
+
+#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICLK_GPIO15 1
+#define FUNC_SPICLK_SPICLK 0
+
+#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPID_GPIO16 1
+#define FUNC_SPID_SPID 0
+
+#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIQ_GPIO17 1
+#define FUNC_SPIQ_SPIQ 0
+
+#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE + 0x4c)
+#define FUNC_GPIO18_GPIO18 1
+#define FUNC_GPIO18_GPIO18_0 0
+
+#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE + 0x50)
+#define FUNC_GPIO19_GPIO19 1
+#define FUNC_GPIO19_GPIO19_0 0
+
+#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x54)
+#define FUNC_U0RXD_GPIO20 1
+#define FUNC_U0RXD_U0RXD 0
+
+#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x58)
+#define FUNC_U0TXD_GPIO21 1
+#define FUNC_U0TXD_U0TXD 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
-#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE 0xffffffff
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x2006050
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
index 088ff6a..e35f38d 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
@@ -71,6 +71,5 @@ int esp32c3_bringup(void);
int esp32c3_gpio_init(void);
#endif
-
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_SRC_ESP32C3_DEVKIT_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
index c4095bb..e4e5a7b 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
@@ -111,7 +111,7 @@ static const struct gpio_operations_s gpout_ops =
static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
{
- GPIO_OUT1, GPIO_OUT2
+ GPIO_OUT1, GPIO_OUT2
};
static struct esp32c3gpio_dev_s g_gpout[BOARD_NGPIOOUT];
[incubator-nuttx] 01/03: esp32-c3: Add the GPIO driver.
Posted by pr...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
protobits pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4a42998f36f19aae3e3cf3858e19bda1fd9e1cce
Author: Alan Carvalho <al...@espressif.com>
AuthorDate: Wed Feb 17 22:44:27 2021 +0100
esp32-c3: Add the GPIO driver.
This commits adds support for the ESP32-C3 IO Mux and GPIO Matrix. It
also includes necessary board logic to run the GPIO example with 2
outputs.
Co-authored-by: Alan Carvalho <al...@espressif.com>
Co-authored-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/include/esp32c3/chip.h | 14 +
arch/risc-v/src/esp32c3/Make.defs | 2 +-
arch/risc-v/src/esp32c3/esp32c3_gpio.c | 232 +
arch/risc-v/src/esp32c3/esp32c3_gpio.h | 168 +
arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h | 5287 ++++++++++++++++++++
.../src/esp32c3/hardware/esp32c3_gpio_sigmap.h | 196 +
arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h | 310 ++
boards/risc-v/esp32c3/esp32c3-devkit/README.txt | 11 +
.../esp32c3/esp32c3-devkit/configs/gpio/defconfig | 65 +
.../risc-v/esp32c3/esp32c3-devkit/include/board.h | 4 +
boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile | 4 +
.../esp32c3/esp32c3-devkit/src/esp32c3-devkit.h | 9 +
.../esp32c3/esp32c3-devkit/src/esp32c3_bringup.c | 9 +
.../esp32c3/esp32c3-devkit/src/esp32c3_gpio.c | 169 +
14 files changed, 6479 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/include/esp32c3/chip.h b/arch/risc-v/include/esp32c3/chip.h
index 1710e6c..7c2bcf2 100644
--- a/arch/risc-v/include/esp32c3/chip.h
+++ b/arch/risc-v/include/esp32c3/chip.h
@@ -21,4 +21,18 @@
#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H
#define __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Characterize each supported ESP32 part */
+
+#define ESP32C3_NGPIOS 22 /* GPIO0-21 */
+
#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H */
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index 4280466..09abfcf 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -51,5 +51,5 @@ endif
CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_idle.c
CHIP_CSRCS += esp32c3_irq.c esp32c3_timerisr.c
-CHIP_CSRCS += esp32c3_clockconfig.c
+CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c
CHIP_CSRCS += esp32c3_serial.c esp32c3_lowputc.c
diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.c b/arch/risc-v/src/esp32c3/esp32c3_gpio.c
new file mode 100644
index 0000000..6b15822
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_gpio.c
@@ -0,0 +1,232 @@
+/****************************************************************************
+ * arch/risc/src/esp32c3/esp32c3_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <arch/irq.h>
+#include <arch/esp32c3/chip.h>
+
+#include "riscv_arch.h"
+#include "hardware/esp32c3_iomux.h"
+#include "hardware/esp32c3_gpio.h"
+
+#include "esp32c3_gpio.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ ****************************************************************************/
+
+int esp32c3_configgpio(int pin, gpio_pinattr_t attr)
+{
+ uintptr_t regaddr;
+ uint32_t func;
+ uint32_t cntrl;
+ uint32_t pin2func;
+
+ DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS);
+
+ func = 0;
+ cntrl = 0;
+
+ /* Handle input pins */
+
+ if ((attr & INPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
+
+ if ((attr & PULLUP) != 0)
+ {
+ func |= FUN_PU;
+ }
+ else if (attr & PULLDOWN)
+ {
+ func |= FUN_PD;
+ }
+ }
+
+ /* Handle output pins */
+
+ else if ((attr & OUTPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
+ }
+
+ /* Add drivers */
+
+ func |= (uint32_t)(2ul << FUN_DRV_S);
+
+ /* Input enable... Required for output as well? */
+
+ func |= FUN_IE;
+
+ /* Select the pad's function. If no function was given, consider it a
+ * normal input or output (i.e. function3).
+ */
+
+ if ((attr & FUNCTION_MASK) != 0)
+ {
+ func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
+ }
+ else
+ {
+ func |= (uint32_t)((2 >> FUNCTION_SHIFT) << MCU_SEL_S);
+ }
+
+ if ((attr & OPEN_DRAIN) != 0)
+ {
+ cntrl = (1 << GPIO_PIN_PAD_DRIVER_S);
+ }
+
+ /* Set the pin function to its register */
+
+ pin2func = (pin + 1) * 4;
+ regaddr = REG_IO_MUX_BASE + pin2func;
+ putreg32(func, regaddr);
+
+ regaddr = GPIO_REG(pin);
+ putreg32(cntrl, regaddr);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c3_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void esp32c3_gpiowrite(int pin, bool value)
+{
+ DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS);
+
+ if (value)
+ {
+ putreg32(1ul << pin, GPIO_OUT_W1TS_REG);
+ }
+ else
+ {
+ putreg32(1ul << pin, GPIO_OUT_W1TC_REG);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32c3_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool esp32c3_gpioread(int pin)
+{
+ uint32_t regval;
+
+ DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS);
+
+ regval = getreg32(GPIO_IN_REG);
+ return ((regval >> pin) & 1) != 0;
+}
+
+/****************************************************************************
+ * Name: esp32c3_gpio_matrix_in
+ *
+ * Description:
+ * Set gpio input to a signal
+ * NOTE: one gpio can input to several signals
+ * If gpio == 0x30, cancel input to the signal, input 0 to signal
+ * If gpio == 0x38, cancel input to the signal, input 1 to signal,
+ * for I2C pad
+ *
+ ****************************************************************************/
+
+void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
+ uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
+
+ if (inv)
+ {
+ regval |= GPIO_FUNC0_IN_INV_SEL;
+ }
+
+ if (gpio != 0x34)
+ {
+ regval |= GPIO_SIG0_IN_SEL;
+ }
+
+ putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: esp32c3_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to gpio
+ * NOTE: one signal can output to several gpios
+ * If signal_idx == 0x100, cancel output put to the gpio
+ *
+ ****************************************************************************/
+
+void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+ bool out_inv, bool oen_inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
+ uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
+
+ if (gpio >= ESP32C3_NGPIOS)
+ {
+ return;
+ }
+
+ putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG);
+
+ if (out_inv)
+ {
+ regval |= GPIO_FUNC0_OUT_INV_SEL;
+ }
+
+ if (oen_inv)
+ {
+ regval |= GPIO_FUNC0_OEN_INV_SEL;
+ }
+
+ putreg32(regval, regaddr);
+}
+
diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
new file mode 100644
index 0000000..0a4423a
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_gpio.h
@@ -0,0 +1,168 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32/esp32c3_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Bit-encoded input to esp32c3_configgpio() ********************************/
+
+/* Encoded pin attributes used with esp32c3_configgpio()
+ *
+ * 8 7 6 5 4 3 2 1 0
+ * -- -- -- -- -- -- -- -- --
+ * FN FN FN OD PD PU F O I
+ */
+
+#define PINMODE_SHIFT 0
+#define PINMODE_MASK (7 << PINMODE_SHIFT)
+# define INPUT (1 << 0)
+# define OUTPUT (1 << 1)
+# define FUNCTION (1 << 2)
+
+#define PULLUP (1 << 3)
+#define PULLDOWN (1 << 4)
+#define OPEN_DRAIN (1 << 5)
+#define FUNCTION_SHIFT 6
+#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
+# define FUNCTION_0 (1 << FUNCTION_SHIFT)
+# define FUNCTION_1 (2 << FUNCTION_SHIFT)
+# define FUNCTION_2 (3 << FUNCTION_SHIFT)
+# define FUNCTION_3 (4 << FUNCTION_SHIFT)
+# define FUNCTION_4 (5 << FUNCTION_SHIFT)
+
+#define INPUT_PULLUP (INPUT | PULLUP)
+#define INPUT_PULLDOWN (INPUT | PULLDOWN)
+#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
+#define INPUT_FUNCTION (INPUT | FUNCTION)
+# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0)
+# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
+# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
+# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
+# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
+#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
+# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0)
+# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
+# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
+# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
+# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Must be big enough to hold the above encodings */
+
+typedef uint16_t gpio_pinattr_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ ****************************************************************************/
+
+int esp32c3_configgpio(int pin, gpio_pinattr_t attr);
+
+/****************************************************************************
+ * Name: esp32c3_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
+ ****************************************************************************/
+
+void esp32c3_gpiowrite(int pin, bool value);
+
+/****************************************************************************
+ * Name: esp32c3_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ****************************************************************************/
+
+bool esp32c3_gpioread(int pin);
+
+/****************************************************************************
+ * Name: esp32c3_gpio_matrix_in
+ *
+ * Description:
+ * Set gpio input to a signal
+ * NOTE: one gpio can input to several signals
+ * If gpio == 0x30, cancel input to the signal, input 0 to signal
+ * If gpio == 0x38, cancel input to the signal, input 1 to signal
+ *
+ ****************************************************************************/
+
+void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
+
+/****************************************************************************
+ * Name: esp32c3_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to gpio
+ * NOTE: one signal can output to several gpios
+ * If signal_idx == 0x100, cancel output put to the gpio
+ *
+ ****************************************************************************/
+
+void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+ bool out_inv, bool oen_inv);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
new file mode 100644
index 0000000..662282c
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
@@ -0,0 +1,5287 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/esp32c3_soc.h"
+
+/****************************************************************************
+ * Pre-preprocessor Definitions
+ ****************************************************************************/
+
+#define GPIO_REG(io_num) (GPIO_PIN0_REG + ((io_num) * 0x4))
+
+#define GPIO_PIN_CONFIG_MSB 12
+#define GPIO_PIN_CONFIG_LSB 11
+#define GPIO_PIN_CONFIG_MASK 0x00001800
+#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE 1
+#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB 10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB 10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK 0x380
+#define GPIO_PIN_INT_TYPE_MSB 9
+#define GPIO_PIN_INT_TYPE_LSB 7
+#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE 1
+#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB 2
+#define GPIO_PIN_PAD_DRIVER_LSB 2
+#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
+
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+
+#define GPIO_BT_SEL 0xffffffff
+#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V 0xffffffff
+#define GPIO_BT_SEL_S 0
+
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+
+/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_OUT_DATA 0x03ffffff
+#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V 0x3ffffff
+#define GPIO_OUT_DATA_S 0
+
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+
+/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_OUT_W1TS 0x03ffffff
+#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
+#define GPIO_OUT_W1TS_V 0x3ffffff
+#define GPIO_OUT_W1TS_S 0
+
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+
+/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_OUT_W1TC 0x03ffffff
+#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
+#define GPIO_OUT_W1TC_V 0x3ffffff
+#define GPIO_OUT_W1TC_S 0
+
+#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c)
+
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+
+#define GPIO_SDIO_SEL 0x000000ff
+#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V 0xff
+#define GPIO_SDIO_SEL_S 0
+
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
+
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_ENABLE_DATA 0x03ffffff
+#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V 0x3ffffff
+#define GPIO_ENABLE_DATA_S 0
+
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
+
+/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_ENABLE_W1TS 0x03ffffff
+#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
+#define GPIO_ENABLE_W1TS_V 0x3ffffff
+#define GPIO_ENABLE_W1TS_S 0
+
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
+
+/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_ENABLE_W1TC 0x03ffffff
+#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
+#define GPIO_ENABLE_W1TC_V 0x3ffffff
+#define GPIO_ENABLE_W1TC_S 0
+
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
+
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */
+
+#define GPIO_STRAPPING 0x0000ffff
+#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V 0xffff
+#define GPIO_STRAPPING_S 0
+
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
+
+/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default: ; */
+
+#define GPIO_IN_DATA 0x03ffffff
+#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V 0x3ffffff
+#define GPIO_IN_DATA_S 0
+
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
+
+/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_STATUS_INT 0x03ffffff
+#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V 0x3ffffff
+#define GPIO_STATUS_INT_S 0
+
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
+
+/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_STATUS_W1TS 0x03ffffff
+#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
+#define GPIO_STATUS_W1TS_V 0x3ffffff
+#define GPIO_STATUS_W1TS_S 0
+
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
+
+/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_STATUS_W1TC 0x03ffffff
+#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
+#define GPIO_STATUS_W1TC_V 0x3ffffff
+#define GPIO_STATUS_W1TC_S 0
+
+#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c)
+
+/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_PROCPU_INT 0x03ffffff
+#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V 0x3ffffff
+#define GPIO_PROCPU_INT_S 0
+
+#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60)
+
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_PROCPU_NMI_INT 0x03ffffff
+#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V 0x3ffffff
+#define GPIO_PROCPU_NMI_INT_S 0
+
+#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64)
+
+/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_SDIO_INT 0x03ffffff
+#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V 0x3ffffff
+#define GPIO_SDIO_INT_S 0
+
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
+
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN0_INT_ENA 0x0000001f
+#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V 0x1f
+#define GPIO_PIN0_INT_ENA_S 13
+
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN0_CONFIG 0x00000003
+#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V 0x3
+#define GPIO_PIN0_CONFIG_S 11
+
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN0_INT_TYPE 0x00000007
+#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V 0x7
+#define GPIO_PIN0_INT_TYPE_S 7
+
+/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN0_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN0_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN0_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN_PAD_DRIVER_S 2
+
+#define GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V 0x1
+#define GPIO_PIN0_PAD_DRIVER_S 2
+
+/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN0_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN0_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN0_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
+
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN1_INT_ENA 0x0000001f
+#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V 0x1f
+#define GPIO_PIN1_INT_ENA_S 13
+
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN1_CONFIG 0x00000003
+#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V 0x3
+#define GPIO_PIN1_CONFIG_S 11
+
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN1_INT_TYPE 0x00000007
+#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V 0x7
+#define GPIO_PIN1_INT_TYPE_S 7
+
+/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN1_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
+#define GPIO_PIN1_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN1_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V 0x1
+#define GPIO_PIN1_PAD_DRIVER_S 2
+
+/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN1_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
+#define GPIO_PIN1_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN1_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
+
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN2_INT_ENA 0x0000001f
+#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V 0x1f
+#define GPIO_PIN2_INT_ENA_S 13
+
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN2_CONFIG 0x00000003
+#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V 0x3
+#define GPIO_PIN2_CONFIG_S 11
+
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN2_INT_TYPE 0x00000007
+#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V 0x7
+#define GPIO_PIN2_INT_TYPE_S 7
+
+/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN2_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
+#define GPIO_PIN2_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN2_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V 0x1
+#define GPIO_PIN2_PAD_DRIVER_S 2
+
+/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN2_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
+#define GPIO_PIN2_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN2_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
+
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN3_INT_ENA 0x0000001f
+#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V 0x1f
+#define GPIO_PIN3_INT_ENA_S 13
+
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN3_CONFIG 0x00000003
+#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V 0x3
+#define GPIO_PIN3_CONFIG_S 11
+
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN3_INT_TYPE 0x00000007
+#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V 0x7
+#define GPIO_PIN3_INT_TYPE_S 7
+
+/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN3_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
+#define GPIO_PIN3_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN3_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V 0x1
+#define GPIO_PIN3_PAD_DRIVER_S 2
+
+/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN3_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
+#define GPIO_PIN3_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN3_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
+
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN4_INT_ENA 0x0000001f
+#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V 0x1f
+#define GPIO_PIN4_INT_ENA_S 13
+
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN4_CONFIG 0x00000003
+#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V 0x3
+#define GPIO_PIN4_CONFIG_S 11
+
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN4_INT_TYPE 0x00000007
+#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V 0x7
+#define GPIO_PIN4_INT_TYPE_S 7
+
+/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN4_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
+#define GPIO_PIN4_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN4_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V 0x1
+#define GPIO_PIN4_PAD_DRIVER_S 2
+
+/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN4_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
+#define GPIO_PIN4_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN4_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
+
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN5_INT_ENA 0x0000001f
+#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V 0x1f
+#define GPIO_PIN5_INT_ENA_S 13
+
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN5_CONFIG 0x00000003
+#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V 0x3
+#define GPIO_PIN5_CONFIG_S 11
+
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN5_INT_TYPE 0x00000007
+#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V 0x7
+#define GPIO_PIN5_INT_TYPE_S 7
+
+/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN5_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
+#define GPIO_PIN5_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN5_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V 0x1
+#define GPIO_PIN5_PAD_DRIVER_S 2
+
+/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN5_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
+#define GPIO_PIN5_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN5_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
+
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN6_INT_ENA 0x0000001f
+#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V 0x1f
+#define GPIO_PIN6_INT_ENA_S 13
+
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN6_CONFIG 0x00000003
+#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V 0x3
+#define GPIO_PIN6_CONFIG_S 11
+
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN6_INT_TYPE 0x00000007
+#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V 0x7
+#define GPIO_PIN6_INT_TYPE_S 7
+
+/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN6_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
+#define GPIO_PIN6_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN6_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V 0x1
+#define GPIO_PIN6_PAD_DRIVER_S 2
+
+/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN6_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
+#define GPIO_PIN6_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN6_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
+
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN7_INT_ENA 0x0000001f
+#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V 0x1f
+#define GPIO_PIN7_INT_ENA_S 13
+
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN7_CONFIG 0x00000003
+#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V 0x3
+#define GPIO_PIN7_CONFIG_S 11
+
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN7_INT_TYPE 0x00000007
+#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V 0x7
+#define GPIO_PIN7_INT_TYPE_S 7
+
+/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN7_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
+#define GPIO_PIN7_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN7_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V 0x1
+#define GPIO_PIN7_PAD_DRIVER_S 2
+
+/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN7_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
+#define GPIO_PIN7_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN7_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
+
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN8_INT_ENA 0x0000001f
+#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V 0x1f
+#define GPIO_PIN8_INT_ENA_S 13
+
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN8_CONFIG 0x00000003
+#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V 0x3
+#define GPIO_PIN8_CONFIG_S 11
+
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN8_INT_TYPE 0x00000007
+#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V 0x7
+#define GPIO_PIN8_INT_TYPE_S 7
+
+/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN8_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
+#define GPIO_PIN8_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN8_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V 0x1
+#define GPIO_PIN8_PAD_DRIVER_S 2
+
+/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN8_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
+#define GPIO_PIN8_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN8_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
+
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN9_INT_ENA 0x0000001f
+#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V 0x1f
+#define GPIO_PIN9_INT_ENA_S 13
+
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN9_CONFIG 0x00000003
+#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V 0x3
+#define GPIO_PIN9_CONFIG_S 11
+
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN9_INT_TYPE 0x00000007
+#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V 0x7
+#define GPIO_PIN9_INT_TYPE_S 7
+
+/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN9_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
+#define GPIO_PIN9_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN9_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V 0x1
+#define GPIO_PIN9_PAD_DRIVER_S 2
+
+/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN9_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
+#define GPIO_PIN9_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN9_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
+
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN10_INT_ENA 0x0000001f
+#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V 0x1f
+#define GPIO_PIN10_INT_ENA_S 13
+
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN10_CONFIG 0x00000003
+#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V 0x3
+#define GPIO_PIN10_CONFIG_S 11
+
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN10_INT_TYPE 0x00000007
+#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V 0x7
+#define GPIO_PIN10_INT_TYPE_S 7
+
+/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN10_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
+#define GPIO_PIN10_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN10_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V 0x1
+#define GPIO_PIN10_PAD_DRIVER_S 2
+
+/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN10_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
+#define GPIO_PIN10_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN10_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
+
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN11_INT_ENA 0x0000001f
+#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V 0x1f
+#define GPIO_PIN11_INT_ENA_S 13
+
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN11_CONFIG 0x00000003
+#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V 0x3
+#define GPIO_PIN11_CONFIG_S 11
+
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN11_INT_TYPE 0x00000007
+#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V 0x7
+#define GPIO_PIN11_INT_TYPE_S 7
+
+/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN11_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
+#define GPIO_PIN11_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN11_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V 0x1
+#define GPIO_PIN11_PAD_DRIVER_S 2
+
+/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN11_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
+#define GPIO_PIN11_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN11_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
+
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN12_INT_ENA 0x0000001f
+#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V 0x1f
+#define GPIO_PIN12_INT_ENA_S 13
+
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN12_CONFIG 0x00000003
+#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V 0x3
+#define GPIO_PIN12_CONFIG_S 11
+
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN12_INT_TYPE 0x00000007
+#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V 0x7
+#define GPIO_PIN12_INT_TYPE_S 7
+
+/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN12_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
+#define GPIO_PIN12_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN12_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V 0x1
+#define GPIO_PIN12_PAD_DRIVER_S 2
+
+/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN12_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
+#define GPIO_PIN12_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN12_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
+
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN13_INT_ENA 0x0000001f
+#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V 0x1f
+#define GPIO_PIN13_INT_ENA_S 13
+
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN13_CONFIG 0x00000003
+#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V 0x3
+#define GPIO_PIN13_CONFIG_S 11
+
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN13_INT_TYPE 0x00000007
+#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V 0x7
+#define GPIO_PIN13_INT_TYPE_S 7
+
+/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN13_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
+#define GPIO_PIN13_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN13_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V 0x1
+#define GPIO_PIN13_PAD_DRIVER_S 2
+
+/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN13_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
+#define GPIO_PIN13_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN13_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
+
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN14_INT_ENA 0x0000001f
+#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V 0x1f
+#define GPIO_PIN14_INT_ENA_S 13
+
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN14_CONFIG 0x00000003
+#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V 0x3
+#define GPIO_PIN14_CONFIG_S 11
+
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN14_INT_TYPE 0x00000007
+#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V 0x7
+#define GPIO_PIN14_INT_TYPE_S 7
+
+/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN14_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
+#define GPIO_PIN14_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN14_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V 0x1
+#define GPIO_PIN14_PAD_DRIVER_S 2
+
+/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN14_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
+#define GPIO_PIN14_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN14_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
+
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN15_INT_ENA 0x0000001f
+#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V 0x1f
+#define GPIO_PIN15_INT_ENA_S 13
+
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN15_CONFIG 0x00000003
+#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V 0x3
+#define GPIO_PIN15_CONFIG_S 11
+
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN15_INT_TYPE 0x00000007
+#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V 0x7
+#define GPIO_PIN15_INT_TYPE_S 7
+
+/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN15_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
+#define GPIO_PIN15_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN15_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V 0x1
+#define GPIO_PIN15_PAD_DRIVER_S 2
+
+/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN15_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
+#define GPIO_PIN15_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN15_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
+
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN16_INT_ENA 0x0000001f
+#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V 0x1f
+#define GPIO_PIN16_INT_ENA_S 13
+
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN16_CONFIG 0x00000003
+#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V 0x3
+#define GPIO_PIN16_CONFIG_S 11
+
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN16_INT_TYPE 0x00000007
+#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V 0x7
+#define GPIO_PIN16_INT_TYPE_S 7
+
+/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN16_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
+#define GPIO_PIN16_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN16_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V 0x1
+#define GPIO_PIN16_PAD_DRIVER_S 2
+
+/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN16_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
+#define GPIO_PIN16_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN16_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
+
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN17_INT_ENA 0x0000001f
+#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V 0x1f
+#define GPIO_PIN17_INT_ENA_S 13
+
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN17_CONFIG 0x00000003
+#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V 0x3
+#define GPIO_PIN17_CONFIG_S 11
+
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN17_INT_TYPE 0x00000007
+#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V 0x7
+#define GPIO_PIN17_INT_TYPE_S 7
+
+/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN17_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
+#define GPIO_PIN17_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN17_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V 0x1
+#define GPIO_PIN17_PAD_DRIVER_S 2
+
+/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN17_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
+#define GPIO_PIN17_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN17_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
+
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN18_INT_ENA 0x0000001f
+#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V 0x1f
+#define GPIO_PIN18_INT_ENA_S 13
+
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN18_CONFIG 0x00000003
+#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V 0x3
+#define GPIO_PIN18_CONFIG_S 11
+
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN18_INT_TYPE 0x00000007
+#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V 0x7
+#define GPIO_PIN18_INT_TYPE_S 7
+
+/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN18_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
+#define GPIO_PIN18_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN18_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN18_PAD_DRIVER (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V 0x1
+#define GPIO_PIN18_PAD_DRIVER_S 2
+
+/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN18_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
+#define GPIO_PIN18_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN18_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
+
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN19_INT_ENA 0x0000001f
+#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V 0x1f
+#define GPIO_PIN19_INT_ENA_S 13
+
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN19_CONFIG 0x00000003
+#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V 0x3
+#define GPIO_PIN19_CONFIG_S 11
+
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN19_INT_TYPE 0x00000007
+#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V 0x7
+#define GPIO_PIN19_INT_TYPE_S 7
+
+/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN19_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
+#define GPIO_PIN19_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN19_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN19_PAD_DRIVER (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V 0x1
+#define GPIO_PIN19_PAD_DRIVER_S 2
+
+/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN19_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
+#define GPIO_PIN19_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN19_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
+
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN20_INT_ENA 0x0000001f
+#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V 0x1f
+#define GPIO_PIN20_INT_ENA_S 13
+
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN20_CONFIG 0x00000003
+#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V 0x3
+#define GPIO_PIN20_CONFIG_S 11
+
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN20_INT_TYPE 0x00000007
+#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V 0x7
+#define GPIO_PIN20_INT_TYPE_S 7
+
+/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN20_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
+#define GPIO_PIN20_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN20_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN20_PAD_DRIVER (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V 0x1
+#define GPIO_PIN20_PAD_DRIVER_S 2
+
+/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN20_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
+#define GPIO_PIN20_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN20_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
+
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN21_INT_ENA 0x0000001f
+#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V 0x1f
+#define GPIO_PIN21_INT_ENA_S 13
+
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN21_CONFIG 0x00000003
+#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V 0x3
+#define GPIO_PIN21_CONFIG_S 11
+
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN21_INT_TYPE 0x00000007
+#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V 0x7
+#define GPIO_PIN21_INT_TYPE_S 7
+
+/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN21_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
+#define GPIO_PIN21_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN21_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN21_PAD_DRIVER (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V 0x1
+#define GPIO_PIN21_PAD_DRIVER_S 2
+
+/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN21_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
+#define GPIO_PIN21_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN21_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
+
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN22_INT_ENA 0x0000001f
+#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V 0x1f
+#define GPIO_PIN22_INT_ENA_S 13
+
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN22_CONFIG 0x00000003
+#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V 0x3
+#define GPIO_PIN22_CONFIG_S 11
+
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN22_INT_TYPE 0x00000007
+#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V 0x7
+#define GPIO_PIN22_INT_TYPE_S 7
+
+/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN22_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
+#define GPIO_PIN22_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN22_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN22_PAD_DRIVER (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V 0x1
+#define GPIO_PIN22_PAD_DRIVER_S 2
+
+/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN22_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
+#define GPIO_PIN22_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN22_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
+
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN23_INT_ENA 0x0000001f
+#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V 0x1f
+#define GPIO_PIN23_INT_ENA_S 13
+
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN23_CONFIG 0x00000003
+#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V 0x3
+#define GPIO_PIN23_CONFIG_S 11
+
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN23_INT_TYPE 0x00000007
+#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V 0x7
+#define GPIO_PIN23_INT_TYPE_S 7
+
+/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN23_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
+#define GPIO_PIN23_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN23_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN23_PAD_DRIVER (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V 0x1
+#define GPIO_PIN23_PAD_DRIVER_S 2
+
+/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN23_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
+#define GPIO_PIN23_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN23_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
+
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN24_INT_ENA 0x0000001f
+#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V 0x1f
+#define GPIO_PIN24_INT_ENA_S 13
+
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN24_CONFIG 0x00000003
+#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V 0x3
+#define GPIO_PIN24_CONFIG_S 11
+
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN24_INT_TYPE 0x00000007
+#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V 0x7
+#define GPIO_PIN24_INT_TYPE_S 7
+
+/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN24_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
+#define GPIO_PIN24_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN24_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN24_PAD_DRIVER (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V 0x1
+#define GPIO_PIN24_PAD_DRIVER_S 2
+
+/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN24_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
+#define GPIO_PIN24_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN24_SYNC2_BYPASS_S 0
+
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
+
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+
+#define GPIO_PIN25_INT_ENA 0x0000001f
+#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V 0x1f
+#define GPIO_PIN25_INT_ENA_S 13
+
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+
+#define GPIO_PIN25_CONFIG 0x00000003
+#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V 0x3
+#define GPIO_PIN25_CONFIG_S 11
+
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S 10
+
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+
+#define GPIO_PIN25_INT_TYPE 0x00000007
+#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V 0x7
+#define GPIO_PIN25_INT_TYPE_S 7
+
+/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+
+#define GPIO_PIN25_SYNC1_BYPASS 0x00000003
+#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
+#define GPIO_PIN25_SYNC1_BYPASS_V 0x3
+#define GPIO_PIN25_SYNC1_BYPASS_S 3
+
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+
+#define GPIO_PIN25_PAD_DRIVER (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V 0x1
+#define GPIO_PIN25_PAD_DRIVER_S 2
+
+/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+
+#define GPIO_PIN25_SYNC2_BYPASS 0x00000003
+#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
+#define GPIO_PIN25_SYNC2_BYPASS_V 0x3
+#define GPIO_PIN25_SYNC2_BYPASS_S 0
+
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c)
+
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+
+#define GPIO_STATUS_INTERRUPT_NEXT 0x03ffffff
+#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
+#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3ffffff
+#define GPIO_STATUS_INTERRUPT_NEXT_S 0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154)
+
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG0_IN_SEL (BIT(6))
+#define GPIO_SIG0_IN_SEL_M (BIT(6))
+#define GPIO_SIG0_IN_SEL_V 0x1
+#define GPIO_SIG0_IN_SEL_S 6
+
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC0_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_V 0x1
+#define GPIO_FUNC0_IN_INV_SEL_S 5
+
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC0_IN_SEL 0x0000001f
+#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V 0x1f
+#define GPIO_FUNC0_IN_SEL_S 0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158)
+
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG1_IN_SEL (BIT(6))
+#define GPIO_SIG1_IN_SEL_M (BIT(6))
+#define GPIO_SIG1_IN_SEL_V 0x1
+#define GPIO_SIG1_IN_SEL_S 6
+
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC1_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_V 0x1
+#define GPIO_FUNC1_IN_INV_SEL_S 5
+
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC1_IN_SEL 0x0000001f
+#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V 0x1f
+#define GPIO_FUNC1_IN_SEL_S 0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG2_IN_SEL (BIT(6))
+#define GPIO_SIG2_IN_SEL_M (BIT(6))
+#define GPIO_SIG2_IN_SEL_V 0x1
+#define GPIO_SIG2_IN_SEL_S 6
+
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC2_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_V 0x1
+#define GPIO_FUNC2_IN_INV_SEL_S 5
+
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC2_IN_SEL 0x0000001f
+#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V 0x1f
+#define GPIO_FUNC2_IN_SEL_S 0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG3_IN_SEL (BIT(6))
+#define GPIO_SIG3_IN_SEL_M (BIT(6))
+#define GPIO_SIG3_IN_SEL_V 0x1
+#define GPIO_SIG3_IN_SEL_S 6
+
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC3_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_V 0x1
+#define GPIO_FUNC3_IN_INV_SEL_S 5
+
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC3_IN_SEL 0x0000001f
+#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V 0x1f
+#define GPIO_FUNC3_IN_SEL_S 0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG4_IN_SEL (BIT(6))
+#define GPIO_SIG4_IN_SEL_M (BIT(6))
+#define GPIO_SIG4_IN_SEL_V 0x1
+#define GPIO_SIG4_IN_SEL_S 6
+
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC4_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_V 0x1
+#define GPIO_FUNC4_IN_INV_SEL_S 5
+
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC4_IN_SEL 0x0000001f
+#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V 0x1f
+#define GPIO_FUNC4_IN_SEL_S 0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG5_IN_SEL (BIT(6))
+#define GPIO_SIG5_IN_SEL_M (BIT(6))
+#define GPIO_SIG5_IN_SEL_V 0x1
+#define GPIO_SIG5_IN_SEL_S 6
+
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC5_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_V 0x1
+#define GPIO_FUNC5_IN_INV_SEL_S 5
+
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC5_IN_SEL 0x0000001f
+#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V 0x1f
+#define GPIO_FUNC5_IN_SEL_S 0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG6_IN_SEL (BIT(6))
+#define GPIO_SIG6_IN_SEL_M (BIT(6))
+#define GPIO_SIG6_IN_SEL_V 0x1
+#define GPIO_SIG6_IN_SEL_S 6
+
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC6_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_V 0x1
+#define GPIO_FUNC6_IN_INV_SEL_S 5
+
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC6_IN_SEL 0x0000001f
+#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V 0x1f
+#define GPIO_FUNC6_IN_SEL_S 0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG7_IN_SEL (BIT(6))
+#define GPIO_SIG7_IN_SEL_M (BIT(6))
+#define GPIO_SIG7_IN_SEL_V 0x1
+#define GPIO_SIG7_IN_SEL_S 6
+
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC7_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_V 0x1
+#define GPIO_FUNC7_IN_INV_SEL_S 5
+
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC7_IN_SEL 0x0000001f
+#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V 0x1f
+#define GPIO_FUNC7_IN_SEL_S 0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG8_IN_SEL (BIT(6))
+#define GPIO_SIG8_IN_SEL_M (BIT(6))
+#define GPIO_SIG8_IN_SEL_V 0x1
+#define GPIO_SIG8_IN_SEL_S 6
+
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC8_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_V 0x1
+#define GPIO_FUNC8_IN_INV_SEL_S 5
+
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC8_IN_SEL 0x0000001f
+#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V 0x1f
+#define GPIO_FUNC8_IN_SEL_S 0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
+
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG9_IN_SEL (BIT(6))
+#define GPIO_SIG9_IN_SEL_M (BIT(6))
+#define GPIO_SIG9_IN_SEL_V 0x1
+#define GPIO_SIG9_IN_SEL_S 6
+
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC9_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_V 0x1
+#define GPIO_FUNC9_IN_INV_SEL_S 5
+
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC9_IN_SEL 0x0000001f
+#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V 0x1f
+#define GPIO_FUNC9_IN_SEL_S 0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
+
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG10_IN_SEL (BIT(6))
+#define GPIO_SIG10_IN_SEL_M (BIT(6))
+#define GPIO_SIG10_IN_SEL_V 0x1
+#define GPIO_SIG10_IN_SEL_S 6
+
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC10_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_V 0x1
+#define GPIO_FUNC10_IN_INV_SEL_S 5
+
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC10_IN_SEL 0x0000001f
+#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V 0x1f
+#define GPIO_FUNC10_IN_SEL_S 0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
+
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG11_IN_SEL (BIT(6))
+#define GPIO_SIG11_IN_SEL_M (BIT(6))
+#define GPIO_SIG11_IN_SEL_V 0x1
+#define GPIO_SIG11_IN_SEL_S 6
+
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC11_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_V 0x1
+#define GPIO_FUNC11_IN_INV_SEL_S 5
+
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC11_IN_SEL 0x0000001f
+#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V 0x1f
+#define GPIO_FUNC11_IN_SEL_S 0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
+
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG12_IN_SEL (BIT(6))
+#define GPIO_SIG12_IN_SEL_M (BIT(6))
+#define GPIO_SIG12_IN_SEL_V 0x1
+#define GPIO_SIG12_IN_SEL_S 6
+
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC12_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_V 0x1
+#define GPIO_FUNC12_IN_INV_SEL_S 5
+
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC12_IN_SEL 0x0000001f
+#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V 0x1f
+#define GPIO_FUNC12_IN_SEL_S 0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
+
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG13_IN_SEL (BIT(6))
+#define GPIO_SIG13_IN_SEL_M (BIT(6))
+#define GPIO_SIG13_IN_SEL_V 0x1
+#define GPIO_SIG13_IN_SEL_S 6
+
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC13_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_V 0x1
+#define GPIO_FUNC13_IN_INV_SEL_S 5
+
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC13_IN_SEL 0x0000001f
+#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V 0x1f
+#define GPIO_FUNC13_IN_SEL_S 0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
+
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG14_IN_SEL (BIT(6))
+#define GPIO_SIG14_IN_SEL_M (BIT(6))
+#define GPIO_SIG14_IN_SEL_V 0x1
+#define GPIO_SIG14_IN_SEL_S 6
+
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC14_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_V 0x1
+#define GPIO_FUNC14_IN_INV_SEL_S 5
+
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC14_IN_SEL 0x0000001f
+#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V 0x1f
+#define GPIO_FUNC14_IN_SEL_S 0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
+
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG15_IN_SEL (BIT(6))
+#define GPIO_SIG15_IN_SEL_M (BIT(6))
+#define GPIO_SIG15_IN_SEL_V 0x1
+#define GPIO_SIG15_IN_SEL_S 6
+
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC15_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_V 0x1
+#define GPIO_FUNC15_IN_INV_SEL_S 5
+
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC15_IN_SEL 0x0000001f
+#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V 0x1f
+#define GPIO_FUNC15_IN_SEL_S 0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
+
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG16_IN_SEL (BIT(6))
+#define GPIO_SIG16_IN_SEL_M (BIT(6))
+#define GPIO_SIG16_IN_SEL_V 0x1
+#define GPIO_SIG16_IN_SEL_S 6
+
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC16_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_V 0x1
+#define GPIO_FUNC16_IN_INV_SEL_S 5
+
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC16_IN_SEL 0x0000001f
+#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V 0x1f
+#define GPIO_FUNC16_IN_SEL_S 0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
+
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG17_IN_SEL (BIT(6))
+#define GPIO_SIG17_IN_SEL_M (BIT(6))
+#define GPIO_SIG17_IN_SEL_V 0x1
+#define GPIO_SIG17_IN_SEL_S 6
+
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC17_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_V 0x1
+#define GPIO_FUNC17_IN_INV_SEL_S 5
+
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC17_IN_SEL 0x0000001f
+
+#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V 0x1f
+#define GPIO_FUNC17_IN_SEL_S 0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
+
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG18_IN_SEL (BIT(6))
+#define GPIO_SIG18_IN_SEL_M (BIT(6))
+#define GPIO_SIG18_IN_SEL_V 0x1
+#define GPIO_SIG18_IN_SEL_S 6
+
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC18_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_V 0x1
+#define GPIO_FUNC18_IN_INV_SEL_S 5
+
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC18_IN_SEL 0x0000001f
+#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V 0x1f
+#define GPIO_FUNC18_IN_SEL_S 0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
+
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG19_IN_SEL (BIT(6))
+#define GPIO_SIG19_IN_SEL_M (BIT(6))
+#define GPIO_SIG19_IN_SEL_V 0x1
+#define GPIO_SIG19_IN_SEL_S 6
+
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC19_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_V 0x1
+#define GPIO_FUNC19_IN_INV_SEL_S 5
+
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC19_IN_SEL 0x0000001f
+#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V 0x1f
+#define GPIO_FUNC19_IN_SEL_S 0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
+
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG20_IN_SEL (BIT(6))
+#define GPIO_SIG20_IN_SEL_M (BIT(6))
+#define GPIO_SIG20_IN_SEL_V 0x1
+#define GPIO_SIG20_IN_SEL_S 6
+
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC20_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_V 0x1
+#define GPIO_FUNC20_IN_INV_SEL_S 5
+
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC20_IN_SEL 0x0000001f
+#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V 0x1f
+#define GPIO_FUNC20_IN_SEL_S 0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
+
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG21_IN_SEL (BIT(6))
+#define GPIO_SIG21_IN_SEL_M (BIT(6))
+#define GPIO_SIG21_IN_SEL_V 0x1
+#define GPIO_SIG21_IN_SEL_S 6
+
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC21_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_V 0x1
+#define GPIO_FUNC21_IN_INV_SEL_S 5
+
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC21_IN_SEL 0x0000001f
+#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V 0x1f
+#define GPIO_FUNC21_IN_SEL_S 0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
+
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG22_IN_SEL (BIT(6))
+#define GPIO_SIG22_IN_SEL_M (BIT(6))
+#define GPIO_SIG22_IN_SEL_V 0x1
+#define GPIO_SIG22_IN_SEL_S 6
+
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC22_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_V 0x1
+#define GPIO_FUNC22_IN_INV_SEL_S 5
+
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC22_IN_SEL 0x0000001f
+#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V 0x1f
+#define GPIO_FUNC22_IN_SEL_S 0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
+
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG23_IN_SEL (BIT(6))
+#define GPIO_SIG23_IN_SEL_M (BIT(6))
+#define GPIO_SIG23_IN_SEL_V 0x1
+#define GPIO_SIG23_IN_SEL_S 6
+
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC23_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_V 0x1
+#define GPIO_FUNC23_IN_INV_SEL_S 5
+
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC23_IN_SEL 0x0000001f
+#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V 0x1f
+#define GPIO_FUNC23_IN_SEL_S 0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
+
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG24_IN_SEL (BIT(6))
+#define GPIO_SIG24_IN_SEL_M (BIT(6))
+#define GPIO_SIG24_IN_SEL_V 0x1
+#define GPIO_SIG24_IN_SEL_S 6
+
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC24_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_V 0x1
+#define GPIO_FUNC24_IN_INV_SEL_S 5
+
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC24_IN_SEL 0x0000001f
+#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V 0x1f
+#define GPIO_FUNC24_IN_SEL_S 0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
+
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG25_IN_SEL (BIT(6))
+#define GPIO_SIG25_IN_SEL_M (BIT(6))
+#define GPIO_SIG25_IN_SEL_V 0x1
+#define GPIO_SIG25_IN_SEL_S 6
+
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC25_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_V 0x1
+#define GPIO_FUNC25_IN_INV_SEL_S 5
+
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC25_IN_SEL 0x0000001f
+#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V 0x1f
+#define GPIO_FUNC25_IN_SEL_S 0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
+
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG26_IN_SEL (BIT(6))
+#define GPIO_SIG26_IN_SEL_M (BIT(6))
+#define GPIO_SIG26_IN_SEL_V 0x1
+#define GPIO_SIG26_IN_SEL_S 6
+
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC26_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_V 0x1
+#define GPIO_FUNC26_IN_INV_SEL_S 5
+
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC26_IN_SEL 0x0000001f
+#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V 0x1f
+#define GPIO_FUNC26_IN_SEL_S 0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
+
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG27_IN_SEL (BIT(6))
+#define GPIO_SIG27_IN_SEL_M (BIT(6))
+#define GPIO_SIG27_IN_SEL_V 0x1
+#define GPIO_SIG27_IN_SEL_S 6
+
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC27_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_V 0x1
+#define GPIO_FUNC27_IN_INV_SEL_S 5
+
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC27_IN_SEL 0x0000001f
+#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V 0x1f
+#define GPIO_FUNC27_IN_SEL_S 0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
+
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG28_IN_SEL (BIT(6))
+#define GPIO_SIG28_IN_SEL_M (BIT(6))
+#define GPIO_SIG28_IN_SEL_V 0x1
+#define GPIO_SIG28_IN_SEL_S 6
+
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC28_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_V 0x1
+#define GPIO_FUNC28_IN_INV_SEL_S 5
+
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC28_IN_SEL 0x0000001f
+#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V 0x1f
+#define GPIO_FUNC28_IN_SEL_S 0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
+
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG29_IN_SEL (BIT(6))
+#define GPIO_SIG29_IN_SEL_M (BIT(6))
+#define GPIO_SIG29_IN_SEL_V 0x1
+#define GPIO_SIG29_IN_SEL_S 6
+
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC29_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_V 0x1
+#define GPIO_FUNC29_IN_INV_SEL_S 5
+
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC29_IN_SEL 0x0000001f
+#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V 0x1f
+#define GPIO_FUNC29_IN_SEL_S 0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
+
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG30_IN_SEL (BIT(6))
+#define GPIO_SIG30_IN_SEL_M (BIT(6))
+#define GPIO_SIG30_IN_SEL_V 0x1
+#define GPIO_SIG30_IN_SEL_S 6
+
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC30_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_V 0x1
+#define GPIO_FUNC30_IN_INV_SEL_S 5
+
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC30_IN_SEL 0x0000001f
+#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V 0x1f
+#define GPIO_FUNC30_IN_SEL_S 0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
+
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG31_IN_SEL (BIT(6))
+#define GPIO_SIG31_IN_SEL_M (BIT(6))
+#define GPIO_SIG31_IN_SEL_V 0x1
+#define GPIO_SIG31_IN_SEL_S 6
+
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC31_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_V 0x1
+#define GPIO_FUNC31_IN_INV_SEL_S 5
+
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC31_IN_SEL 0x0000001f
+#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V 0x1f
+#define GPIO_FUNC31_IN_SEL_S 0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
+
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG32_IN_SEL (BIT(6))
+#define GPIO_SIG32_IN_SEL_M (BIT(6))
+#define GPIO_SIG32_IN_SEL_V 0x1
+#define GPIO_SIG32_IN_SEL_S 6
+
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC32_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_V 0x1
+#define GPIO_FUNC32_IN_INV_SEL_S 5
+
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC32_IN_SEL 0x0000001f
+#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V 0x1f
+#define GPIO_FUNC32_IN_SEL_S 0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
+
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG33_IN_SEL (BIT(6))
+#define GPIO_SIG33_IN_SEL_M (BIT(6))
+#define GPIO_SIG33_IN_SEL_V 0x1
+#define GPIO_SIG33_IN_SEL_S 6
+
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC33_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_V 0x1
+#define GPIO_FUNC33_IN_INV_SEL_S 5
+
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC33_IN_SEL 0x0000001f
+#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V 0x1f
+#define GPIO_FUNC33_IN_SEL_S 0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
+
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG34_IN_SEL (BIT(6))
+#define GPIO_SIG34_IN_SEL_M (BIT(6))
+#define GPIO_SIG34_IN_SEL_V 0x1
+#define GPIO_SIG34_IN_SEL_S 6
+
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC34_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_V 0x1
+#define GPIO_FUNC34_IN_INV_SEL_S 5
+
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC34_IN_SEL 0x0000001f
+#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V 0x1f
+#define GPIO_FUNC34_IN_SEL_S 0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
+
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG35_IN_SEL (BIT(6))
+#define GPIO_SIG35_IN_SEL_M (BIT(6))
+#define GPIO_SIG35_IN_SEL_V 0x1
+#define GPIO_SIG35_IN_SEL_S 6
+
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC35_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_V 0x1
+#define GPIO_FUNC35_IN_INV_SEL_S 5
+
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC35_IN_SEL 0x0000001f
+#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V 0x1f
+#define GPIO_FUNC35_IN_SEL_S 0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
+
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG36_IN_SEL (BIT(6))
+#define GPIO_SIG36_IN_SEL_M (BIT(6))
+#define GPIO_SIG36_IN_SEL_V 0x1
+#define GPIO_SIG36_IN_SEL_S 6
+
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC36_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_V 0x1
+#define GPIO_FUNC36_IN_INV_SEL_S 5
+
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC36_IN_SEL 0x0000001f
+#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V 0x1f
+#define GPIO_FUNC36_IN_SEL_S 0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
+
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG37_IN_SEL (BIT(6))
+#define GPIO_SIG37_IN_SEL_M (BIT(6))
+#define GPIO_SIG37_IN_SEL_V 0x1
+#define GPIO_SIG37_IN_SEL_S 6
+
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC37_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_V 0x1
+#define GPIO_FUNC37_IN_INV_SEL_S 5
+
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC37_IN_SEL 0x0000001f
+#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V 0x1f
+#define GPIO_FUNC37_IN_SEL_S 0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
+
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG38_IN_SEL (BIT(6))
+#define GPIO_SIG38_IN_SEL_M (BIT(6))
+#define GPIO_SIG38_IN_SEL_V 0x1
+#define GPIO_SIG38_IN_SEL_S 6
+
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC38_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_V 0x1
+#define GPIO_FUNC38_IN_INV_SEL_S 5
+
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC38_IN_SEL 0x0000001f
+#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V 0x1f
+#define GPIO_FUNC38_IN_SEL_S 0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
+
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG39_IN_SEL (BIT(6))
+#define GPIO_SIG39_IN_SEL_M (BIT(6))
+#define GPIO_SIG39_IN_SEL_V 0x1
+#define GPIO_SIG39_IN_SEL_S 6
+
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC39_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_V 0x1
+#define GPIO_FUNC39_IN_INV_SEL_S 5
+
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC39_IN_SEL 0x0000001f
+#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V 0x1f
+#define GPIO_FUNC39_IN_SEL_S 0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
+
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG40_IN_SEL (BIT(6))
+#define GPIO_SIG40_IN_SEL_M (BIT(6))
+#define GPIO_SIG40_IN_SEL_V 0x1
+#define GPIO_SIG40_IN_SEL_S 6
+
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC40_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_V 0x1
+#define GPIO_FUNC40_IN_INV_SEL_S 5
+
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC40_IN_SEL 0x0000001f
+#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V 0x1f
+#define GPIO_FUNC40_IN_SEL_S 0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
+
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG41_IN_SEL (BIT(6))
+#define GPIO_SIG41_IN_SEL_M (BIT(6))
+#define GPIO_SIG41_IN_SEL_V 0x1
+#define GPIO_SIG41_IN_SEL_S 6
+
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC41_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_V 0x1
+#define GPIO_FUNC41_IN_INV_SEL_S 5
+
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC41_IN_SEL 0x0000001f
+#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V 0x1f
+#define GPIO_FUNC41_IN_SEL_S 0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
+
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG42_IN_SEL (BIT(6))
+#define GPIO_SIG42_IN_SEL_M (BIT(6))
+#define GPIO_SIG42_IN_SEL_V 0x1
+#define GPIO_SIG42_IN_SEL_S 6
+
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC42_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_V 0x1
+#define GPIO_FUNC42_IN_INV_SEL_S 5
+
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC42_IN_SEL 0x0000001f
+#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V 0x1f
+#define GPIO_FUNC42_IN_SEL_S 0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
+
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG43_IN_SEL (BIT(6))
+#define GPIO_SIG43_IN_SEL_M (BIT(6))
+#define GPIO_SIG43_IN_SEL_V 0x1
+#define GPIO_SIG43_IN_SEL_S 6
+
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC43_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_V 0x1
+#define GPIO_FUNC43_IN_INV_SEL_S 5
+
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC43_IN_SEL 0x0000001f
+#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V 0x1f
+#define GPIO_FUNC43_IN_SEL_S 0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
+
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG44_IN_SEL (BIT(6))
+#define GPIO_SIG44_IN_SEL_M (BIT(6))
+#define GPIO_SIG44_IN_SEL_V 0x1
+#define GPIO_SIG44_IN_SEL_S 6
+
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC44_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_V 0x1
+#define GPIO_FUNC44_IN_INV_SEL_S 5
+
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC44_IN_SEL 0x0000001f
+#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V 0x1f
+#define GPIO_FUNC44_IN_SEL_S 0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
+
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG45_IN_SEL (BIT(6))
+#define GPIO_SIG45_IN_SEL_M (BIT(6))
+#define GPIO_SIG45_IN_SEL_V 0x1
+#define GPIO_SIG45_IN_SEL_S 6
+
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC45_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_V 0x1
+#define GPIO_FUNC45_IN_INV_SEL_S 5
+
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC45_IN_SEL 0x0000001f
+#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V 0x1f
+#define GPIO_FUNC45_IN_SEL_S 0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
+
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG46_IN_SEL (BIT(6))
+#define GPIO_SIG46_IN_SEL_M (BIT(6))
+#define GPIO_SIG46_IN_SEL_V 0x1
+#define GPIO_SIG46_IN_SEL_S 6
+
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC46_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_V 0x1
+#define GPIO_FUNC46_IN_INV_SEL_S 5
+
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC46_IN_SEL 0x0000001f
+#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V 0x1f
+#define GPIO_FUNC46_IN_SEL_S 0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210)
+
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG47_IN_SEL (BIT(6))
+#define GPIO_SIG47_IN_SEL_M (BIT(6))
+#define GPIO_SIG47_IN_SEL_V 0x1
+#define GPIO_SIG47_IN_SEL_S 6
+
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC47_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_V 0x1
+#define GPIO_FUNC47_IN_INV_SEL_S 5
+
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC47_IN_SEL 0x0000001f
+#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V 0x1f
+#define GPIO_FUNC47_IN_SEL_S 0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
+
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG48_IN_SEL (BIT(6))
+#define GPIO_SIG48_IN_SEL_M (BIT(6))
+#define GPIO_SIG48_IN_SEL_V 0x1
+#define GPIO_SIG48_IN_SEL_S 6
+
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC48_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_V 0x1
+#define GPIO_FUNC48_IN_INV_SEL_S 5
+
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC48_IN_SEL 0x0000001f
+#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V 0x1f
+#define GPIO_FUNC48_IN_SEL_S 0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
+
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG49_IN_SEL (BIT(6))
+#define GPIO_SIG49_IN_SEL_M (BIT(6))
+#define GPIO_SIG49_IN_SEL_V 0x1
+#define GPIO_SIG49_IN_SEL_S 6
+
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC49_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_V 0x1
+#define GPIO_FUNC49_IN_INV_SEL_S 5
+
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC49_IN_SEL 0x0000001f
+#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V 0x1f
+#define GPIO_FUNC49_IN_SEL_S 0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
+
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG50_IN_SEL (BIT(6))
+#define GPIO_SIG50_IN_SEL_M (BIT(6))
+#define GPIO_SIG50_IN_SEL_V 0x1
+#define GPIO_SIG50_IN_SEL_S 6
+
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC50_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_V 0x1
+#define GPIO_FUNC50_IN_INV_SEL_S 5
+
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC50_IN_SEL 0x0000001f
+#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V 0x1f
+#define GPIO_FUNC50_IN_SEL_S 0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
+
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG51_IN_SEL (BIT(6))
+#define GPIO_SIG51_IN_SEL_M (BIT(6))
+#define GPIO_SIG51_IN_SEL_V 0x1
+#define GPIO_SIG51_IN_SEL_S 6
+
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC51_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_V 0x1
+#define GPIO_FUNC51_IN_INV_SEL_S 5
+
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC51_IN_SEL 0x0000001f
+#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V 0x1f
+#define GPIO_FUNC51_IN_SEL_S 0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
+
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG52_IN_SEL (BIT(6))
+#define GPIO_SIG52_IN_SEL_M (BIT(6))
+#define GPIO_SIG52_IN_SEL_V 0x1
+#define GPIO_SIG52_IN_SEL_S 6
+
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC52_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_V 0x1
+#define GPIO_FUNC52_IN_INV_SEL_S 5
+
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC52_IN_SEL 0x0000001f
+#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V 0x1f
+#define GPIO_FUNC52_IN_SEL_S 0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
+
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG53_IN_SEL (BIT(6))
+#define GPIO_SIG53_IN_SEL_M (BIT(6))
+#define GPIO_SIG53_IN_SEL_V 0x1
+#define GPIO_SIG53_IN_SEL_S 6
+
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC53_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_V 0x1
+#define GPIO_FUNC53_IN_INV_SEL_S 5
+
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC53_IN_SEL 0x0000001f
+#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V 0x1f
+#define GPIO_FUNC53_IN_SEL_S 0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
+
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG54_IN_SEL (BIT(6))
+#define GPIO_SIG54_IN_SEL_M (BIT(6))
+#define GPIO_SIG54_IN_SEL_V 0x1
+#define GPIO_SIG54_IN_SEL_S 6
+
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC54_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_V 0x1
+#define GPIO_FUNC54_IN_INV_SEL_S 5
+
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC54_IN_SEL 0x0000001f
+#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V 0x1f
+#define GPIO_FUNC54_IN_SEL_S 0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
+
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG55_IN_SEL (BIT(6))
+#define GPIO_SIG55_IN_SEL_M (BIT(6))
+#define GPIO_SIG55_IN_SEL_V 0x1
+#define GPIO_SIG55_IN_SEL_S 6
+
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC55_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_V 0x1
+#define GPIO_FUNC55_IN_INV_SEL_S 5
+
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC55_IN_SEL 0x0000001f
+#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V 0x1f
+#define GPIO_FUNC55_IN_SEL_S 0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
+
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG56_IN_SEL (BIT(6))
+#define GPIO_SIG56_IN_SEL_M (BIT(6))
+#define GPIO_SIG56_IN_SEL_V 0x1
+#define GPIO_SIG56_IN_SEL_S 6
+
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC56_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_V 0x1
+#define GPIO_FUNC56_IN_INV_SEL_S 5
+
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC56_IN_SEL 0x0000001f
+#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V 0x1f
+#define GPIO_FUNC56_IN_SEL_S 0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
+
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG57_IN_SEL (BIT(6))
+#define GPIO_SIG57_IN_SEL_M (BIT(6))
+#define GPIO_SIG57_IN_SEL_V 0x1
+#define GPIO_SIG57_IN_SEL_S 6
+
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC57_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_V 0x1
+#define GPIO_FUNC57_IN_INV_SEL_S 5
+
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC57_IN_SEL 0x0000001f
+#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V 0x1f
+#define GPIO_FUNC57_IN_SEL_S 0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
+
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG58_IN_SEL (BIT(6))
+#define GPIO_SIG58_IN_SEL_M (BIT(6))
+#define GPIO_SIG58_IN_SEL_V 0x1
+#define GPIO_SIG58_IN_SEL_S 6
+
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC58_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_V 0x1
+#define GPIO_FUNC58_IN_INV_SEL_S 5
+
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC58_IN_SEL 0x0000001f
+#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V 0x1f
+#define GPIO_FUNC58_IN_SEL_S 0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
+
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG59_IN_SEL (BIT(6))
+#define GPIO_SIG59_IN_SEL_M (BIT(6))
+#define GPIO_SIG59_IN_SEL_V 0x1
+#define GPIO_SIG59_IN_SEL_S 6
+
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC59_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_V 0x1
+#define GPIO_FUNC59_IN_INV_SEL_S 5
+
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC59_IN_SEL 0x0000001f
+#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V 0x1f
+#define GPIO_FUNC59_IN_SEL_S 0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
+
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG60_IN_SEL (BIT(6))
+#define GPIO_SIG60_IN_SEL_M (BIT(6))
+#define GPIO_SIG60_IN_SEL_V 0x1
+#define GPIO_SIG60_IN_SEL_S 6
+
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC60_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_V 0x1
+#define GPIO_FUNC60_IN_INV_SEL_S 5
+
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC60_IN_SEL 0x0000001f
+#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V 0x1f
+#define GPIO_FUNC60_IN_SEL_S 0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
+
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG61_IN_SEL (BIT(6))
+#define GPIO_SIG61_IN_SEL_M (BIT(6))
+#define GPIO_SIG61_IN_SEL_V 0x1
+#define GPIO_SIG61_IN_SEL_S 6
+
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC61_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_V 0x1
+#define GPIO_FUNC61_IN_INV_SEL_S 5
+
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC61_IN_SEL 0x0000001f
+#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V 0x1f
+#define GPIO_FUNC61_IN_SEL_S 0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
+
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG62_IN_SEL (BIT(6))
+#define GPIO_SIG62_IN_SEL_M (BIT(6))
+#define GPIO_SIG62_IN_SEL_V 0x1
+#define GPIO_SIG62_IN_SEL_S 6
+
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC62_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_V 0x1
+#define GPIO_FUNC62_IN_INV_SEL_S 5
+
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC62_IN_SEL 0x0000001f
+#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V 0x1f
+#define GPIO_FUNC62_IN_SEL_S 0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
+
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG63_IN_SEL (BIT(6))
+#define GPIO_SIG63_IN_SEL_M (BIT(6))
+#define GPIO_SIG63_IN_SEL_V 0x1
+#define GPIO_SIG63_IN_SEL_S 6
+
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC63_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_V 0x1
+#define GPIO_FUNC63_IN_INV_SEL_S 5
+
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC63_IN_SEL 0x0000001f
+#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V 0x1f
+#define GPIO_FUNC63_IN_SEL_S 0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
+
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG64_IN_SEL (BIT(6))
+#define GPIO_SIG64_IN_SEL_M (BIT(6))
+#define GPIO_SIG64_IN_SEL_V 0x1
+#define GPIO_SIG64_IN_SEL_S 6
+
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC64_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_V 0x1
+#define GPIO_FUNC64_IN_INV_SEL_S 5
+
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC64_IN_SEL 0x0000001f
+#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V 0x1f
+#define GPIO_FUNC64_IN_SEL_S 0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
+
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG65_IN_SEL (BIT(6))
+#define GPIO_SIG65_IN_SEL_M (BIT(6))
+#define GPIO_SIG65_IN_SEL_V 0x1
+#define GPIO_SIG65_IN_SEL_S 6
+
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC65_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_V 0x1
+#define GPIO_FUNC65_IN_INV_SEL_S 5
+
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC65_IN_SEL 0x0000001f
+#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V 0x1f
+#define GPIO_FUNC65_IN_SEL_S 0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
+
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG66_IN_SEL (BIT(6))
+#define GPIO_SIG66_IN_SEL_M (BIT(6))
+#define GPIO_SIG66_IN_SEL_V 0x1
+#define GPIO_SIG66_IN_SEL_S 6
+
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC66_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_V 0x1
+#define GPIO_FUNC66_IN_INV_SEL_S 5
+
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC66_IN_SEL 0x0000001f
+#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V 0x1f
+#define GPIO_FUNC66_IN_SEL_S 0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
+
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG67_IN_SEL (BIT(6))
+#define GPIO_SIG67_IN_SEL_M (BIT(6))
+#define GPIO_SIG67_IN_SEL_V 0x1
+#define GPIO_SIG67_IN_SEL_S 6
+
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC67_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_V 0x1
+#define GPIO_FUNC67_IN_INV_SEL_S 5
+
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC67_IN_SEL 0x0000001f
+#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V 0x1f
+#define GPIO_FUNC67_IN_SEL_S 0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264)
+
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG68_IN_SEL (BIT(6))
+#define GPIO_SIG68_IN_SEL_M (BIT(6))
+#define GPIO_SIG68_IN_SEL_V 0x1
+#define GPIO_SIG68_IN_SEL_S 6
+
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC68_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_V 0x1
+#define GPIO_FUNC68_IN_INV_SEL_S 5
+
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC68_IN_SEL 0x0000001f
+#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V 0x1f
+#define GPIO_FUNC68_IN_SEL_S 0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
+
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG69_IN_SEL (BIT(6))
+#define GPIO_SIG69_IN_SEL_M (BIT(6))
+#define GPIO_SIG69_IN_SEL_V 0x1
+#define GPIO_SIG69_IN_SEL_S 6
+
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC69_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_V 0x1
+#define GPIO_FUNC69_IN_INV_SEL_S 5
+
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC69_IN_SEL 0x0000001f
+#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V 0x1f
+#define GPIO_FUNC69_IN_SEL_S 0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
+
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG70_IN_SEL (BIT(6))
+#define GPIO_SIG70_IN_SEL_M (BIT(6))
+#define GPIO_SIG70_IN_SEL_V 0x1
+#define GPIO_SIG70_IN_SEL_S 6
+
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC70_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_V 0x1
+#define GPIO_FUNC70_IN_INV_SEL_S 5
+
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC70_IN_SEL 0x0000001f
+#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V 0x1f
+#define GPIO_FUNC70_IN_SEL_S 0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
+
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG71_IN_SEL (BIT(6))
+#define GPIO_SIG71_IN_SEL_M (BIT(6))
+#define GPIO_SIG71_IN_SEL_V 0x1
+#define GPIO_SIG71_IN_SEL_S 6
+
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC71_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_V 0x1
+#define GPIO_FUNC71_IN_INV_SEL_S 5
+
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC71_IN_SEL 0x0000001f
+#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V 0x1f
+#define GPIO_FUNC71_IN_SEL_S 0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
+
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG72_IN_SEL (BIT(6))
+#define GPIO_SIG72_IN_SEL_M (BIT(6))
+#define GPIO_SIG72_IN_SEL_V 0x1
+#define GPIO_SIG72_IN_SEL_S 6
+
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC72_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_V 0x1
+#define GPIO_FUNC72_IN_INV_SEL_S 5
+
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC72_IN_SEL 0x0000001f
+#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V 0x1f
+#define GPIO_FUNC72_IN_SEL_S 0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278)
+
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG73_IN_SEL (BIT(6))
+#define GPIO_SIG73_IN_SEL_M (BIT(6))
+#define GPIO_SIG73_IN_SEL_V 0x1
+#define GPIO_SIG73_IN_SEL_S 6
+
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC73_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_V 0x1
+#define GPIO_FUNC73_IN_INV_SEL_S 5
+
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC73_IN_SEL 0x0000001f
+#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V 0x1f
+#define GPIO_FUNC73_IN_SEL_S 0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c)
+
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG74_IN_SEL (BIT(6))
+#define GPIO_SIG74_IN_SEL_M (BIT(6))
+#define GPIO_SIG74_IN_SEL_V 0x1
+#define GPIO_SIG74_IN_SEL_S 6
+
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC74_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_V 0x1
+#define GPIO_FUNC74_IN_INV_SEL_S 5
+
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC74_IN_SEL 0x0000001f
+#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V 0x1f
+#define GPIO_FUNC74_IN_SEL_S 0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
+
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG75_IN_SEL (BIT(6))
+#define GPIO_SIG75_IN_SEL_M (BIT(6))
+#define GPIO_SIG75_IN_SEL_V 0x1
+#define GPIO_SIG75_IN_SEL_S 6
+
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC75_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_V 0x1
+#define GPIO_FUNC75_IN_INV_SEL_S 5
+
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC75_IN_SEL 0x0000001f
+#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V 0x1f
+#define GPIO_FUNC75_IN_SEL_S 0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
+
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG76_IN_SEL (BIT(6))
+#define GPIO_SIG76_IN_SEL_M (BIT(6))
+#define GPIO_SIG76_IN_SEL_V 0x1
+#define GPIO_SIG76_IN_SEL_S 6
+
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC76_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_V 0x1
+#define GPIO_FUNC76_IN_INV_SEL_S 5
+
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC76_IN_SEL 0x0000001f
+#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V 0x1f
+#define GPIO_FUNC76_IN_SEL_S 0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
+
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG77_IN_SEL (BIT(6))
+#define GPIO_SIG77_IN_SEL_M (BIT(6))
+#define GPIO_SIG77_IN_SEL_V 0x1
+#define GPIO_SIG77_IN_SEL_S 6
+
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC77_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_V 0x1
+#define GPIO_FUNC77_IN_INV_SEL_S 5
+
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC77_IN_SEL 0x0000001f
+#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V 0x1f
+#define GPIO_FUNC77_IN_SEL_S 0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
+
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG78_IN_SEL (BIT(6))
+#define GPIO_SIG78_IN_SEL_M (BIT(6))
+#define GPIO_SIG78_IN_SEL_V 0x1
+#define GPIO_SIG78_IN_SEL_S 6
+
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC78_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_V 0x1
+#define GPIO_FUNC78_IN_INV_SEL_S 5
+
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC78_IN_SEL 0x0000001f
+#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V 0x1f
+#define GPIO_FUNC78_IN_SEL_S 0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
+
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG79_IN_SEL (BIT(6))
+#define GPIO_SIG79_IN_SEL_M (BIT(6))
+#define GPIO_SIG79_IN_SEL_V 0x1
+#define GPIO_SIG79_IN_SEL_S 6
+
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC79_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_V 0x1
+#define GPIO_FUNC79_IN_INV_SEL_S 5
+
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC79_IN_SEL 0x0000001f
+#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V 0x1f
+#define GPIO_FUNC79_IN_SEL_S 0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294)
+
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG80_IN_SEL (BIT(6))
+#define GPIO_SIG80_IN_SEL_M (BIT(6))
+#define GPIO_SIG80_IN_SEL_V 0x1
+#define GPIO_SIG80_IN_SEL_S 6
+
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC80_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_V 0x1
+#define GPIO_FUNC80_IN_INV_SEL_S 5
+
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC80_IN_SEL 0x0000001f
+#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V 0x1f
+#define GPIO_FUNC80_IN_SEL_S 0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
+
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG81_IN_SEL (BIT(6))
+#define GPIO_SIG81_IN_SEL_M (BIT(6))
+#define GPIO_SIG81_IN_SEL_V 0x1
+#define GPIO_SIG81_IN_SEL_S 6
+
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC81_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_V 0x1
+#define GPIO_FUNC81_IN_INV_SEL_S 5
+
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC81_IN_SEL 0x0000001f
+#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V 0x1f
+#define GPIO_FUNC81_IN_SEL_S 0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c)
+
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG82_IN_SEL (BIT(6))
+#define GPIO_SIG82_IN_SEL_M (BIT(6))
+#define GPIO_SIG82_IN_SEL_V 0x1
+#define GPIO_SIG82_IN_SEL_S 6
+
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC82_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_V 0x1
+#define GPIO_FUNC82_IN_INV_SEL_S 5
+
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC82_IN_SEL 0x0000001f
+#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V 0x1f
+#define GPIO_FUNC82_IN_SEL_S 0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0)
+
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG83_IN_SEL (BIT(6))
+#define GPIO_SIG83_IN_SEL_M (BIT(6))
+#define GPIO_SIG83_IN_SEL_V 0x1
+#define GPIO_SIG83_IN_SEL_S 6
+
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC83_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_V 0x1
+#define GPIO_FUNC83_IN_INV_SEL_S 5
+
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC83_IN_SEL 0x0000001f
+#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V 0x1f
+#define GPIO_FUNC83_IN_SEL_S 0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
+
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG84_IN_SEL (BIT(6))
+#define GPIO_SIG84_IN_SEL_M (BIT(6))
+#define GPIO_SIG84_IN_SEL_V 0x1
+#define GPIO_SIG84_IN_SEL_S 6
+
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC84_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_V 0x1
+#define GPIO_FUNC84_IN_INV_SEL_S 5
+
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC84_IN_SEL 0x0000001f
+#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V 0x1f
+#define GPIO_FUNC84_IN_SEL_S 0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8)
+
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG85_IN_SEL (BIT(6))
+#define GPIO_SIG85_IN_SEL_M (BIT(6))
+#define GPIO_SIG85_IN_SEL_V 0x1
+#define GPIO_SIG85_IN_SEL_S 6
+
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC85_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_V 0x1
+#define GPIO_FUNC85_IN_INV_SEL_S 5
+
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC85_IN_SEL 0x0000001f
+#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V 0x1f
+#define GPIO_FUNC85_IN_SEL_S 0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac)
+
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG86_IN_SEL (BIT(6))
+#define GPIO_SIG86_IN_SEL_M (BIT(6))
+#define GPIO_SIG86_IN_SEL_V 0x1
+#define GPIO_SIG86_IN_SEL_S 6
+
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC86_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_V 0x1
+#define GPIO_FUNC86_IN_INV_SEL_S 5
+
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC86_IN_SEL 0x0000001f
+#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V 0x1f
+#define GPIO_FUNC86_IN_SEL_S 0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
+
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG87_IN_SEL (BIT(6))
+#define GPIO_SIG87_IN_SEL_M (BIT(6))
+#define GPIO_SIG87_IN_SEL_V 0x1
+#define GPIO_SIG87_IN_SEL_S 6
+
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC87_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_V 0x1
+#define GPIO_FUNC87_IN_INV_SEL_S 5
+
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC87_IN_SEL 0x0000001f
+#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V 0x1f
+#define GPIO_FUNC87_IN_SEL_S 0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4)
+
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG88_IN_SEL (BIT(6))
+#define GPIO_SIG88_IN_SEL_M (BIT(6))
+#define GPIO_SIG88_IN_SEL_V 0x1
+#define GPIO_SIG88_IN_SEL_S 6
+
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC88_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_V 0x1
+#define GPIO_FUNC88_IN_INV_SEL_S 5
+
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC88_IN_SEL 0x0000001f
+#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V 0x1f
+#define GPIO_FUNC88_IN_SEL_S 0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8)
+
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG89_IN_SEL (BIT(6))
+#define GPIO_SIG89_IN_SEL_M (BIT(6))
+#define GPIO_SIG89_IN_SEL_V 0x1
+#define GPIO_SIG89_IN_SEL_S 6
+
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC89_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_V 0x1
+#define GPIO_FUNC89_IN_INV_SEL_S 5
+
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC89_IN_SEL 0x0000001f
+#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V 0x1f
+#define GPIO_FUNC89_IN_SEL_S 0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
+
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG90_IN_SEL (BIT(6))
+#define GPIO_SIG90_IN_SEL_M (BIT(6))
+#define GPIO_SIG90_IN_SEL_V 0x1
+#define GPIO_SIG90_IN_SEL_S 6
+
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC90_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_V 0x1
+#define GPIO_FUNC90_IN_INV_SEL_S 5
+
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC90_IN_SEL 0x0000001f
+#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V 0x1f
+#define GPIO_FUNC90_IN_SEL_S 0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
+
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG91_IN_SEL (BIT(6))
+#define GPIO_SIG91_IN_SEL_M (BIT(6))
+#define GPIO_SIG91_IN_SEL_V 0x1
+#define GPIO_SIG91_IN_SEL_S 6
+
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC91_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_V 0x1
+#define GPIO_FUNC91_IN_INV_SEL_S 5
+
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC91_IN_SEL 0x0000001f
+#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V 0x1f
+#define GPIO_FUNC91_IN_SEL_S 0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG92_IN_SEL (BIT(6))
+#define GPIO_SIG92_IN_SEL_M (BIT(6))
+#define GPIO_SIG92_IN_SEL_V 0x1
+#define GPIO_SIG92_IN_SEL_S 6
+
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC92_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_V 0x1
+#define GPIO_FUNC92_IN_INV_SEL_S 5
+
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC92_IN_SEL 0x0000001f
+#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V 0x1f
+#define GPIO_FUNC92_IN_SEL_S 0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
+
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG93_IN_SEL (BIT(6))
+#define GPIO_SIG93_IN_SEL_M (BIT(6))
+#define GPIO_SIG93_IN_SEL_V 0x1
+#define GPIO_SIG93_IN_SEL_S 6
+
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC93_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_V 0x1
+#define GPIO_FUNC93_IN_INV_SEL_S 5
+
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC93_IN_SEL 0x0000001f
+#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V 0x1f
+#define GPIO_FUNC93_IN_SEL_S 0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
+
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG94_IN_SEL (BIT(6))
+#define GPIO_SIG94_IN_SEL_M (BIT(6))
+#define GPIO_SIG94_IN_SEL_V 0x1
+#define GPIO_SIG94_IN_SEL_S 6
+
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC94_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_V 0x1
+#define GPIO_FUNC94_IN_INV_SEL_S 5
+
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC94_IN_SEL 0x0000001f
+#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V 0x1f
+#define GPIO_FUNC94_IN_SEL_S 0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
+
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG95_IN_SEL (BIT(6))
+#define GPIO_SIG95_IN_SEL_M (BIT(6))
+#define GPIO_SIG95_IN_SEL_V 0x1
+#define GPIO_SIG95_IN_SEL_S 6
+
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC95_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_V 0x1
+#define GPIO_FUNC95_IN_INV_SEL_S 5
+
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC95_IN_SEL 0x0000001f
+#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V 0x1f
+#define GPIO_FUNC95_IN_SEL_S 0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
+
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG96_IN_SEL (BIT(6))
+#define GPIO_SIG96_IN_SEL_M (BIT(6))
+#define GPIO_SIG96_IN_SEL_V 0x1
+#define GPIO_SIG96_IN_SEL_S 6
+
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC96_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_V 0x1
+#define GPIO_FUNC96_IN_INV_SEL_S 5
+
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC96_IN_SEL 0x0000001f
+#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V 0x1f
+#define GPIO_FUNC96_IN_SEL_S 0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
+
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG97_IN_SEL (BIT(6))
+#define GPIO_SIG97_IN_SEL_M (BIT(6))
+#define GPIO_SIG97_IN_SEL_V 0x1
+#define GPIO_SIG97_IN_SEL_S 6
+
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC97_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_V 0x1
+#define GPIO_FUNC97_IN_INV_SEL_S 5
+
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC97_IN_SEL 0x0000001f
+#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V 0x1f
+#define GPIO_FUNC97_IN_SEL_S 0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG98_IN_SEL (BIT(6))
+#define GPIO_SIG98_IN_SEL_M (BIT(6))
+#define GPIO_SIG98_IN_SEL_V 0x1
+#define GPIO_SIG98_IN_SEL_S 6
+
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC98_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_V 0x1
+#define GPIO_FUNC98_IN_INV_SEL_S 5
+
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC98_IN_SEL 0x0000001f
+#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V 0x1f
+#define GPIO_FUNC98_IN_SEL_S 0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG99_IN_SEL (BIT(6))
+#define GPIO_SIG99_IN_SEL_M (BIT(6))
+#define GPIO_SIG99_IN_SEL_V 0x1
+#define GPIO_SIG99_IN_SEL_S 6
+
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC99_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_V 0x1
+#define GPIO_FUNC99_IN_INV_SEL_S 5
+
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC99_IN_SEL 0x0000001f
+#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V 0x1f
+#define GPIO_FUNC99_IN_SEL_S 0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG100_IN_SEL (BIT(6))
+#define GPIO_SIG100_IN_SEL_M (BIT(6))
+#define GPIO_SIG100_IN_SEL_V 0x1
+#define GPIO_SIG100_IN_SEL_S 6
+
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC100_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_V 0x1
+#define GPIO_FUNC100_IN_INV_SEL_S 5
+
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC100_IN_SEL 0x0000001f
+#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V 0x1f
+#define GPIO_FUNC100_IN_SEL_S 0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG101_IN_SEL (BIT(6))
+#define GPIO_SIG101_IN_SEL_M (BIT(6))
+#define GPIO_SIG101_IN_SEL_V 0x1
+#define GPIO_SIG101_IN_SEL_S 6
+
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC101_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_V 0x1
+#define GPIO_FUNC101_IN_INV_SEL_S 5
+
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC101_IN_SEL 0x0000001f
+#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V 0x1f
+#define GPIO_FUNC101_IN_SEL_S 0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG102_IN_SEL (BIT(6))
+#define GPIO_SIG102_IN_SEL_M (BIT(6))
+#define GPIO_SIG102_IN_SEL_V 0x1
+#define GPIO_SIG102_IN_SEL_S 6
+
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC102_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_V 0x1
+#define GPIO_FUNC102_IN_INV_SEL_S 5
+
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC102_IN_SEL 0x0000001f
+#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V 0x1f
+#define GPIO_FUNC102_IN_SEL_S 0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG103_IN_SEL (BIT(6))
+#define GPIO_SIG103_IN_SEL_M (BIT(6))
+#define GPIO_SIG103_IN_SEL_V 0x1
+#define GPIO_SIG103_IN_SEL_S 6
+
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC103_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_V 0x1
+#define GPIO_FUNC103_IN_INV_SEL_S 5
+
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC103_IN_SEL 0x0000001f
+#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V 0x1f
+#define GPIO_FUNC103_IN_SEL_S 0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG104_IN_SEL (BIT(6))
+#define GPIO_SIG104_IN_SEL_M (BIT(6))
+#define GPIO_SIG104_IN_SEL_V 0x1
+#define GPIO_SIG104_IN_SEL_S 6
+
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC104_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_V 0x1
+#define GPIO_FUNC104_IN_INV_SEL_S 5
+
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC104_IN_SEL 0x0000001f
+#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V 0x1f
+#define GPIO_FUNC104_IN_SEL_S 0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG105_IN_SEL (BIT(6))
+#define GPIO_SIG105_IN_SEL_M (BIT(6))
+#define GPIO_SIG105_IN_SEL_V 0x1
+#define GPIO_SIG105_IN_SEL_S 6
+
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC105_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_V 0x1
+#define GPIO_FUNC105_IN_INV_SEL_S 5
+
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC105_IN_SEL 0x0000001f
+#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V 0x1f
+#define GPIO_FUNC105_IN_SEL_S 0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG106_IN_SEL (BIT(6))
+#define GPIO_SIG106_IN_SEL_M (BIT(6))
+#define GPIO_SIG106_IN_SEL_V 0x1
+#define GPIO_SIG106_IN_SEL_S 6
+
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC106_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_V 0x1
+#define GPIO_FUNC106_IN_INV_SEL_S 5
+
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC106_IN_SEL 0x0000001f
+#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V 0x1f
+#define GPIO_FUNC106_IN_SEL_S 0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG107_IN_SEL (BIT(6))
+#define GPIO_SIG107_IN_SEL_M (BIT(6))
+#define GPIO_SIG107_IN_SEL_V 0x1
+#define GPIO_SIG107_IN_SEL_S 6
+
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC107_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_V 0x1
+#define GPIO_FUNC107_IN_INV_SEL_S 5
+
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC107_IN_SEL 0x0000001f
+#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V 0x1f
+#define GPIO_FUNC107_IN_SEL_S 0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG108_IN_SEL (BIT(6))
+#define GPIO_SIG108_IN_SEL_M (BIT(6))
+#define GPIO_SIG108_IN_SEL_V 0x1
+#define GPIO_SIG108_IN_SEL_S 6
+
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC108_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_V 0x1
+#define GPIO_FUNC108_IN_INV_SEL_S 5
+
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC108_IN_SEL 0x0000001f
+#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V 0x1f
+#define GPIO_FUNC108_IN_SEL_S 0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG109_IN_SEL (BIT(6))
+#define GPIO_SIG109_IN_SEL_M (BIT(6))
+#define GPIO_SIG109_IN_SEL_V 0x1
+#define GPIO_SIG109_IN_SEL_S 6
+
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC109_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_V 0x1
+#define GPIO_FUNC109_IN_INV_SEL_S 5
+
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC109_IN_SEL 0x0000001f
+#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V 0x1f
+#define GPIO_FUNC109_IN_SEL_S 0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG110_IN_SEL (BIT(6))
+#define GPIO_SIG110_IN_SEL_M (BIT(6))
+#define GPIO_SIG110_IN_SEL_V 0x1
+#define GPIO_SIG110_IN_SEL_S 6
+
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC110_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_V 0x1
+#define GPIO_FUNC110_IN_INV_SEL_S 5
+
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC110_IN_SEL 0x0000001f
+#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V 0x1f
+#define GPIO_FUNC110_IN_SEL_S 0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG111_IN_SEL (BIT(6))
+#define GPIO_SIG111_IN_SEL_M (BIT(6))
+#define GPIO_SIG111_IN_SEL_V 0x1
+#define GPIO_SIG111_IN_SEL_S 6
+
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC111_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_V 0x1
+#define GPIO_FUNC111_IN_INV_SEL_S 5
+
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC111_IN_SEL 0x0000001f
+#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V 0x1f
+#define GPIO_FUNC111_IN_SEL_S 0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
+
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG112_IN_SEL (BIT(6))
+#define GPIO_SIG112_IN_SEL_M (BIT(6))
+#define GPIO_SIG112_IN_SEL_V 0x1
+#define GPIO_SIG112_IN_SEL_S 6
+
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC112_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_V 0x1
+#define GPIO_FUNC112_IN_INV_SEL_S 5
+
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC112_IN_SEL 0x0000001f
+#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V 0x1f
+#define GPIO_FUNC112_IN_SEL_S 0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
+
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG113_IN_SEL (BIT(6))
+#define GPIO_SIG113_IN_SEL_M (BIT(6))
+#define GPIO_SIG113_IN_SEL_V 0x1
+#define GPIO_SIG113_IN_SEL_S 6
+
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC113_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_V 0x1
+#define GPIO_FUNC113_IN_INV_SEL_S 5
+
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC113_IN_SEL 0x0000001f
+#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V 0x1f
+#define GPIO_FUNC113_IN_SEL_S 0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG114_IN_SEL (BIT(6))
+#define GPIO_SIG114_IN_SEL_M (BIT(6))
+#define GPIO_SIG114_IN_SEL_V 0x1
+#define GPIO_SIG114_IN_SEL_S 6
+
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC114_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_V 0x1
+#define GPIO_FUNC114_IN_INV_SEL_S 5
+
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC114_IN_SEL 0x0000001f
+#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V 0x1f
+#define GPIO_FUNC114_IN_SEL_S 0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG115_IN_SEL (BIT(6))
+#define GPIO_SIG115_IN_SEL_M (BIT(6))
+#define GPIO_SIG115_IN_SEL_V 0x1
+#define GPIO_SIG115_IN_SEL_S 6
+
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC115_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_V 0x1
+#define GPIO_FUNC115_IN_INV_SEL_S 5
+
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC115_IN_SEL 0x0000001f
+#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V 0x1f
+#define GPIO_FUNC115_IN_SEL_S 0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324)
+
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG116_IN_SEL (BIT(6))
+#define GPIO_SIG116_IN_SEL_M (BIT(6))
+#define GPIO_SIG116_IN_SEL_V 0x1
+#define GPIO_SIG116_IN_SEL_S 6
+
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC116_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_V 0x1
+#define GPIO_FUNC116_IN_INV_SEL_S 5
+
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC116_IN_SEL 0x0000001f
+#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V 0x1f
+#define GPIO_FUNC116_IN_SEL_S 0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328)
+
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG117_IN_SEL (BIT(6))
+#define GPIO_SIG117_IN_SEL_M (BIT(6))
+#define GPIO_SIG117_IN_SEL_V 0x1
+#define GPIO_SIG117_IN_SEL_S 6
+
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC117_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_V 0x1
+#define GPIO_FUNC117_IN_INV_SEL_S 5
+
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC117_IN_SEL 0x0000001f
+#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V 0x1f
+#define GPIO_FUNC117_IN_SEL_S 0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG118_IN_SEL (BIT(6))
+#define GPIO_SIG118_IN_SEL_M (BIT(6))
+#define GPIO_SIG118_IN_SEL_V 0x1
+#define GPIO_SIG118_IN_SEL_S 6
+
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC118_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_V 0x1
+#define GPIO_FUNC118_IN_INV_SEL_S 5
+
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC118_IN_SEL 0x0000001f
+#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V 0x1f
+#define GPIO_FUNC118_IN_SEL_S 0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG119_IN_SEL (BIT(6))
+#define GPIO_SIG119_IN_SEL_M (BIT(6))
+#define GPIO_SIG119_IN_SEL_V 0x1
+#define GPIO_SIG119_IN_SEL_S 6
+
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC119_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_V 0x1
+#define GPIO_FUNC119_IN_INV_SEL_S 5
+
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC119_IN_SEL 0x0000001f
+#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V 0x1f
+#define GPIO_FUNC119_IN_SEL_S 0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
+
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG120_IN_SEL (BIT(6))
+#define GPIO_SIG120_IN_SEL_M (BIT(6))
+#define GPIO_SIG120_IN_SEL_V 0x1
+#define GPIO_SIG120_IN_SEL_S 6
+
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC120_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_V 0x1
+#define GPIO_FUNC120_IN_INV_SEL_S 5
+
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC120_IN_SEL 0x0000001f
+#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V 0x1f
+#define GPIO_FUNC120_IN_SEL_S 0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
+
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG121_IN_SEL (BIT(6))
+#define GPIO_SIG121_IN_SEL_M (BIT(6))
+#define GPIO_SIG121_IN_SEL_V 0x1
+#define GPIO_SIG121_IN_SEL_S 6
+
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC121_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_V 0x1
+#define GPIO_FUNC121_IN_INV_SEL_S 5
+
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC121_IN_SEL 0x0000001f
+#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V 0x1f
+#define GPIO_FUNC121_IN_SEL_S 0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
+
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG122_IN_SEL (BIT(6))
+#define GPIO_SIG122_IN_SEL_M (BIT(6))
+#define GPIO_SIG122_IN_SEL_V 0x1
+#define GPIO_SIG122_IN_SEL_S 6
+
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC122_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_V 0x1
+#define GPIO_FUNC122_IN_INV_SEL_S 5
+
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC122_IN_SEL 0x0000001f
+#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V 0x1f
+#define GPIO_FUNC122_IN_SEL_S 0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
+
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG123_IN_SEL (BIT(6))
+#define GPIO_SIG123_IN_SEL_M (BIT(6))
+#define GPIO_SIG123_IN_SEL_V 0x1
+#define GPIO_SIG123_IN_SEL_S 6
+
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC123_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_V 0x1
+#define GPIO_FUNC123_IN_INV_SEL_S 5
+
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC123_IN_SEL 0x0000001f
+#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V 0x1f
+#define GPIO_FUNC123_IN_SEL_S 0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
+
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG124_IN_SEL (BIT(6))
+#define GPIO_SIG124_IN_SEL_M (BIT(6))
+#define GPIO_SIG124_IN_SEL_V 0x1
+#define GPIO_SIG124_IN_SEL_S 6
+
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC124_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_V 0x1
+#define GPIO_FUNC124_IN_INV_SEL_S 5
+
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+#define GPIO_FUNC124_IN_SEL 0x0000001f
+#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V 0x1f
+#define GPIO_FUNC124_IN_SEL_S 0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348)
+
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG125_IN_SEL (BIT(6))
+#define GPIO_SIG125_IN_SEL_M (BIT(6))
+#define GPIO_SIG125_IN_SEL_V 0x1
+#define GPIO_SIG125_IN_SEL_S 6
+
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC125_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_V 0x1
+#define GPIO_FUNC125_IN_INV_SEL_S 5
+
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC125_IN_SEL 0x0000001f
+#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V 0x1f
+#define GPIO_FUNC125_IN_SEL_S 0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c)
+
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG126_IN_SEL (BIT(6))
+#define GPIO_SIG126_IN_SEL_M (BIT(6))
+#define GPIO_SIG126_IN_SEL_V 0x1
+#define GPIO_SIG126_IN_SEL_S 6
+
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC126_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_V 0x1
+#define GPIO_FUNC126_IN_INV_SEL_S 5
+
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC126_IN_SEL 0x0000001f
+#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V 0x1f
+#define GPIO_FUNC126_IN_SEL_S 0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+
+#define GPIO_SIG127_IN_SEL (BIT(6))
+#define GPIO_SIG127_IN_SEL_M (BIT(6))
+#define GPIO_SIG127_IN_SEL_V 0x1
+#define GPIO_SIG127_IN_SEL_S 6
+
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+
+#define GPIO_FUNC127_IN_INV_SEL (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_V 0x1
+#define GPIO_FUNC127_IN_INV_SEL_S 5
+
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+
+#define GPIO_FUNC127_IN_SEL 0x0000001f
+#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V 0x1f
+#define GPIO_FUNC127_IN_SEL_S 0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC0_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC0_OEN_SEL (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_V 0x1
+#define GPIO_FUNC0_OEN_SEL_S 9
+
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC0_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC0_OUT_SEL 0x000000ff
+#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V 0xff
+#define GPIO_FUNC0_OUT_SEL_S 0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC1_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC1_OEN_SEL (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_V 0x1
+#define GPIO_FUNC1_OEN_SEL_S 9
+
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC1_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC1_OUT_SEL 0x000000ff
+#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V 0xff
+#define GPIO_FUNC1_OUT_SEL_S 0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC2_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC2_OEN_SEL (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_V 0x1
+#define GPIO_FUNC2_OEN_SEL_S 9
+
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC2_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC2_OUT_SEL 0x000000ff
+#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V 0xff
+#define GPIO_FUNC2_OUT_SEL_S 0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC3_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC3_OEN_SEL (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_V 0x1
+#define GPIO_FUNC3_OEN_SEL_S 9
+
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC3_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC3_OUT_SEL 0x000000ff
+#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V 0xff
+#define GPIO_FUNC3_OUT_SEL_S 0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC4_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC4_OEN_SEL (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_V 0x1
+#define GPIO_FUNC4_OEN_SEL_S 9
+
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC4_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC4_OUT_SEL 0x000000ff
+#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V 0xff
+#define GPIO_FUNC4_OUT_SEL_S 0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
+
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC5_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC5_OEN_SEL (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_V 0x1
+#define GPIO_FUNC5_OEN_SEL_S 9
+
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC5_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC5_OUT_SEL 0x000000ff
+#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V 0xff
+#define GPIO_FUNC5_OUT_SEL_S 0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC6_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC6_OEN_SEL (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_V 0x1
+#define GPIO_FUNC6_OEN_SEL_S 9
+
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC6_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC6_OUT_SEL 0x000000ff
+#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V 0xff
+#define GPIO_FUNC6_OUT_SEL_S 0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC7_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC7_OEN_SEL (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_V 0x1
+#define GPIO_FUNC7_OEN_SEL_S 9
+
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC7_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC7_OUT_SEL 0x000000ff
+#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V 0xff
+#define GPIO_FUNC7_OUT_SEL_S 0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC8_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC8_OEN_SEL (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_V 0x1
+#define GPIO_FUNC8_OEN_SEL_S 9
+
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC8_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC8_OUT_SEL 0x000000ff
+#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V 0xff
+#define GPIO_FUNC8_OUT_SEL_S 0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC9_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC9_OEN_SEL (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_V 0x1
+#define GPIO_FUNC9_OEN_SEL_S 9
+
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC9_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC9_OUT_SEL 0x000000ff
+#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V 0xff
+#define GPIO_FUNC9_OUT_SEL_S 0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC10_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC10_OEN_SEL (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_V 0x1
+#define GPIO_FUNC10_OEN_SEL_S 9
+
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC10_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC10_OUT_SEL 0x000000ff
+#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V 0xff
+#define GPIO_FUNC10_OUT_SEL_S 0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC11_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC11_OEN_SEL (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_V 0x1
+#define GPIO_FUNC11_OEN_SEL_S 9
+
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC11_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC11_OUT_SEL 0x000000ff
+#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V 0xff
+#define GPIO_FUNC11_OUT_SEL_S 0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC12_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC12_OEN_SEL (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_V 0x1
+#define GPIO_FUNC12_OEN_SEL_S 9
+
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC12_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC12_OUT_SEL 0x000000ff
+#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V 0xff
+#define GPIO_FUNC12_OUT_SEL_S 0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC13_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC13_OEN_SEL (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_V 0x1
+#define GPIO_FUNC13_OEN_SEL_S 9
+
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC13_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC13_OUT_SEL 0x000000ff
+#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V 0xff
+#define GPIO_FUNC13_OUT_SEL_S 0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC14_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC14_OEN_SEL (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_V 0x1
+#define GPIO_FUNC14_OEN_SEL_S 9
+
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC14_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC14_OUT_SEL 0x000000ff
+#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V 0xff
+#define GPIO_FUNC14_OUT_SEL_S 0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC15_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC15_OEN_SEL (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_V 0x1
+#define GPIO_FUNC15_OEN_SEL_S 9
+
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC15_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC15_OUT_SEL 0x000000ff
+#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V 0xff
+#define GPIO_FUNC15_OUT_SEL_S 0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC16_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC16_OEN_SEL (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_V 0x1
+#define GPIO_FUNC16_OEN_SEL_S 9
+
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC16_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC16_OUT_SEL 0x000000ff
+#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V 0xff
+#define GPIO_FUNC16_OUT_SEL_S 0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC17_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC17_OEN_SEL (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_V 0x1
+#define GPIO_FUNC17_OEN_SEL_S 9
+
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC17_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC17_OUT_SEL 0x000000ff
+#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V 0xff
+#define GPIO_FUNC17_OUT_SEL_S 0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC18_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC18_OEN_SEL (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_V 0x1
+#define GPIO_FUNC18_OEN_SEL_S 9
+
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC18_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC18_OUT_SEL 0x000000ff
+#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V 0xff
+#define GPIO_FUNC18_OUT_SEL_S 0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC19_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC19_OEN_SEL (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_V 0x1
+#define GPIO_FUNC19_OEN_SEL_S 9
+
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC19_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC19_OUT_SEL 0x000000ff
+#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V 0xff
+#define GPIO_FUNC19_OUT_SEL_S 0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC20_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC20_OEN_SEL (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_V 0x1
+#define GPIO_FUNC20_OEN_SEL_S 9
+
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC20_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC20_OUT_SEL 0x000000ff
+#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V 0xff
+#define GPIO_FUNC20_OUT_SEL_S 0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC21_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC21_OEN_SEL (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_V 0x1
+#define GPIO_FUNC21_OEN_SEL_S 9
+
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC21_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC21_OUT_SEL 0x000000ff
+#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V 0xff
+#define GPIO_FUNC21_OUT_SEL_S 0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC22_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC22_OEN_SEL (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_V 0x1
+#define GPIO_FUNC22_OEN_SEL_S 9
+
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC22_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC22_OUT_SEL 0x000000ff
+#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V 0xff
+#define GPIO_FUNC22_OUT_SEL_S 0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC23_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC23_OEN_SEL (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_V 0x1
+#define GPIO_FUNC23_OEN_SEL_S 9
+
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC23_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC23_OUT_SEL 0x000000ff
+#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V 0xff
+#define GPIO_FUNC23_OUT_SEL_S 0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC24_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC24_OEN_SEL (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_V 0x1
+#define GPIO_FUNC24_OEN_SEL_S 9
+
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC24_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC24_OUT_SEL 0x000000ff
+#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V 0xff
+#define GPIO_FUNC24_OUT_SEL_S 0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
+
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+
+#define GPIO_FUNC25_OEN_INV_SEL (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_V 0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S 10
+
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+
+#define GPIO_FUNC25_OEN_SEL (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_M (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_V 0x1
+#define GPIO_FUNC25_OEN_SEL_S 9
+
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+
+#define GPIO_FUNC25_OUT_INV_SEL (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_V 0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S 8
+
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+
+#define GPIO_FUNC25_OUT_SEL 0x000000ff
+#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V 0xff
+#define GPIO_FUNC25_OUT_SEL_S 0
+
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c)
+
+/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+
+#define GPIO_CLK_EN (BIT(0))
+#define GPIO_CLK_EN_M (BIT(0))
+#define GPIO_CLK_EN_V 0x1
+#define GPIO_CLK_EN_S 0
+
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc)
+
+/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */
+
+#define GPIO_DATE 0x0fffffff
+#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S))
+#define GPIO_DATE_V 0xfffffff
+#define GPIO_DATE_S 0
+
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h
new file mode 100644
index 0000000..56a3beb
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h
@@ -0,0 +1,196 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H
+#define __ARCH_RISCV_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
+#define SPIQ_IN_IDX 0
+#define SPIQ_OUT_IDX 0
+#define SPID_IN_IDX 1
+#define SPID_OUT_IDX 1
+#define SPIHD_IN_IDX 2
+#define SPIHD_OUT_IDX 2
+#define SPIWP_IN_IDX 3
+#define SPIWP_OUT_IDX 3
+#define SPICLK_OUT_IDX 4
+#define SPICS0_OUT_IDX 5
+#define U0RXD_IN_IDX 6
+#define U0TXD_OUT_IDX 6
+#define U0CTS_IN_IDX 7
+#define U0RTS_OUT_IDX 7
+#define U0DSR_IN_IDX 8
+#define U0DTR_OUT_IDX 8
+#define U1RXD_IN_IDX 9
+#define U1TXD_OUT_IDX 9
+#define U1CTS_IN_IDX 10
+#define U1RTS_OUT_IDX 10
+#define U1DSR_IN_IDX 11
+#define U1DTR_OUT_IDX 11
+#define I2S_MCLK_IN_IDX 12
+#define I2S_MCLK_OUT_IDX 12
+#define I2SO_BCK_IN_IDX 13
+#define I2SO_BCK_OUT_IDX 13
+#define I2SO_WS_IN_IDX 14
+#define I2SO_WS_OUT_IDX 14
+#define I2SI_SD_IN_IDX 15
+#define I2SO_SD_OUT_IDX 15
+#define I2SI_BCK_IN_IDX 16
+#define I2SI_BCK_OUT_IDX 16
+#define I2SI_WS_IN_IDX 17
+#define I2SI_WS_OUT_IDX 17
+#define GPIO_BT_PRIORITY_IDX 18
+#define GPIO_WLAN_PRIO_IDX 18
+#define GPIO_BT_ACTIVE_IDX 19
+#define GPIO_WLAN_ACTIVE_IDX 19
+#define BB_DIAG0_IDX 20
+#define BB_DIAG1_IDX 21
+#define BB_DIAG2_IDX 22
+#define BB_DIAG3_IDX 23
+#define BB_DIAG4_IDX 24
+#define BB_DIAG5_IDX 25
+#define BB_DIAG6_IDX 26
+#define BB_DIAG7_IDX 27
+#define BB_DIAG8_IDX 28
+#define BB_DIAG9_IDX 29
+#define BB_DIAG10_IDX 30
+#define BB_DIAG11_IDX 31
+#define BB_DIAG12_IDX 32
+#define BB_DIAG13_IDX 33
+#define BB_DIAG14_IDX 34
+#define BB_DIAG15_IDX 35
+#define BB_DIAG16_IDX 36
+#define BB_DIAG17_IDX 37
+#define BB_DIAG18_IDX 38
+#define BB_DIAG19_IDX 39
+#define USB_EXTPHY_VP_IDX 40
+#define USB_EXTPHY_OEN_IDX 40
+#define USB_EXTPHY_VM_IDX 41
+#define USB_EXTPHY_SPEED_IDX 41
+#define USB_EXTPHY_RCV_IDX 42
+#define USB_EXTPHY_VPO_IDX 42
+#define USB_EXTPHY_VMO_IDX 43
+#define USB_EXTPHY_SUSPND_IDX 44
+#define EXT_ADC_START_IDX 45
+#define LEDC_LS_SIG_OUT0_IDX 45
+#define LEDC_LS_SIG_OUT1_IDX 46
+#define LEDC_LS_SIG_OUT2_IDX 47
+#define LEDC_LS_SIG_OUT3_IDX 48
+#define LEDC_LS_SIG_OUT4_IDX 49
+#define LEDC_LS_SIG_OUT5_IDX 50
+#define RMT_SIG_IN0_IDX 51
+#define RMT_SIG_OUT0_IDX 51
+#define RMT_SIG_IN1_IDX 52
+#define RMT_SIG_OUT1_IDX 52
+#define I2CEXT0_SCL_IN_IDX 53
+#define I2CEXT0_SCL_OUT_IDX 53
+#define I2CEXT0_SDA_IN_IDX 54
+#define I2CEXT0_SDA_OUT_IDX 54
+#define GPIO_SD0_OUT_IDX 55
+#define GPIO_SD1_OUT_IDX 56
+#define GPIO_SD2_OUT_IDX 57
+#define GPIO_SD3_OUT_IDX 58
+#define FSPICLK_IN_IDX 63
+#define FSPICLK_OUT_IDX 63
+#define FSPIQ_IN_IDX 64
+#define FSPIQ_OUT_IDX 64
+#define FSPID_IN_IDX 65
+#define FSPID_OUT_IDX 65
+#define FSPIHD_IN_IDX 66
+#define FSPIHD_OUT_IDX 66
+#define FSPIWP_IN_IDX 67
+#define FSPIWP_OUT_IDX 67
+#define FSPICS0_IN_IDX 68
+#define FSPICS0_OUT_IDX 68
+#define FSPICS1_OUT_IDX 69
+#define FSPICS2_OUT_IDX 70
+#define FSPICS3_OUT_IDX 71
+#define FSPICS4_OUT_IDX 72
+#define FSPICS5_OUT_IDX 73
+#define TWAI_RX_IDX 74
+#define TWAI_TX_IDX 74
+#define TWAI_BUS_OFF_ON_IDX 75
+#define TWAI_CLKOUT_IDX 76
+#define PCMFSYNC_IN_IDX 77
+#define BT_AUDIO0_IRQ_IDX 77
+#define PCMCLK_IN_IDX 78
+#define BT_AUDIO1_IRQ_IDX 78
+#define PCMDIN_IDX 79
+#define BT_AUDIO2_IRQ_IDX 79
+#define RW_WAKEUP_REQ_IDX 80
+#define BLE_AUDIO0_IRQ_IDX 80
+#define BLE_AUDIO1_IRQ_IDX 81
+#define BLE_AUDIO2_IRQ_IDX 82
+#define PCMFSYNC_OUT_IDX 83
+#define PCMCLK_OUT_IDX 84
+#define PCMDOUT_IDX 85
+#define BLE_AUDIO_SYNC0_P_IDX 86
+#define BLE_AUDIO_SYNC1_P_IDX 87
+#define BLE_AUDIO_SYNC2_P_IDX 88
+#define ANT_SEL0_IDX 89
+#define ANT_SEL1_IDX 90
+#define ANT_SEL2_IDX 91
+#define ANT_SEL3_IDX 92
+#define ANT_SEL4_IDX 93
+#define ANT_SEL5_IDX 94
+#define ANT_SEL6_IDX 95
+#define ANT_SEL7_IDX 96
+#define SIG_IN_FUNC_97_IDX 97
+#define SIG_IN_FUNC97_IDX 97
+#define SIG_IN_FUNC_98_IDX 98
+#define SIG_IN_FUNC98_IDX 98
+#define SIG_IN_FUNC_99_IDX 99
+#define SIG_IN_FUNC99_IDX 99
+#define SIG_IN_FUNC_100_IDX 100
+#define SIG_IN_FUNC100_IDX 100
+#define SYNCERR_IDX 101
+#define SYNCFOUND_FLAG_IDX 102
+#define EVT_CNTL_IMMEDIATE_ABORT_IDX 103
+#define LINKLBL_IDX 104
+#define DATA_EN_IDX 105
+#define DATA_IDX 106
+#define PKT_TX_ON_IDX 107
+#define PKT_RX_ON_IDX 108
+#define RW_TX_ON_IDX 109
+#define RW_RX_ON_IDX 110
+#define EVT_REQ_P_IDX 111
+#define EVT_STOP_P_IDX 112
+#define BT_MODE_ON_IDX 113
+#define GPIO_LC_DIAG0_IDX 114
+#define GPIO_LC_DIAG1_IDX 115
+#define GPIO_LC_DIAG2_IDX 116
+#define CH_IDX_IDX 117
+#define RX_WINDOW_IDX 118
+#define UPDATE_RX_IDX 119
+#define RX_STATUS_IDX 120
+#define CLK_GPIO_IDX 121
+#define NBT_BLE_IDX 122
+#define CLK_OUT_OUT1_IDX 123
+#define CLK_OUT_OUT2_IDX 124
+#define CLK_OUT_OUT3_IDX 125
+#define SPICS1_OUT_IDX 126
+#define SIG_GPIO_OUT_IDX 128
+#define GPIO_MAP_DATE_IDX 0x2006130
+
+#endif /* __ARCH_RISCV_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
new file mode 100644
index 0000000..9d057b7
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
@@ -0,0 +1,310 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32_HARDWARE_ESP32_IOMUX_H
+#define __ARCH_RISCV_SRC_ESP32_HARDWARE_ESP32_IOMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c3_soc.h"
+
+/****************************************************************************
+ * Pre-preprocessor Definitions
+ ****************************************************************************/
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+
+/* Output enable in sleep mode */
+
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+
+/* Pin used for wakeup from sleep */
+
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+
+/* Pulldown enable in sleep mode */
+
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+
+/* Pullup enable in sleep mode */
+
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+
+/* Input enable in sleep mode */
+
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+
+/* Drive strength in sleep mode */
+
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+
+/* Pulldown enable */
+
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+
+/* Pullup enable */
+
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+
+/* Input enable */
+
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+
+/* Drive strength */
+
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+
+/* Function select (possible values are defined for each pin as
+ * FUNC_pinname_function below)
+ */
+
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
+
+#define FUNC_GPIO_GPIO 1
+#define PIN_FUNC_GPIO 1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define U0RXD_GPIO_NUM 20
+#define U0TXD_GPIO_NUM 21
+
+#define SPI_HD_GPIO_NUM 12
+#define SPI_WP_GPIO_NUM 13
+#define SPI_CS0_GPIO_NUM 14
+#define SPI_CLK_GPIO_NUM 15
+#define SPI_D_GPIO_NUM 16
+#define SPI_Q_GPIO_NUM 17
+
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+
+#define MAX_RTC_GPIO_NUM 0
+#define MAX_PAD_GPIO_NUM 22
+#define MAX_GPIO_NUM 22
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL (REG_IO_MUX_BASE + 0x00)
+#define PAD_POWER_SEL BIT(15)
+#define PAD_POWER_SEL_V 0x1
+#define PAD_POWER_SEL_M BIT(15)
+#define PAD_POWER_SEL_S 15
+
+#define PAD_POWER_SWITCH_DELAY 0x7
+#define PAD_POWER_SWITCH_DELAY_V 0x7
+#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S 12
+
+#define CLK_OUT3 0xf
+#define CLK_OUT3_V CLK_OUT3
+#define CLK_OUT3_S 8
+#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2 0xf
+#define CLK_OUT2_V CLK_OUT2
+#define CLK_OUT2_S 4
+#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1 0xf
+#define CLK_OUT1_V CLK_OUT1
+#define CLK_OUT1_S 0
+#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x04)
+#define FUNC_XTAL_32K_P_GPIO0 1
+#define FUNC_XTAL_32K_P_GPIO0_0 0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x08)
+#define FUNC_XTAL_32K_N_GPIO1 1
+#define FUNC_XTAL_32K_N_GPIO1_0 0
+
+#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0c)
+#define FUNC_GPIO2_FSPIQ 2
+#define FUNC_GPIO2_GPIO2 1
+#define FUNC_GPIO2_GPIO2_0 0
+
+#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3 1
+#define FUNC_GPIO3_GPIO3_0 0
+
+#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTMS_FSPIHD 2
+#define FUNC_MTMS_GPIO4 1
+#define FUNC_MTMS_MTMS 0
+
+#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPIWP 2
+#define FUNC_MTDI_GPIO5 1
+#define FUNC_MTDI_MTDI 0
+
+#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1c)
+#define FUNC_MTCK_FSPICLK 2
+#define FUNC_MTCK_GPIO6 1
+#define FUNC_MTCK_MTCK 0
+
+#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
+#define FUNC_MTDO_FSPID 2
+#define FUNC_MTDO_GPIO7 1
+#define FUNC_MTDO_MTDO 0
+
+#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8 1
+#define FUNC_GPIO8_GPIO8_0 0
+
+#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9 1
+#define FUNC_GPIO9_GPIO9_0 0
+
+#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2c)
+#define FUNC_GPIO10_FSPICS0 2
+#define FUNC_GPIO10_GPIO10 1
+#define FUNC_GPIO10_GPIO10_0 0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x30)
+#define FUNC_VDD_SPI_GPIO11 1
+#define FUNC_VDD_SPI_GPIO11_0 0
+
+#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x34)
+#define FUNC_SPIHD_GPIO12 1
+#define FUNC_SPIHD_SPIHD 0
+
+#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x38)
+#define FUNC_SPIWP_GPIO13 1
+#define FUNC_SPIWP_SPIWP 0
+
+#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x3c)
+#define FUNC_SPICS0_GPIO14 1
+#define FUNC_SPICS0_SPICS0 0
+
+#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICLK_GPIO15 1
+#define FUNC_SPICLK_SPICLK 0
+
+#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPID_GPIO16 1
+#define FUNC_SPID_SPID 0
+
+#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIQ_GPIO17 1
+#define FUNC_SPIQ_SPIQ 0
+
+#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE + 0x4c)
+#define FUNC_GPIO18_GPIO18 1
+#define FUNC_GPIO18_GPIO18_0 0
+
+#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE + 0x50)
+#define FUNC_GPIO19_GPIO19 1
+#define FUNC_GPIO19_GPIO19_0 0
+
+#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x54)
+#define FUNC_U0RXD_GPIO20 1
+#define FUNC_U0RXD_U0RXD 0
+
+#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x58)
+#define FUNC_U0TXD_GPIO21 1
+#define FUNC_U0TXD_U0TXD 0
+
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE_S 0
+#define IO_MUX_DATE_VERSION 0x2006050
+
+#endif
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
index 787f2cd..23dc3cb 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt
@@ -77,6 +77,17 @@ Configurations
Basic configuration to run the NuttShell (nsh).
+ gpio
+ ____
+
+ This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs.
+ At the nsh, we can turn the outputs on and off with the following:
+ nsh> gpio -o 1 /dev/gpout0
+ nsh> gpio -o 1 /dev/gpout1
+
+ nsh> gpio -o 0 /dev/gpout0
+ nsh> gpio -o 0 /dev/gpout1
+
Building and flashing
=====================
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig
new file mode 100644
index 0000000..a28b2fa
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig
@@ -0,0 +1,65 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c3-devkit"
+CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c3"
+CONFIG_ARCH_CHIP_ESP32C3=y
+CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEV_GPIO=y
+CONFIG_DEV_ZERO=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_EXAMPLES_GPIO=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_HELLO_STACKSIZE=1024
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INPUT=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MAX_TASKS=8
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_CD=y
+CONFIG_NSH_DISABLE_CP=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PTHREAD_STACK_DEFAULT=1536
+CONFIG_RAM_SIZE=16384
+CONFIG_RAM_START=0x80000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=12
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=1536
+CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
index f3a3be6..1d0432f 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h
@@ -29,5 +29,9 @@
#define BOARD_XTAL_FREQUENCY 40000000
+/* GPIO pins used by the GPIO Subsystem */
+
+#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */
+
#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
index 46aafc6..30f9273 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
@@ -30,6 +30,10 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += esp32c3_appinit.c
endif
+ifeq ($(CONFIG_DEV_GPIO),y)
+CSRCS += esp32c3_gpio.c
+endif
+
SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32c3.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
index 5e4d457..088ff6a 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
@@ -63,5 +63,14 @@
int esp32c3_bringup(void);
+/****************************************************************************
+ * Name: esp32c3_gpio_init
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_GPIO
+int esp32c3_gpio_init(void);
+#endif
+
+
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_SRC_ESP32C3_DEVKIT_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
index f6fbaa5..fdcd140 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
@@ -76,6 +76,15 @@ int esp32c3_bringup(void)
}
#endif
+#ifdef CONFIG_DEV_GPIO
+ ret = esp32c3_gpio_init();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret);
+ return ret;
+ }
+#endif
+
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
new file mode 100644
index 0000000..3844e9b
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c
@@ -0,0 +1,169 @@
+/****************************************************************************
+ * boards/risc-v/esp32c3-devkit/src/esp32c3_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/ioexpander/gpio.h>
+
+#include <arch/board/board.h>
+
+#include "esp32c3-devkit.h"
+#include "esp32c3_gpio.h"
+#include "hardware/esp32c3_gpio_sigmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Pin 1 and 2 are used for this example as GPIO outputs. */
+
+#define GPIO_OUT1 1
+#define GPIO_OUT2 2
+
+#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32c3gpio_dev_s
+{
+ struct gpio_dev_s gpio;
+ uint8_t id;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#if BOARD_NGPIOOUT > 0
+static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value);
+static int gpout_write(FAR struct gpio_dev_s *dev, bool value);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#if BOARD_NGPIOOUT > 0
+static const struct gpio_operations_s gpout_ops =
+{
+ .go_read = gpout_read,
+ .go_write = gpout_write,
+ .go_attach = NULL,
+ .go_enable = NULL,
+};
+
+/* This array maps the GPIO pins used as OUTPUT */
+
+static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] =
+{
+ GPIO_OUT1, GPIO_OUT2
+};
+
+static struct esp32c3gpio_dev_s g_gpout[BOARD_NGPIOOUT];
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpout_read
+ ****************************************************************************/
+
+#if BOARD_NGPIOOUT > 0
+static int gpout_read(FAR struct gpio_dev_s *dev, FAR bool *value)
+{
+ FAR struct esp32c3gpio_dev_s *esp32c3gpio =
+ (FAR struct esp32c3gpio_dev_s *)dev;
+
+ DEBUGASSERT(esp32c3gpio != NULL && value != NULL);
+ DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT);
+ gpioinfo("Reading...\n");
+
+ *value = esp32c3_gpioread(g_gpiooutputs[esp32c3gpio->id]);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: gpout_write
+ ****************************************************************************/
+
+static int gpout_write(FAR struct gpio_dev_s *dev, bool value)
+{
+ FAR struct esp32c3gpio_dev_s *esp32c3gpio =
+ (FAR struct esp32c3gpio_dev_s *)dev;
+
+ DEBUGASSERT(esp32c3gpio != NULL);
+ DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT);
+ gpioinfo("Writing %d\n", (int)value);
+
+ esp32c3_gpiowrite(g_gpiooutputs[esp32c3gpio->id], value);
+ return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_gpio_init
+ ****************************************************************************/
+
+int esp32c3_gpio_init(void)
+{
+ int i;
+ int pincount = 0;
+
+#if BOARD_NGPIOOUT > 0
+ for (i = 0; i < BOARD_NGPIOOUT; i++)
+ {
+ /* Setup and register the GPIO pin */
+
+ g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN;
+ g_gpout[i].gpio.gp_ops = &gpout_ops;
+ g_gpout[i].id = i;
+ gpio_pin_register(&g_gpout[i].gpio, pincount);
+
+ /* Configure the pins that will be used as output */
+
+ esp32c3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0);
+ esp32c3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1);
+ esp32c3_gpiowrite(g_gpiooutputs[i], 0);
+
+ pincount++;
+ }
+#endif
+
+ return OK;
+}
+#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */