You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/04/14 08:43:39 UTC
[incubator-nuttx] branch master updated (701bbaac74 -> c2b69cc2c9)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from 701bbaac74 sched/environ: Ensure tg_envp terminated by double '\0'
new 3d6ab5c804 RISC-V: Add SBI glue logic
new c2b69cc2c9 RISC-V: mtimer register via SBI when S-mode is in use
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/risc-v/src/common/riscv_internal.h | 7 +++
arch/risc-v/src/common/riscv_mtimer.c | 15 ++++++
arch/risc-v/src/common/supervisor/Make.defs | 2 +-
.../src/common/supervisor/riscv_sbi.c} | 62 ++++++++++++++--------
4 files changed, 63 insertions(+), 23 deletions(-)
copy arch/{xtensa/src/esp32s3/esp32s3_user.c => risc-v/src/common/supervisor/riscv_sbi.c} (72%)
[incubator-nuttx] 02/02: RISC-V: mtimer register via SBI when S-mode is in use
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit c2b69cc2c9a0a26da8d2d26e5d41f02cb6715e76
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Thu Apr 14 09:22:26 2022 +0300
RISC-V: mtimer register via SBI when S-mode is in use
Cannot access the memory mapped registers directly when the kernel
runs in S-mode, must forward the access to SBI.
---
arch/risc-v/src/common/riscv_mtimer.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/risc-v/src/common/riscv_mtimer.c b/arch/risc-v/src/common/riscv_mtimer.c
index 27ce9e4e41..c78919763e 100644
--- a/arch/risc-v/src/common/riscv_mtimer.c
+++ b/arch/risc-v/src/common/riscv_mtimer.c
@@ -80,6 +80,7 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
* Private Functions
****************************************************************************/
+#ifndef CONFIG_ARCH_USE_S_MODE
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
{
#ifdef CONFIG_ARCH_RV64
@@ -114,6 +115,20 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
__DMB();
}
+#else
+static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
+{
+ UNUSED(priv);
+ return riscv_sbi_get_time();
+}
+
+static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
+ uint64_t value)
+{
+ UNUSED(priv);
+ riscv_sbi_set_timer(value);
+}
+#endif
/****************************************************************************
* Name: riscv_mtimer_max_delay
[incubator-nuttx] 01/02: RISC-V: Add SBI glue logic
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3d6ab5c804d372d1f3e8f24a38982603d6426e16
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Thu Apr 14 08:58:29 2022 +0300
RISC-V: Add SBI glue logic
Currently only stubs for mtime handling added, with a gentle reminder
that the actual implementation is still missing.
---
arch/risc-v/src/common/riscv_internal.h | 7 +++
arch/risc-v/src/common/supervisor/Make.defs | 2 +-
arch/risc-v/src/common/supervisor/riscv_sbi.c | 89 +++++++++++++++++++++++++++
3 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index 627d834d86..a56be9416d 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -250,6 +250,13 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size);
int riscv_configured_pmp_regions(void);
int riscv_next_free_pmp_region(void);
+/* RISC-V SBI wrappers ******************************************************/
+
+#ifdef CONFIG_ARCH_USE_S_MODE
+void riscv_sbi_set_timer(uint64_t stime_value);
+uint64_t riscv_sbi_get_time(void);
+#endif
+
/* Power management *********************************************************/
#ifdef CONFIG_PM
diff --git a/arch/risc-v/src/common/supervisor/Make.defs b/arch/risc-v/src/common/supervisor/Make.defs
index e3125b0cef..62625c2368 100644
--- a/arch/risc-v/src/common/supervisor/Make.defs
+++ b/arch/risc-v/src/common/supervisor/Make.defs
@@ -22,7 +22,7 @@
CMN_ASRCS += riscv_dispatch_syscall.S
CMN_CSRCS += riscv_perform_syscall.c
-CMN_CSRCS += riscv_percpu.c
+CMN_CSRCS += riscv_percpu.c riscv_sbi.c
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)common$(DELIM)supervisor}
VPATH += common$(DELIM)supervisor
diff --git a/arch/risc-v/src/common/supervisor/riscv_sbi.c b/arch/risc-v/src/common/supervisor/riscv_sbi.c
new file mode 100644
index 0000000000..9694f69f64
--- /dev/null
+++ b/arch/risc-v/src/common/supervisor/riscv_sbi.c
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/risc-v/src/common/supervisor/riscv_sbi.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include <stdint.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_RV64
+static inline uint64_t rdtime(void)
+{
+ uint32_t hi;
+ uint32_t lo;
+
+ do
+ {
+ hi = READ_CSR(timeh);
+ lo = READ_CSR(time);
+ }
+ while (hi != READ_CSR(timeh));
+
+ return (((uint64_t) hi) << 32) | lo;
+}
+#else
+#define rdtime() READ_CSR(time)
+#endif /* CONFIG_ARCH_RV64 */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: riscv_sbi_set_timer
+ *
+ * Description:
+ * Set new compare match value for timer
+ *
+ * Input Parameters:
+ * stime_value - Value to set
+ *
+ ****************************************************************************/
+
+void riscv_sbi_set_timer(uint64_t stime_value)
+{
+#error "Missing functionality..."
+}
+
+/****************************************************************************
+ * Name: riscv_sbi_get_time
+ *
+ * Description:
+ * Get value of mtime
+ *
+ * Return:
+ * Value of mtime
+ *
+ ****************************************************************************/
+
+uint64_t riscv_sbi_get_time(void)
+{
+ return rdtime();
+}