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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/07/15 07:11:15 UTC
[nuttx] 02/06: armv7/8 cache: add up_get_xcache_size() support
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 22d1059c97f767f2c204725cd4d8bcd7a40373a7
Author: chenrun1 <ch...@xiaomi.com>
AuthorDate: Fri May 5 11:18:06 2023 +0800
armv7/8 cache: add up_get_xcache_size() support
Signed-off-by: chenrun1 <ch...@xiaomi.com>
---
arch/arm/src/armv7-a/arm_cache.c | 52 +++++++++++++++++++
arch/arm/src/armv7-a/arm_l2cc_pl310.c | 19 +++++++
arch/arm/src/armv7-a/l2cc.h | 17 +++++++
arch/arm/src/armv7-m/arm_cache.c | 95 +++++++++++++++++++++++++++++++++++
arch/arm/src/armv7-r/arm_cache.c | 52 +++++++++++++++++++
arch/arm/src/armv7-r/arm_l2cc_pl310.c | 19 +++++++
arch/arm/src/armv7-r/l2cc.h | 17 +++++++
arch/arm/src/armv8-m/arm_cache.c | 95 +++++++++++++++++++++++++++++++++++
include/nuttx/cache.h | 40 +++++++++++++++
9 files changed, 406 insertions(+)
diff --git a/arch/arm/src/armv7-a/arm_cache.c b/arch/arm/src/armv7-a/arm_cache.c
index e5120cb32f..545a05c1af 100644
--- a/arch/arm/src/armv7-a/arm_cache.c
+++ b/arch/arm/src/armv7-a/arm_cache.c
@@ -63,6 +63,32 @@ size_t up_get_icache_linesize(void)
return clsize;
}
+/****************************************************************************
+ * Name: up_get_icache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = MAX(cp15_icache_size(), l2cc_size());
+ }
+
+ return csize;
+}
+
/****************************************************************************
* Name: up_invalidate_icache_all
*
@@ -172,6 +198,32 @@ size_t up_get_dcache_linesize(void)
return clsize;
}
+/****************************************************************************
+ * Name: up_get_dcache_size
+ *
+ * Description:
+ * Get dcache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = MAX(cp15_dcache_size(), l2cc_size());
+ }
+
+ return csize;
+}
+
/****************************************************************************
* Name: up_invalidate_dcache
*
diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
index 5744091ee7..993cb2c30b 100644
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -415,6 +415,25 @@ uint32_t l2cc_linesize(void)
return PL310_CACHE_LINE_SIZE;
}
+/****************************************************************************
+ * Name: l2cc_size
+ *
+ * Description:
+ * Get L2CC-P310 L2 cache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * L2 cache size
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_size(void)
+{
+ return PL310_CACHE_SIZE;
+}
+
/****************************************************************************
* Name: l2cc_enable
*
diff --git a/arch/arm/src/armv7-a/l2cc.h b/arch/arm/src/armv7-a/l2cc.h
index e0d96974b8..368bc02c2c 100644
--- a/arch/arm/src/armv7-a/l2cc.h
+++ b/arch/arm/src/armv7-a/l2cc.h
@@ -86,6 +86,22 @@ void arm_l2ccinitialize(void);
uint32_t l2cc_linesize(void);
+/****************************************************************************
+ * Name: l2cc_size
+ *
+ * Description:
+ * Get L2CC-P310 L2 cache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * L2 cache size
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_size(void);
+
/****************************************************************************
* Name: l2cc_enable
*
@@ -245,6 +261,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
* compilation in one place.
*/
+# define l2cc_size() 0
# define l2cc_linesize() 0
# define l2cc_enable()
# define l2cc_disable()
diff --git a/arch/arm/src/armv7-m/arm_cache.c b/arch/arm/src/armv7-m/arm_cache.c
index 4588ea1e42..88bc5ac2b5 100644
--- a/arch/arm/src/armv7-m/arm_cache.c
+++ b/arch/arm/src/armv7-m/arm_cache.c
@@ -142,6 +142,49 @@ static size_t up_get_cache_linesize(bool icache)
return 1 << sshift;
}
+
+/****************************************************************************
+ * Name: up_get_cache_size
+ *
+ * Description:
+ * Get cache size
+ *
+ * Input Parameters:
+ * level - Difference between icache and dcache.
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+static size_t up_get_cache_size(bool icache)
+{
+ uint32_t ccsidr;
+ uint32_t csselr;
+ uint32_t sshift;
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t line;
+
+ csselr = getreg32(NVIC_CSSELR);
+
+ if (icache)
+ {
+ csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
+ }
+ else
+ {
+ csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
+ }
+
+ ccsidr = getreg32(NVIC_CCSIDR);
+ sets = CCSIDR_SETS(ccsidr) + 1;
+ ways = CCSIDR_WAYS(ccsidr) + 1;
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
+ line = 1 << sshift;
+
+ return sets * ways * line;
+}
#endif
/****************************************************************************
@@ -174,6 +217,32 @@ size_t up_get_icache_linesize(void)
return clsize;
}
+
+/****************************************************************************
+ * Name: up_get_icache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = up_get_cache_size(true);
+ }
+
+ return csize;
+}
#endif
/****************************************************************************
@@ -367,6 +436,32 @@ size_t up_get_dcache_linesize(void)
return clsize;
}
+
+/****************************************************************************
+ * Name: up_get_dcache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = up_get_cache_size(false);
+ }
+
+ return csize;
+}
#endif
/****************************************************************************
diff --git a/arch/arm/src/armv7-r/arm_cache.c b/arch/arm/src/armv7-r/arm_cache.c
index 323da0bce3..c626a34a87 100644
--- a/arch/arm/src/armv7-r/arm_cache.c
+++ b/arch/arm/src/armv7-r/arm_cache.c
@@ -63,6 +63,32 @@ size_t up_get_icache_linesize(void)
return clsize;
}
+/****************************************************************************
+ * Name: up_get_icache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = MAX(cp15_icache_size(), l2cc_size());
+ }
+
+ return csize;
+}
+
/****************************************************************************
* Name: up_invalidate_icache_all
*
@@ -172,6 +198,32 @@ size_t up_get_dcache_linesize(void)
return clsize;
}
+/****************************************************************************
+ * Name: up_get_dcache_size
+ *
+ * Description:
+ * Get dcache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = MAX(cp15_dcache_size(), l2cc_size());
+ }
+
+ return csize;
+}
+
/****************************************************************************
* Name: up_invalidate_dcache
*
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index bd5e5a54b7..ef381b3501 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -415,6 +415,25 @@ uint32_t l2cc_linesize(void)
return PL310_CACHE_LINE_SIZE;
}
+/****************************************************************************
+ * Name: l2cc_size
+ *
+ * Description:
+ * Get L2CC-P310 L2 cache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * L2 cache size
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_size(void)
+{
+ return PL310_CACHE_SIZE;
+}
+
/****************************************************************************
* Name: l2cc_enable
*
diff --git a/arch/arm/src/armv7-r/l2cc.h b/arch/arm/src/armv7-r/l2cc.h
index fa62baf3bf..916d1d8d87 100644
--- a/arch/arm/src/armv7-r/l2cc.h
+++ b/arch/arm/src/armv7-r/l2cc.h
@@ -86,6 +86,22 @@ void arm_l2ccinitialize(void);
uint32_t l2cc_linesize(void);
+/****************************************************************************
+ * Name: l2cc_size
+ *
+ * Description:
+ * Get L2CC-P310 L2 cache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * L2 cache size
+ *
+ ****************************************************************************/
+
+uint32_t l2cc_size(void);
+
/****************************************************************************
* Name: l2cc_enable
*
@@ -245,6 +261,7 @@ void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
* compilation in one place.
*/
+# define l2cc_size() 0
# define l2cc_linesize() 0
# define l2cc_enable()
# define l2cc_disable()
diff --git a/arch/arm/src/armv8-m/arm_cache.c b/arch/arm/src/armv8-m/arm_cache.c
index 4028f3d5a2..c4d0ec1ccc 100644
--- a/arch/arm/src/armv8-m/arm_cache.c
+++ b/arch/arm/src/armv8-m/arm_cache.c
@@ -144,6 +144,49 @@ static size_t up_get_cache_linesize(bool icache)
}
#endif
+/****************************************************************************
+ * Name: up_get_cache_size
+ *
+ * Description:
+ * Get cache size
+ *
+ * Input Parameters:
+ * level - Difference between icache and dcache.
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+static size_t up_get_cache_size(bool icache)
+{
+ uint32_t ccsidr;
+ uint32_t csselr;
+ uint32_t sshift;
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t line;
+
+ csselr = getreg32(NVIC_CSSELR);
+
+ if (icache)
+ {
+ csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_ICACHE;
+ }
+ else
+ {
+ csselr = (csselr & ~NVIC_CSSELR_IND) | NVIC_CSSELR_IND_DCACHE;
+ }
+
+ ccsidr = getreg32(NVIC_CCSIDR);
+ sets = CCSIDR_SETS(ccsidr) + 1;
+ ways = CCSIDR_WAYS(ccsidr) + 1;
+ sshift = CCSIDR_LSSHIFT(ccsidr) + 4; /* log2(cache-line-size-in-bytes) */
+ line = 1 << sshift;
+
+ return sets * ways * line;
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -174,6 +217,32 @@ size_t up_get_icache_linesize(void)
return clsize;
}
+
+/****************************************************************************
+ * Name: up_get_icache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_icache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = up_get_cache_size(true);
+ }
+
+ return csize;
+}
#endif
/****************************************************************************
@@ -367,6 +436,32 @@ size_t up_get_dcache_linesize(void)
return clsize;
}
+
+/****************************************************************************
+ * Name: up_get_dcache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+size_t up_get_dcache_size(void)
+{
+ static uint32_t csize;
+
+ if (csize == 0)
+ {
+ csize = up_get_cache_size(false);
+ }
+
+ return csize;
+}
#endif
/****************************************************************************
diff --git a/include/nuttx/cache.h b/include/nuttx/cache.h
index 7814165fd1..b978c01e7a 100644
--- a/include/nuttx/cache.h
+++ b/include/nuttx/cache.h
@@ -68,6 +68,26 @@ size_t up_get_icache_linesize(void);
# define up_get_icache_linesize() 0
#endif
+/****************************************************************************
+ * Name: up_get_icache_size
+ *
+ * Description:
+ * Get icache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_ICACHE
+size_t up_get_icache_size(void);
+#else
+# define up_get_icache_size() 0
+#endif
+
/****************************************************************************
* Name: up_enable_icache
*
@@ -237,6 +257,26 @@ size_t up_get_dcache_linesize(void);
# define up_get_dcache_linesize() 0
#endif
+/****************************************************************************
+ * Name: up_get_dcache_size
+ *
+ * Description:
+ * Get dcache size
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Cache size
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_DCACHE
+size_t up_get_dcache_size(void);
+#else
+# define up_get_dcache_size() 0
+#endif
+
/****************************************************************************
* Name: up_enable_dcache
*