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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2021/08/10 23:35:46 UTC

[GitHub] [incubator-nuttx] masayuki2009 edited a comment on pull request #4304: esp32: Re-organize the interrupt handling process to correctly handle the SMP case

masayuki2009 edited a comment on pull request #4304:
URL: https://github.com/apache/incubator-nuttx/pull/4304#issuecomment-896381697


   @Ouss4 
   
   According to the esp32_technical_reference_manual_el.pdf (version 4.5),
   it seems that we can enable/disable IRQ for peripherals with the Interrupt Matrix outside the dual LX6.
   
   If my understanding is correct, the feature is very similar to the GIC (Generic Interrupt Controller) for Cortex-A and PLIC (Platform Level Interrupt Controller) for RISC-V. In this case, we do not need such a remote IRQ handling logic which I implemented for cxd56xx. Instead, we can control the interrupt controller (i.e. the Interrupt Matrix for ESP32) directly.
   
   Unfortunately, cxd56xx does not have such an interrupt controller inside the processor.
   So I had to control the NVIC on each CPU.
   


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