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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/11/25 13:11:38 UTC
[incubator-nuttx] 01/35: arch/arm/src/efm32/efm32_timer.c: Appease
nxstyle
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 2e6c1bc8ad5d7353f7b2c4488e036c08203d71af
Author: YAMAMOTO Takashi <ya...@midokura.com>
AuthorDate: Wed Nov 25 14:32:57 2020 +0900
arch/arm/src/efm32/efm32_timer.c: Appease nxstyle
---
arch/arm/src/efm32/efm32_timer.c | 66 +++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 31 deletions(-)
diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c
index fd9b81d..1bdf8cf 100644
--- a/arch/arm/src/efm32/efm32_timer.c
+++ b/arch/arm/src/efm32/efm32_timer.c
@@ -92,15 +92,15 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
tmrinfo("%s:\n", msg);
tmrinfo(" CTRL: %04x STATUS: %04x IEN: %04x IF: %04x\n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
- getreg32(base + EFM32_TIMER_IF_OFFSET ));
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET),
+ getreg32(base + EFM32_TIMER_IF_OFFSET));
tmrinfo(" TOP: %04x TOPB: %04x CNT: %04x ROUTE: %04x\n",
- getreg32(base + EFM32_TIMER_TOP_OFFSET ),
- getreg32(base + EFM32_TIMER_TOPB_OFFSET ),
- getreg32(base + EFM32_TIMER_CNT_OFFSET ),
- getreg32(base + EFM32_TIMER_ROUTE_OFFSET ));
+ getreg32(base + EFM32_TIMER_TOP_OFFSET),
+ getreg32(base + EFM32_TIMER_TOPB_OFFSET),
+ getreg32(base + EFM32_TIMER_CNT_OFFSET),
+ getreg32(base + EFM32_TIMER_ROUTE_OFFSET));
for (i = 0; i < EFM32_TIMER_NCC; i++)
{
@@ -108,21 +108,21 @@ void efm32_timer_dumpregs(uintptr_t base, FAR const char *msg)
tmrinfo("CC%d => CTRL: %04x CCV: %04x CCVP: %04x CCVB: %04x\n",
i
- getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET ),
- getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET ));
+ getreg32(base_cc + EFM32_TIMER_CC_CTRL_OFFSET),
+ getreg32(base_cc + EFM32_TIMER_CC_CCV_OFFSET),
+ getreg32(base_cc + EFM32_TIMER_CC_CCVP_OFFSET),
+ getreg32(base_cc + EFM32_TIMER_CC_CCVB_OFFSET));
}
tmrinfo("DTCTRL: %04x DTTIME: %04x DTFC: %04x DTOGEN: %04x\n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
- getreg32(base + EFM32_TIMER_IF_OFFSET ));
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET),
+ getreg32(base + EFM32_TIMER_IF_OFFSET));
tmrinfo("DTFAULT: %04x DTFAULTC: %04x DTLOCK: %04x \n",
- getreg32(base + EFM32_TIMER_CTRL_OFFSET ),
- getreg32(base + EFM32_TIMER_STATUS_OFFSET ),
- getreg32(base + EFM32_TIMER_IEN_OFFSET ),
+ getreg32(base + EFM32_TIMER_CTRL_OFFSET),
+ getreg32(base + EFM32_TIMER_STATUS_OFFSET),
+ getreg32(base + EFM32_TIMER_IEN_OFFSET),
#endif
}
@@ -150,25 +150,28 @@ void efm32_timer_reset(uintptr_t base)
/* Reset timer register */
- putreg32(_TIMER_CTRL_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET );
- putreg32(_TIMER_IEN_RESETVALUE, base + EFM32_TIMER_STATUS_OFFSET );
- putreg32(_TIMER_IFC_MASK, base + EFM32_TIMER_IEN_OFFSET );
- putreg32(_TIMER_TOP_RESETVALUE, base + EFM32_TIMER_IF_OFFSET );
- putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET );
- putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET );
+ putreg32(_TIMER_CTRL_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET);
+ putreg32(_TIMER_IEN_RESETVALUE, base + EFM32_TIMER_STATUS_OFFSET);
+ putreg32(_TIMER_IFC_MASK, base + EFM32_TIMER_IEN_OFFSET);
+ putreg32(_TIMER_TOP_RESETVALUE, base + EFM32_TIMER_IF_OFFSET);
+ putreg32(_TIMER_TOPB_RESETVALUE, base + EFM32_TIMER_CTRL_OFFSET);
+ putreg32(_TIMER_CNT_RESETVALUE, base + EFM32_TIMER_CMD_OFFSET);
/* Do not reset route register, setting should be done independently
* (Note: ROUTE register may be locked by DTLOCK register.)
*/
- //putreg32(_TIMER_ROUTE_RESETVALUE, base + EFM32_TIMER_ROUTE_OFFSET );
+ /* putreg32(_TIMER_ROUTE_RESETVALUE, base + EFM32_TIMER_ROUTE_OFFSET); */
for (i = 0; i < EFM32_TIMER_NCC; i++)
{
uintptr_t base_cc = base + EFM32_TIMER_CC_OFFSET(i);
- putreg32(_TIMER_CC_CTRL_RESETVALUE, base_cc+EFM32_TIMER_CC_CTRL_OFFSET);
- putreg32(_TIMER_CC_CCV_RESETVALUE, base_cc+EFM32_TIMER_CC_CCV_OFFSET );
- putreg32(_TIMER_CC_CCVB_RESETVALUE, base_cc+EFM32_TIMER_CC_CCVB_OFFSET);
+ putreg32(_TIMER_CC_CTRL_RESETVALUE,
+ base_cc + EFM32_TIMER_CC_CTRL_OFFSET);
+ putreg32(_TIMER_CC_CCV_RESETVALUE,
+ base_cc + EFM32_TIMER_CC_CCV_OFFSET);
+ putreg32(_TIMER_CC_CCVB_RESETVALUE,
+ base_cc + EFM32_TIMER_CC_CCVB_OFFSET);
}
/* Reset dead time insertion module, no effect on timers without DTI */
@@ -181,7 +184,7 @@ void efm32_timer_reset(uintptr_t base)
putreg32(_TIMER_DTCTRL_RESETVALUE, base + EFM32_TIMER_DTCTRL_OFFSET);
putreg32(_TIMER_DTTIME_RESETVALUE, base + EFM32_TIMER_DTTIME_OFFSET);
putreg32(_TIMER_DTFC_RESETVALUE, base + EFM32_TIMER_DTFC_OFFSET);
- putreg32(_TIMER_DTOGEN_RESETVALUE,base + EFM32_TIMER_DTOGEN_OFFSET);
+ putreg32(_TIMER_DTOGEN_RESETVALUE, base + EFM32_TIMER_DTOGEN_OFFSET);
putreg32(_TIMER_DTFAULTC_MASK, base + EFM32_TIMER_DTFAULTC_OFFSET);
#endif
}
@@ -226,7 +229,8 @@ int efm32_timer_set_freq(uintptr_t base, uint32_t clk_freq, uint32_t freq)
reload = (clk_freq / prescaler / freq);
- tmrinfo("Source: %4xHz Div: %4x Reload: %4x \n", clk_freq, prescaler, reload);
+ tmrinfo("Source: %4xHz Div: %4x Reload: %4x \n", clk_freq, prescaler,
+ reload);
putreg32(reload, base + EFM32_TIMER_TOP_OFFSET);