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Posted to commits@mynewt.apache.org by ut...@apache.org on 2018/07/25 15:46:21 UTC
[mynewt-core] branch master updated (4685c8f -> 3b16576)
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from 4685c8f Merge pull request #1292 from wes3/batt_poll_fix
new de96e6e [STM32] Add syscfg's for HAL driver choice
new 3b16576 Fix identation
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/mcu/stm/stm32_common/src/hal_gpio.c | 72 +++++++++++-----------
hw/mcu/stm/stm32_common/src/hal_i2c.c | 10 +--
hw/mcu/stm/stm32_common/src/hal_uart.c | 14 ++---
.../stm/stm32_common/src/stm32_driver_mod_i2c_v1.c | 4 +-
.../stm/stm32_common/src/stm32_driver_mod_i2c_v2.c | 4 +-
hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c | 2 +-
hw/mcu/stm/stm32f1xx/syscfg.yml | 14 ++++-
hw/mcu/stm/stm32f3xx/syscfg.yml | 14 +++++
hw/mcu/stm/stm32f4xx/syscfg.yml | 14 ++++-
hw/mcu/stm/stm32f7xx/syscfg.yml | 14 +++++
hw/mcu/stm/stm32l1xx/syscfg.yml | 14 ++++-
hw/mcu/stm/stm32l4xx/syscfg.yml | 14 ++++-
12 files changed, 133 insertions(+), 57 deletions(-)
[mynewt-core] 01/02: [STM32] Add syscfg's for HAL driver choice
Posted by ut...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit de96e6e23f76137148f7745357ba74de8a43e8cb
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Wed Jul 18 11:12:16 2018 -0300
[STM32] Add syscfg's for HAL driver choice
---
hw/mcu/stm/stm32_common/src/hal_i2c.c | 10 +++++-----
hw/mcu/stm/stm32_common/src/hal_uart.c | 14 +++++++-------
hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c | 4 ++--
hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c | 4 ++--
hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c | 2 +-
hw/mcu/stm/stm32f1xx/syscfg.yml | 14 +++++++++++++-
hw/mcu/stm/stm32f3xx/syscfg.yml | 14 ++++++++++++++
hw/mcu/stm/stm32f4xx/syscfg.yml | 14 +++++++++++++-
hw/mcu/stm/stm32f7xx/syscfg.yml | 14 ++++++++++++++
hw/mcu/stm/stm32l1xx/syscfg.yml | 14 +++++++++++++-
hw/mcu/stm/stm32l4xx/syscfg.yml | 14 +++++++++++++-
11 files changed, 97 insertions(+), 21 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_i2c.c b/hw/mcu/stm/stm32_common/src/hal_i2c.c
index dc1896b..e59da38 100644
--- a/hw/mcu/stm/stm32_common/src/hal_i2c.c
+++ b/hw/mcu/stm/stm32_common/src/hal_i2c.c
@@ -71,7 +71,7 @@ static struct stm32_hal_i2c *hal_i2c_devs[HAL_I2C_MAX_DEVS] = {
#endif
};
-#if defined(STM32F1)
+#if MYNEWT_VAL(MCU_STM32F1)
static void
i2c_reset(I2C_HandleTypeDef *hi2c)
{
@@ -88,7 +88,7 @@ hal_i2c_init(uint8_t i2c_num, void *usercfg)
struct stm32_hal_i2c_cfg *cfg = (struct stm32_hal_i2c_cfg *)usercfg;
struct stm32_hal_i2c *dev;
I2C_InitTypeDef *init;
-#if defined(STM32F1)
+#if MYNEWT_VAL(MCU_STM32F1)
GPIO_InitTypeDef gpio;
#endif
int rc;
@@ -99,7 +99,7 @@ hal_i2c_init(uint8_t i2c_num, void *usercfg)
init = &dev->hid_handle.Init;
dev->hid_handle.Instance = cfg->hic_i2c;
-#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
+#if !MYNEWT_VAL(STM32_HAL_I2C_HAS_CLOCKSPEED)
init->Timing = cfg->hic_timingr;
#else
init->ClockSpeed = cfg->hic_speed;
@@ -116,7 +116,7 @@ hal_i2c_init(uint8_t i2c_num, void *usercfg)
* Configure GPIO pins for I2C.
* Enable clock routing for I2C.
*/
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
rc = hal_gpio_init_af(cfg->hic_pin_sda, cfg->hic_pin_af, HAL_GPIO_PULL_UP,
1);
if (rc) {
@@ -234,7 +234,7 @@ hal_i2c_master_probe(uint8_t i2c_num, uint8_t address, uint32_t timo)
rc = HAL_I2C_IsDeviceReady(&dev->hid_handle, address << 1, 1, timo);
-#if defined(STM32F1)
+#if MYNEWT_VAL(MCU_STM32F1)
if (rc == HAL_BUSY) {
i2c_reset(&dev->hid_handle);
}
diff --git a/hw/mcu/stm/stm32_common/src/hal_uart.c b/hw/mcu/stm/stm32_common/src/hal_uart.c
index 188ec17..9fcad07 100644
--- a/hw/mcu/stm/stm32_common/src/hal_uart.c
+++ b/hw/mcu/stm/stm32_common/src/hal_uart.c
@@ -58,7 +58,7 @@ static struct hal_uart_irq uart_irqs[4];
static struct hal_uart_irq uart_irqs[3];
#endif
-#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
+#if !MYNEWT_VAL(STM32_HAL_UART_HAS_SR)
# define STATUS(x) ((x)->ISR)
# define RXNE USART_ISR_RXNE
# define TXE USART_ISR_TXE
@@ -140,7 +140,7 @@ uart_irq_handler(int num)
}
regs->CR1 = cr1;
}
-#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
+#if !MYNEWT_VAL(STM32_HAL_UART_HAS_SR)
/* clear overrun */
if (isr & USART_ISR_ORE) {
regs->ICR |= USART_ICR_ORECF;
@@ -335,7 +335,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
struct hal_uart *u;
const struct stm32_uart_cfg *cfg;
uint32_t cr1, cr2, cr3;
-#if defined(STM32F1)
+#if MYNEWT_VAL(MCU_STM32F1)
GPIO_InitTypeDef gpio;
#endif
@@ -350,7 +350,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
cfg = u->u_cfg;
assert(cfg);
-#if defined(STM32F1)
+#if MYNEWT_VAL(MCU_STM32F1)
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -383,7 +383,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
cr3 = cfg->suc_uart->CR3;
cr1 &= ~(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_RE);
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
cr1 &= ~(USART_CR1_OVER8);
#endif
cr2 &= ~(USART_CR2_STOP);
@@ -441,7 +441,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
break;
}
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
cr1 |= (UART_MODE_RX | UART_MODE_TX | UART_OVERSAMPLING_16);
#else
cr1 |= (UART_MODE_TX_RX | UART_OVERSAMPLING_16);
@@ -449,7 +449,7 @@ hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
*cfg->suc_rcc_reg |= cfg->suc_rcc_dev;
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
hal_gpio_init_af(cfg->suc_pin_tx, cfg->suc_pin_af, 0, 0);
hal_gpio_init_af(cfg->suc_pin_rx, cfg->suc_pin_af, 0, 0);
if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
index 61335d3..83eee17 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
@@ -29,7 +29,7 @@
#include <mcu/stm32_hal.h>
#include <syscfg/syscfg.h>
-#if !MYNEWT_VAL(MCU_STM32F3) && !MYNEWT_VAL(MCU_STM32F7) && !MYNEWT_VAL(MCU_STM32L4)
+#if MYNEWT_VAL(STM32_HAL_I2C_HAS_CLOCKSPEED)
#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
@@ -852,6 +852,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_Custom(I2C_HandleTypeDef *hi2c,
}
}
-#endif /* !defined(STM32F3) && !defined(STM32F7) */
+#endif /* MYNEWT_VAL(STM32_HAL_I2C_HAS_CLOCKSPEED) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
index 134a64c..9671b8b 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
@@ -30,7 +30,7 @@
#include <mcu/stm32_hal.h>
#include <syscfg/syscfg.h>
-#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
+#if !MYNEWT_VAL(STM32_HAL_I2C_HAS_CLOCKSPEED)
#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
@@ -661,4 +661,4 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_Custom(I2C_HandleTypeDef *hi2c,
}
}
-#endif /* defined(STM32F3) || defined(STM32F7) */
+#endif /* !MYNEWT_VAL(STM32_HAL_I2C_HAS_CLOCKSPEED) */
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
index 9f54ee2..335e1ac 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
@@ -32,7 +32,7 @@
HAL_StatusTypeDef HAL_SPI_Slave_Queue_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-#define SPI_HAS_FIFO (MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4))
+#define SPI_HAS_FIFO MYNEWT_VAL(STM32_HAL_SPI_HAS_FIFO)
#if SPI_HAS_FIFO && (MYNEWT_VAL(SPI_0_SLAVE) || \
MYNEWT_VAL(SPI_1_SLAVE) || \
diff --git a/hw/mcu/stm/stm32f1xx/syscfg.yml b/hw/mcu/stm/stm32f1xx/syscfg.yml
index e59fc47..94af10a 100644
--- a/hw/mcu/stm/stm32f1xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f1xx/syscfg.yml
@@ -16,7 +16,7 @@
# under the License.
#
-# Package: hw/bsp/stm32l152discovery
+# Package: hw/mcu/stm/stm32f1xx
syscfg.defs:
MCU_FLASH_MIN_WRITE_SIZE:
@@ -29,6 +29,18 @@ syscfg.defs:
description: MCUs are of STM32F1xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI without FIFO
+ value: 0
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has a clock speed register
+ value: 1
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses SR register for status.
+ value: 1
+
I2C_0:
description: 'I2C (TWI) interface 0'
value: 0
diff --git a/hw/mcu/stm/stm32f3xx/syscfg.yml b/hw/mcu/stm/stm32f3xx/syscfg.yml
index 4ea70c8..5007f54 100644
--- a/hw/mcu/stm/stm32f3xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f3xx/syscfg.yml
@@ -16,6 +16,8 @@
# under the License.
#
+# Package: hw/mcu/stm/stm32f3xx
+
syscfg.defs:
MCU_FLASH_MIN_WRITE_SIZE:
description: >
@@ -27,6 +29,18 @@ syscfg.defs:
description: MCUs are of STM32F3xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI with FIFO
+ value: 1
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has no clock speed register (has TIMINGR)
+ value: 0
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses ISR register (not SR) for status.
+ value: 0
+
MCU_SYSCLK_PLL_HSI:
description: Configure PLL as sysclock driven by HSI.
value: 0
diff --git a/hw/mcu/stm/stm32f4xx/syscfg.yml b/hw/mcu/stm/stm32f4xx/syscfg.yml
index 0c92552..e9db83f 100644
--- a/hw/mcu/stm/stm32f4xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f4xx/syscfg.yml
@@ -16,7 +16,7 @@
# under the License.
#
-# Package: hw/mcu/stm32f4xx
+# Package: hw/mcu/stm/stm32f4xx
syscfg.defs:
MCU_FLASH_MIN_WRITE_SIZE:
@@ -29,6 +29,18 @@ syscfg.defs:
description: MCUs are of STM32F4xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI without FIFO
+ value: 0
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has a clock speed register
+ value: 1
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses SR register for status.
+ value: 1
+
I2C_0:
description: 'I2C (TWI) interface 0'
value: 0
diff --git a/hw/mcu/stm/stm32f7xx/syscfg.yml b/hw/mcu/stm/stm32f7xx/syscfg.yml
index d671e4b..dea2cb1 100644
--- a/hw/mcu/stm/stm32f7xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f7xx/syscfg.yml
@@ -16,6 +16,8 @@
# under the License.
#
+# Package: hw/mcu/stm/stm32f7xx
+
syscfg.defs:
MCU_FLASH_MIN_WRITE_SIZE:
description: >
@@ -27,6 +29,18 @@ syscfg.defs:
description: MCUs are of STM32F7xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI with FIFO
+ value: 1
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has no clock speed register (has TIMINGR)
+ value: 0
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses ISR register (not SR) for status.
+ value: 0
+
MCU_SYSCLK_PLL_HSI:
description: Configure PLL as sysclock driven by HSI.
value: 0
diff --git a/hw/mcu/stm/stm32l1xx/syscfg.yml b/hw/mcu/stm/stm32l1xx/syscfg.yml
index f3d02ec..fcdbb26 100644
--- a/hw/mcu/stm/stm32l1xx/syscfg.yml
+++ b/hw/mcu/stm/stm32l1xx/syscfg.yml
@@ -16,7 +16,7 @@
# under the License.
#
-# Package: hw/bsp/stm32l152discovery
+# Package: hw/mcu/stm/stm32l1xx
syscfg.defs:
I2C_0:
@@ -33,6 +33,18 @@ syscfg.defs:
description: MCUs are of STM32L1xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI without FIFO
+ value: 0
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has a clock speed register
+ value: 1
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses SR register for status.
+ value: 1
+
SPI_0_MASTER:
description: 'SPI 0 master'
value: 0
diff --git a/hw/mcu/stm/stm32l4xx/syscfg.yml b/hw/mcu/stm/stm32l4xx/syscfg.yml
index 1f34d29..3cf2419 100644
--- a/hw/mcu/stm/stm32l4xx/syscfg.yml
+++ b/hw/mcu/stm/stm32l4xx/syscfg.yml
@@ -16,7 +16,7 @@
# under the License.
#
-# Package: hw/mcu/stm32l4xx
+# Package: hw/mcu/stm/stm32l4xx
syscfg.defs:
I2C_0:
@@ -33,6 +33,18 @@ syscfg.defs:
description: MCUs are of STM32L4xx family
value: 1
+ STM32_HAL_SPI_HAS_FIFO:
+ description: This MCU has a SPI with FIFO
+ value: 1
+
+ STM32_HAL_I2C_HAS_CLOCKSPEED:
+ description: This MCU's I2C has no clock speed register (has TIMINGR)
+ value: 0
+
+ STM32_HAL_UART_HAS_SR:
+ description: This MCU's UART uses ISR register (not SR) for status.
+ value: 0
+
SPI_0_MASTER:
description: 'SPI 0 master'
value: 0
[mynewt-core] 02/02: Fix identation
Posted by ut...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 3b1657692ac0843364cdd9a136988ec7788dc73e
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Wed Jul 18 12:54:17 2018 -0300
Fix identation
---
hw/mcu/stm/stm32_common/src/hal_gpio.c | 72 +++++++++++++++++-----------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c b/hw/mcu/stm/stm32_common/src/hal_gpio.c
index 20763ec..cabead9 100644
--- a/hw/mcu/stm/stm32_common/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c
@@ -274,63 +274,63 @@ hal_gpio_clk_enable(uint32_t port_idx)
{
switch (port_idx) {
#if defined GPIOA_BASE
- case 0:
- __HAL_RCC_GPIOA_CLK_ENABLE();
- break;
+ case 0:
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ break;
#endif
#if defined GPIOB_BASE
- case 1:
- __HAL_RCC_GPIOB_CLK_ENABLE();
- break;
+ case 1:
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ break;
#endif
#if defined GPIOC_BASE
- case 2:
- __HAL_RCC_GPIOC_CLK_ENABLE();
- break;
+ case 2:
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ break;
#endif
#if defined GPIOD_BASE
- case 3:
- __HAL_RCC_GPIOD_CLK_ENABLE();
- break;
+ case 3:
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ break;
#endif
#if defined GPIOE_BASE
- case 4:
- __HAL_RCC_GPIOE_CLK_ENABLE();
- break;
+ case 4:
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ break;
#endif
#if defined GPIOF_BASE
- case 5:
- __HAL_RCC_GPIOF_CLK_ENABLE();
- break;
+ case 5:
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ break;
#endif
#if defined GPIOG_BASE
- case 6:
- __HAL_RCC_GPIOG_CLK_ENABLE();
- break;
+ case 6:
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ break;
#endif
#if defined GPIOH_BASE
- case 7:
- __HAL_RCC_GPIOH_CLK_ENABLE();
- break;
+ case 7:
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ break;
#endif
#if defined GPIOI_BASE
- case 8:
- __HAL_RCC_GPIOI_CLK_ENABLE();
- break;
+ case 8:
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+ break;
#endif
#if defined GPIOJ_BASE
- case 9:
- __HAL_RCC_GPIOJ_CLK_ENABLE();
- break;
+ case 9:
+ __HAL_RCC_GPIOJ_CLK_ENABLE();
+ break;
#endif
#if defined GPIOK_BASE
- case 10:
- __HAL_RCC_GPIOK_CLK_ENABLE();
- break;
+ case 10:
+ __HAL_RCC_GPIOK_CLK_ENABLE();
+ break;
#endif
- default:
- assert(0);
- break;
+ default:
+ assert(0);
+ break;
}
}