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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/04/12 20:35:12 UTC
[incubator-nuttx] branch master updated: arch/arm: Move FPU initialization to common place
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new df5a8a53ae arch/arm: Move FPU initialization to common place
df5a8a53ae is described below
commit df5a8a53ae92606e2d65149c6b5159b82dfc5d76
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Tue Apr 12 03:18:46 2022 +0800
arch/arm: Move FPU initialization to common place
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/arm/src/a1x/a1x_boot.c | 3 -
arch/arm/src/am335x/am335x_boot.c | 3 -
arch/arm/src/armv7-a/fpu.h | 77 ------------------
arch/arm/src/armv7-m/arm_fpuconfig.c | 117 ++++++++++++++++++++++++++++
arch/arm/src/armv7-r/fpu.h | 77 ------------------
arch/arm/src/armv8-m/arm_fpuconfig.c | 117 ++++++++++++++++++++++++++++
arch/arm/src/common/arm_internal.h | 2 +
arch/arm/src/cxd56xx/Make.defs | 1 +
arch/arm/src/cxd56xx/cxd56_cpustart.c | 3 +-
arch/arm/src/cxd56xx/cxd56_start.c | 93 +---------------------
arch/arm/src/efm32/Make.defs | 1 +
arch/arm/src/efm32/efm32_start.c | 100 +-----------------------
arch/arm/src/eoss3/Make.defs | 4 +
arch/arm/src/eoss3/eoss3_start.c | 104 +------------------------
arch/arm/src/imx6/imx_boot.c | 3 -
arch/arm/src/imx6/imx_cpuboot.c | 3 -
arch/arm/src/imxrt/Make.defs | 1 +
arch/arm/src/imxrt/imxrt_start.c | 102 +-----------------------
arch/arm/src/kinetis/Make.defs | 1 +
arch/arm/src/kinetis/kinetis_start.c | 100 +-----------------------
arch/arm/src/lpc17xx_40xx/Make.defs | 1 +
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c | 92 +---------------------
arch/arm/src/lpc43xx/Make.defs | 1 +
arch/arm/src/lpc43xx/lpc43_start.c | 95 +---------------------
arch/arm/src/lpc54xx/Make.defs | 1 +
arch/arm/src/lpc54xx/lpc54_start.c | 93 +---------------------
arch/arm/src/max326xx/Make.defs | 1 +
arch/arm/src/max326xx/common/max326_start.c | 93 +---------------------
arch/arm/src/nrf52/Make.defs | 1 +
arch/arm/src/nrf52/nrf52_start.c | 89 +--------------------
arch/arm/src/s32k1xx/Make.defs | 4 +
arch/arm/src/s32k1xx/s32k1xx_start.c | 89 +--------------------
arch/arm/src/sam34/Make.defs | 1 +
arch/arm/src/sam34/sam_start.c | 96 +----------------------
arch/arm/src/sama5/sam_boot.c | 3 -
arch/arm/src/samd5e5/Make.defs | 1 +
arch/arm/src/samd5e5/sam_start.c | 92 +---------------------
arch/arm/src/samv7/Make.defs | 1 +
arch/arm/src/samv7/sam_start.c | 100 +-----------------------
arch/arm/src/stm32/Make.defs | 1 +
arch/arm/src/stm32/stm32_start.c | 100 +-----------------------
arch/arm/src/stm32f7/Make.defs | 1 +
arch/arm/src/stm32f7/stm32_start.c | 100 +-----------------------
arch/arm/src/stm32h7/Make.defs | 2 +
arch/arm/src/stm32h7/stm32_start.c | 96 +----------------------
arch/arm/src/stm32l4/Make.defs | 1 +
arch/arm/src/stm32l4/stm32l4_start.c | 100 +-----------------------
arch/arm/src/stm32l5/Make.defs | 1 +
arch/arm/src/stm32l5/stm32l5_start.c | 101 +-----------------------
arch/arm/src/stm32u5/Make.defs | 1 +
arch/arm/src/stm32u5/stm32_start.c | 101 +-----------------------
arch/arm/src/tiva/Make.defs | 1 +
arch/arm/src/tiva/cc13xx/cc13xx_start.c | 93 +---------------------
arch/arm/src/tiva/common/lmxx_tm4c_start.c | 93 +---------------------
arch/arm/src/tms570/tms570_boot.c | 3 -
arch/arm/src/xmc4/Make.defs | 1 +
arch/arm/src/xmc4/xmc4_start.c | 96 +----------------------
57 files changed, 290 insertions(+), 2368 deletions(-)
diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c
index d6effb2173..ba475afb34 100644
--- a/arch/arm/src/a1x/a1x_boot.c
+++ b/arch/arm/src/a1x/a1x_boot.c
@@ -34,7 +34,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
-#include "fpu.h"
#include "arm_internal.h"
#include "a1x_lowputc.h"
#include "a1x_boot.h"
@@ -300,11 +299,9 @@ void arm_boot(void)
a1x_copyvectorblock();
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
-#endif
#ifdef CONFIG_BOOT_SDRAM_DATA
/* This setting is inappropriate for the A1x because the code is *always*
diff --git a/arch/arm/src/am335x/am335x_boot.c b/arch/arm/src/am335x/am335x_boot.c
index 43223174a8..4a203fd27a 100644
--- a/arch/arm/src/am335x/am335x_boot.c
+++ b/arch/arm/src/am335x/am335x_boot.c
@@ -38,7 +38,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
-#include "fpu.h"
#include "arm_internal.h"
#include "am335x_clockconfig.h"
#include "am335x_wdog.h"
@@ -402,11 +401,9 @@ void arm_boot(void)
am335x_clockconfig();
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
-#endif
/* Disable CPU Watchdog */
diff --git a/arch/arm/src/armv7-a/fpu.h b/arch/arm/src/armv7-a/fpu.h
deleted file mode 100644
index 134cce9680..0000000000
--- a/arch/arm/src/armv7-a/fpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/fpu.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_ARMV7_A_FPU_H
-#define __ARCH_ARM_SRC_ARMV7_A_FPU_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: arm_fpuconfig
- *
- * Description:
- * Configure the FPU. Enables access to CP10 and CP11
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-void arm_fpuconfig(void);
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_ARM_SRC_ARMV7_A_FPU_H */
diff --git a/arch/arm/src/armv7-m/arm_fpuconfig.c b/arch/arm/src/armv7-m/arm_fpuconfig.c
new file mode 100644
index 0000000000..df676ee482
--- /dev/null
+++ b/arch/arm/src/armv7-m/arm_fpuconfig.c
@@ -0,0 +1,117 @@
+/****************************************************************************
+ * arch/arm/src/armv7-m/arm_fpuconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "nvic.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_fpuconfig
+ *
+ * Description:
+ * Configure the FPU. Relative bit settings:
+ *
+ * CPACR: Enables access to CP10 and CP11
+ * CONTROL.FPCA: Determines whether the FP extension is active in the
+ * current context:
+ * FPCCR.ASPEN: Enables automatic FP state preservation, then the
+ * processor sets this bit to 1 on successful completion of any FP
+ * instruction.
+ * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
+ * done, the processor reserves space on the stack for the FP state,
+ * but does not save that state information to the stack.
+ *
+ * Software must not change the value of the ASPEN bit or LSPEN bit while
+ * either:
+ *
+ * - the CPACR permits access to CP10 and CP11, that give access to the FP
+ * extension, or
+ * - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARMV7M_LAZYFPU
+
+void arm_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Set CONTROL.FPCA so that we always get the extended context frame
+ * with the volatile FP registers stacked above the basic context.
+ */
+
+ regval = getcontrol();
+ regval |= CONTROL_FPCA;
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
+ * are going to turn on CONTROL.FPCA for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
+ putreg32(regval, NVIC_CPACR);
+}
+
+#else
+
+void arm_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Clear CONTROL.FPCA so that we do not get the extended context frame
+ * with the volatile FP registers stacked in the saved context.
+ */
+
+ regval = getcontrol();
+ regval &= ~CONTROL_FPCA;
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
+ * are going to keep CONTROL.FPCA off for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
+ putreg32(regval, NVIC_CPACR);
+}
+
+#endif
diff --git a/arch/arm/src/armv7-r/fpu.h b/arch/arm/src/armv7-r/fpu.h
deleted file mode 100644
index a89380a9d2..0000000000
--- a/arch/arm/src/armv7-r/fpu.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/fpu.h
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_ARMV7_R_FPU_H
-#define __ARCH_ARM_SRC_ARMV7_R_FPU_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Name: arm_fpuconfig
- *
- * Description:
- * Configure the FPU. Enables access to CP10 and CP11
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-void arm_fpuconfig(void);
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_ARM_SRC_ARMV7_R_FPU_H */
diff --git a/arch/arm/src/armv8-m/arm_fpuconfig.c b/arch/arm/src/armv8-m/arm_fpuconfig.c
new file mode 100644
index 0000000000..f81ada6f51
--- /dev/null
+++ b/arch/arm/src/armv8-m/arm_fpuconfig.c
@@ -0,0 +1,117 @@
+/****************************************************************************
+ * arch/arm/src/armv8-m/arm_fpuconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "nvic.h"
+#include "arm_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_fpuconfig
+ *
+ * Description:
+ * Configure the FPU. Relative bit settings:
+ *
+ * CPACR: Enables access to CP10 and CP11
+ * CONTROL.FPCA: Determines whether the FP extension is active in the
+ * current context:
+ * FPCCR.ASPEN: Enables automatic FP state preservation, then the
+ * processor sets this bit to 1 on successful completion of any FP
+ * instruction.
+ * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
+ * done, the processor reserves space on the stack for the FP state,
+ * but does not save that state information to the stack.
+ *
+ * Software must not change the value of the ASPEN bit or LSPEN bit while
+ * either:
+ *
+ * - the CPACR permits access to CP10 and CP11, that give access to the FP
+ * extension, or
+ * - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARMV8M_LAZYFPU
+
+void arm_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Set CONTROL.FPCA so that we always get the extended context frame
+ * with the volatile FP registers stacked above the basic context.
+ */
+
+ regval = getcontrol();
+ regval |= CONTROL_FPCA;
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
+ * are going to turn on CONTROL.FPCA for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
+ putreg32(regval, NVIC_CPACR);
+}
+
+#else
+
+void arm_fpuconfig(void)
+{
+ uint32_t regval;
+
+ /* Clear CONTROL.FPCA so that we do not get the extended context frame
+ * with the volatile FP registers stacked in the saved context.
+ */
+
+ regval = getcontrol();
+ regval &= ~CONTROL_FPCA;
+ setcontrol(regval);
+
+ /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+ * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
+ * are going to keep CONTROL.FPCA off for all contexts.
+ */
+
+ regval = getreg32(NVIC_FPCCR);
+ regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
+ putreg32(regval, NVIC_FPCCR);
+
+ /* Enable full access to CP10 and CP11 */
+
+ regval = getreg32(NVIC_CPACR);
+ regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
+ putreg32(regval, NVIC_CPACR);
+}
+
+#endif
diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h
index b78707f32a..f0e867a677 100644
--- a/arch/arm/src/common/arm_internal.h
+++ b/arch/arm/src/common/arm_internal.h
@@ -440,9 +440,11 @@ void arm_vectorfiq(void);
/* Floating point unit ******************************************************/
#ifdef CONFIG_ARCH_FPU
+void arm_fpuconfig(void);
void arm_savefpu(uint32_t *regs);
void arm_restorefpu(const uint32_t *regs);
#else
+# define arm_fpuconfig()
# define arm_savefpu(regs)
# define arm_restorefpu(regs)
#endif
diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs
index 2a02b16475..629abecfa5 100644
--- a/arch/arm/src/cxd56xx/Make.defs
+++ b/arch/arm/src/cxd56xx/Make.defs
@@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
diff --git a/arch/arm/src/cxd56xx/cxd56_cpustart.c b/arch/arm/src/cxd56xx/cxd56_cpustart.c
index 6c0bf94aa9..649ba67caa 100644
--- a/arch/arm/src/cxd56xx/cxd56_cpustart.c
+++ b/arch/arm/src/cxd56xx/cxd56_cpustart.c
@@ -73,7 +73,6 @@
volatile static spinlock_t g_appdsp_boot;
extern int arm_pause_handler(int irq, void *c, FAR void *arg);
-extern void fpuconfig(void);
/****************************************************************************
* Private Functions
@@ -104,7 +103,7 @@ static void appdsp_boot(void)
/* Setup FPU */
- fpuconfig();
+ arm_fpuconfig();
/* Clear SW_INT for APP_DSP(cpu) */
diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c
index 2794f96045..b20564aa85 100644
--- a/arch/arm/src/cxd56xx/cxd56_start.c
+++ b/arch/arm/src/cxd56xx/cxd56_start.c
@@ -110,97 +110,6 @@ extern uint32_t _vectors[];
* Public Functions
****************************************************************************/
-/****************************************************************************
- * Name: fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-# ifndef CONFIG_ARMV7M_LAZYFPU
-
-void fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-# else
-
-void fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-# endif
-
-#else
-# define fpuconfig()
-#endif
-
/****************************************************************************
* Name: _start
*
@@ -269,7 +178,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- fpuconfig();
+ arm_fpuconfig();
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */
diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs
index a2fd4d6f2d..03d70d30ca 100644
--- a/arch/arm/src/efm32/Make.defs
+++ b/arch/arm/src/efm32/Make.defs
@@ -58,6 +58,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index 14d47ef566..77f71837d2 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -70,14 +70,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void efm32_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -102,96 +94,6 @@ static inline void efm32_fpuconfig(void);
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: efm32_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void efm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void efm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define efm32_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -212,7 +114,7 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
efm32_clockconfig();
- efm32_fpuconfig();
+ arm_fpuconfig();
efm32_lowsetup();
showprogress('A');
diff --git a/arch/arm/src/eoss3/Make.defs b/arch/arm/src/eoss3/Make.defs
index 7180d15510..b84a63a547 100644
--- a/arch/arm/src/eoss3/Make.defs
+++ b/arch/arm/src/eoss3/Make.defs
@@ -56,6 +56,10 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_CSRCS += arm_fpuconfig.c
+endif
+
CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
CHIP_CSRCS += eoss3_irq.c
CHIP_CSRCS += eoss3_serial.c
diff --git a/arch/arm/src/eoss3/eoss3_start.c b/arch/arm/src/eoss3/eoss3_start.c
index 81511e0215..f9634e33d1 100644
--- a/arch/arm/src/eoss3/eoss3_start.c
+++ b/arch/arm/src/eoss3/eoss3_start.c
@@ -64,14 +64,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void eoss3_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -100,97 +92,6 @@ static inline void eoss3_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: eoss3_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void eoss3_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void eoss3_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define eoss3_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -219,10 +120,7 @@ void __start(void)
eoss3_clockconfig();
- /* Unclear what needs to happen here to make RENODE happy. */
-#if 1
- eoss3_fpuconfig();
-#endif
+ arm_fpuconfig();
eoss3_lowsetup();
diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c
index 9b8d2ed9b6..9a2fc74d3a 100644
--- a/arch/arm/src/imx6/imx_boot.c
+++ b/arch/arm/src/imx6/imx_boot.c
@@ -39,7 +39,6 @@
#include "arm.h"
#include "mmu.h"
#include "scu.h"
-#include "fpu.h"
#include "arm_internal.h"
#include "imx_config.h"
#include "imx_clockconfig.h"
@@ -443,12 +442,10 @@ void arm_boot(void)
imx_clockconfig();
PROGRESS('I');
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
PROGRESS('J');
-#endif
/* Perform board-specific memory initialization, This must include
* initialization of board-specific memory resources (e.g., SDRAM)
diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c
index 85dbfb0617..cec8cff8ee 100644
--- a/arch/arm/src/imx6/imx_cpuboot.c
+++ b/arch/arm/src/imx6/imx_cpuboot.c
@@ -35,7 +35,6 @@
#include "sctlr.h"
#include "smp.h"
#include "scu.h"
-#include "fpu.h"
#include "gic.h"
#ifdef CONFIG_SMP
@@ -247,11 +246,9 @@ void arm_cpu_boot(int cpu)
arm_enable_smp(cpu);
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
-#endif
/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs
index bbd540b3c8..e2efb5adb0 100644
--- a/arch/arm/src/imxrt/Make.defs
+++ b/arch/arm/src/imxrt/Make.defs
@@ -72,6 +72,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
# Required i.MX RT files
diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c
index f462f694d4..346d8936b2 100644
--- a/arch/arm/src/imxrt/imxrt_start.c
+++ b/arch/arm/src/imxrt/imxrt_start.c
@@ -65,14 +65,6 @@
* here.
*/
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void imxrt_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -83,98 +75,6 @@ static inline void imxrt_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: imxrt_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- *
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void imxrt_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void imxrt_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define imxrt_fpuconfig()
-#endif
-
/****************************************************************************
* Name: imxrt_tcmenable
*
@@ -286,7 +186,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
imxrt_clockconfig();
- imxrt_fpuconfig();
+ arm_fpuconfig();
imxrt_lowsetup();
/* Enable/disable tightly coupled memories */
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index fe85131936..55172b856c 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -76,6 +76,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index 62dbc08aa9..8d0cadd9b4 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -40,14 +40,6 @@
#include "kinetis_start.h"
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void kinetis_fpuconfig(void);
-#endif
-
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -96,96 +88,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: kinetis_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void kinetis_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void kinetis_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define kinetis_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -258,7 +160,7 @@ void __start(void)
* configuration).
*/
- kinetis_fpuconfig();
+ arm_fpuconfig();
kinetis_lowsetup();
#ifdef USE_EARLYSERIALINIT
kinetis_earlyserialinit();
diff --git a/arch/arm/src/lpc17xx_40xx/Make.defs b/arch/arm/src/lpc17xx_40xx/Make.defs
index 016a281549..1e680a1b0b 100644
--- a/arch/arm/src/lpc17xx_40xx/Make.defs
+++ b/arch/arm/src/lpc17xx_40xx/Make.defs
@@ -74,6 +74,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
# Required LPC17xx files
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
index 7983ae65d9..0edc1eaf26 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
@@ -86,96 +86,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: lpc17_40_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void lpc17_40_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void lpc17_40_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define lpc17_40_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -213,7 +123,7 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
lpc17_40_clockconfig();
- lpc17_40_fpuconfig();
+ arm_fpuconfig();
lpc17_40_lowsetup();
showprogress('A');
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index b0e1700d1c..220feb5e0f 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c
index c59e336444..4fbe63e511 100644
--- a/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/arch/arm/src/lpc43xx/lpc43_start.c
@@ -83,7 +83,7 @@
#endif
/****************************************************************************
- * Public Functions
+ * Private Functions
****************************************************************************/
/****************************************************************************
@@ -153,97 +153,6 @@ static inline void lpc43_enabuffering(void)
# define lpc43_enabuffering()
#endif
-/****************************************************************************
- * Name: lpc43_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void lpc43_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void lpc43_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define lpc43_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -316,7 +225,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- lpc43_fpuconfig();
+ arm_fpuconfig();
showprogress('D');
/* Perform early serial initialization */
diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs
index 12c3524c12..41f2299fda 100644
--- a/arch/arm/src/lpc54xx/Make.defs
+++ b/arch/arm/src/lpc54xx/Make.defs
@@ -62,6 +62,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
diff --git a/arch/arm/src/lpc54xx/lpc54_start.c b/arch/arm/src/lpc54xx/lpc54_start.c
index 09d55239bb..14c0d80f1c 100644
--- a/arch/arm/src/lpc54xx/lpc54_start.c
+++ b/arch/arm/src/lpc54xx/lpc54_start.c
@@ -80,97 +80,6 @@ static const struct pll_setup_s g_initial_pll_setup =
.ahbdiv = SYSCON_AHBCLKDIV_DIV(BOARD_AHBCLKDIV)
};
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: lpc54_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-static inline void lpc54_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#else
-static inline void lpc54_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#endif
-
-#else
-# define lpc54_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -234,7 +143,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- lpc54_fpuconfig();
+ arm_fpuconfig();
showprogress('D');
/* Perform early serial initialization */
diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs
index fd28fa9c2f..3a6d376126 100644
--- a/arch/arm/src/max326xx/Make.defs
+++ b/arch/arm/src/max326xx/Make.defs
@@ -60,6 +60,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
# Common MAX326XX Source Files
diff --git a/arch/arm/src/max326xx/common/max326_start.c b/arch/arm/src/max326xx/common/max326_start.c
index cde8e28008..9d8d8192ac 100644
--- a/arch/arm/src/max326xx/common/max326_start.c
+++ b/arch/arm/src/max326xx/common/max326_start.c
@@ -80,97 +80,6 @@
const uintptr_t g_idle_topstack = IDLE_STACK;
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: max326_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-static inline void max326_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#else
-static inline void max326_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#endif
-
-#else
-# define max326_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -239,7 +148,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- max326_fpuconfig();
+ arm_fpuconfig();
showprogress('E');
/* Perform early serial initialization */
diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs
index 1d939131d6..c7f225fb9b 100644
--- a/arch/arm/src/nrf52/Make.defs
+++ b/arch/arm/src/nrf52/Make.defs
@@ -70,6 +70,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c
diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c
index 8553696474..397be68eb5 100644
--- a/arch/arm/src/nrf52/nrf52_start.c
+++ b/arch/arm/src/nrf52/nrf52_start.c
@@ -71,93 +71,6 @@
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: nrf52_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-static inline void nrf52_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#else
-static inline void nrf52_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#endif
-
-#else
-# define nrf52_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -227,7 +140,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- nrf52_fpuconfig();
+ arm_fpuconfig();
#ifdef CONFIG_NRF52_FLASH_PREFETCH
nrf_nvmc_enable_icache(true);
diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs
index 090b87f2ef..555f948a3d 100644
--- a/arch/arm/src/s32k1xx/Make.defs
+++ b/arch/arm/src/s32k1xx/Make.defs
@@ -38,6 +38,10 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_pthread_start.c
endif
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_CSRCS += arm_fpuconfig.c
+endif
+
# Source files common to all S32K1xx chip families.
CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c
index 34e241f668..85cd09d323 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.c
@@ -124,93 +124,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Functions
****************************************************************************/
-/****************************************************************************
- * Name: s32k1xx_fpu_config
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-static inline void s32k1xx_fpu_config(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#else
-static inline void s32k1xx_fpu_config(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-#endif
-
-#else
-# define s32k1xx_fpu_config()
-#endif
-
/****************************************************************************
* Name: s32k1xx_cache_config
*
@@ -339,7 +252,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- s32k1xx_fpu_config();
+ arm_fpuconfig();
showprogress('C');
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index e7abde8723..2cbeb3b579 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -66,6 +66,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index c264328e49..76c037a38a 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -71,10 +71,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Function prototypes
****************************************************************************/
-#ifdef CONFIG_ARCH_FPU
-static inline void sam_fpuconfig(void);
-#endif
-
#ifdef CONFIG_ARMV7M_STACKCHECK
/* We need to get r10 set before we can allow instrumentation calls */
@@ -99,96 +95,6 @@ void __start(void) noinstrument_function;
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: sam_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void sam_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void sam_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define sam_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -257,7 +163,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
sam_clockconfig();
- sam_fpuconfig();
+ arm_fpuconfig();
sam_lowsetup();
showprogress('A');
diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c
index d01e7857ab..42951b75f6 100644
--- a/arch/arm/src/sama5/sam_boot.c
+++ b/arch/arm/src/sama5/sam_boot.c
@@ -38,7 +38,6 @@
#include "chip.h"
#include "arm.h"
#include "mmu.h"
-#include "fpu.h"
#include "arm_internal.h"
#include "hardware/sam_wdt.h"
#include "hardware/sam_aximx.h"
@@ -445,11 +444,9 @@ void arm_boot(void)
sam_clockconfig();
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
-#endif
/* Perform board-specific initialization, This must include:
*
diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs
index 8cf43c9612..d224240307 100644
--- a/arch/arm/src/samd5e5/Make.defs
+++ b/arch/arm/src/samd5e5/Make.defs
@@ -56,6 +56,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c
index f2814f6fab..fbe5aac4e2 100644
--- a/arch/arm/src/samd5e5/sam_start.c
+++ b/arch/arm/src/samd5e5/sam_start.c
@@ -101,96 +101,6 @@ void __start(void) noinstrument_function;
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: sam_fpu_configure
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void sam_fpu_configure(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void sam_fpu_configure(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define sam_fpu_configure()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -258,7 +168,7 @@ void __start(void)
*/
sam_clock_initialize();
- sam_fpu_configure();
+ arm_fpuconfig();
sam_lowsetup();
showprogress('A');
diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs
index a3ada0692c..7ff7c5084d 100644
--- a/arch/arm/src/samv7/Make.defs
+++ b/arch/arm/src/samv7/Make.defs
@@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c
index b22b2b8cff..221b117db8 100644
--- a/arch/arm/src/samv7/sam_start.c
+++ b/arch/arm/src/samv7/sam_start.c
@@ -78,14 +78,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void sam_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -96,96 +88,6 @@ static inline void sam_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: sam_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void sam_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void sam_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define sam_fpuconfig()
-#endif
-
/****************************************************************************
* Name: sam_tcmenable
*
@@ -296,7 +198,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
sam_clockconfig();
- sam_fpuconfig();
+ arm_fpuconfig();
sam_gpioinit();
sam_lowsetup();
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index ee8a4eac48..6b73ca5a58 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -70,6 +70,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 7e0b52543a..a49f84af24 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -67,14 +67,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -103,96 +95,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -224,7 +126,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
- stm32_fpuconfig();
+ arm_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 21d694fdfd..80ccb1d381 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -61,6 +61,7 @@ CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c
index 159e2d2eca..f52fd3ea6f 100644
--- a/arch/arm/src/stm32f7/stm32_start.c
+++ b/arch/arm/src/stm32f7/stm32_start.c
@@ -79,14 +79,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -97,96 +89,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32_fpuconfig()
-#endif
-
/****************************************************************************
* Name: stm32_tcmenable
*
@@ -302,7 +204,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
- stm32_fpuconfig();
+ arm_fpuconfig();
stm32_lowsetup();
/* Enable/disable tightly coupled memories */
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index daa9d21734..48b601c932 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -58,8 +58,10 @@ endif
CMN_CSRCS += arm_vectors.c
CMN_CSRCS += arm_cache.c
+
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index a8732f7eda..b945294473 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -84,10 +84,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Function prototypes
****************************************************************************/
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32_fpuconfig(void);
-#endif
-
/****************************************************************************
* Name: showprogress
*
@@ -112,96 +108,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32_fpuconfig()
-#endif
-
/****************************************************************************
* Name: stm32_tcmenable
*
@@ -317,7 +223,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
- stm32_fpuconfig();
+ arm_fpuconfig();
stm32_lowsetup();
showprogress('A');
diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs
index 506ff2b1b9..f9d97f4e44 100644
--- a/arch/arm/src/stm32l4/Make.defs
+++ b/arch/arm/src/stm32l4/Make.defs
@@ -55,6 +55,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c
index 400844ae8a..7a2eb391bb 100644
--- a/arch/arm/src/stm32l4/stm32l4_start.c
+++ b/arch/arm/src/stm32l4/stm32l4_start.c
@@ -75,14 +75,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32l4_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -111,96 +103,6 @@ static inline void stm32l4_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32l4_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void stm32l4_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32l4_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32l4_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -246,7 +148,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32l4_clockconfig();
- stm32l4_fpuconfig();
+ arm_fpuconfig();
stm32l4_lowsetup();
stm32l4_gpioinit();
showprogress('A');
diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs
index 63dd3b203f..6cc506f49c 100644
--- a/arch/arm/src/stm32l5/Make.defs
+++ b/arch/arm/src/stm32l5/Make.defs
@@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c
index 28d55790bb..c672b65b53 100644
--- a/arch/arm/src/stm32l5/stm32l5_start.c
+++ b/arch/arm/src/stm32l5/stm32l5_start.c
@@ -77,14 +77,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32l5_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -113,97 +105,6 @@ static inline void stm32l5_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32l5_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV8M_LAZYFPU
-
-static inline void stm32l5_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32l5_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32l5_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -249,7 +150,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32l5_clockconfig();
- stm32l5_fpuconfig();
+ arm_fpuconfig();
stm32l5_lowsetup();
stm32l5_gpioinit();
showprogress('A');
diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs
index 27fee60065..dc64268e0c 100644
--- a/arch/arm/src/stm32u5/Make.defs
+++ b/arch/arm/src/stm32u5/Make.defs
@@ -60,6 +60,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/stm32u5/stm32_start.c b/arch/arm/src/stm32u5/stm32_start.c
index 3a91c9e467..e230c91f81 100644
--- a/arch/arm/src/stm32u5/stm32_start.c
+++ b/arch/arm/src/stm32u5/stm32_start.c
@@ -77,14 +77,6 @@
const uintptr_t g_idle_topstack = HEAP_BASE;
-/****************************************************************************
- * Private Function prototypes
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-static inline void stm32_fpuconfig(void);
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -113,97 +105,6 @@ static inline void stm32_fpuconfig(void);
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: stm32_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV8M_LAZYFPU
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void stm32_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define stm32_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -249,7 +150,7 @@ void __start(void)
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
- stm32_fpuconfig();
+ arm_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index 9d6e2c5d65..a659f10e93 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -49,6 +49,7 @@ CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+ CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_start.c b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
index f077e90693..7770af4180 100644
--- a/arch/arm/src/tiva/cc13xx/cc13xx_start.c
+++ b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
@@ -96,97 +96,6 @@ void cc13xx_trim_device(void);
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: tiva_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void tiva_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void tiva_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define tiva_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -231,7 +140,7 @@ void __start(void)
*/
tiva_lowsetup();
- tiva_fpuconfig();
+ arm_fpuconfig();
showprogress('A');
#ifdef CONFIG_BOOT_RUNFROMFLASH
diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_start.c b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
index 716856ee6c..aa3730e78b 100644
--- a/arch/arm/src/tiva/common/lmxx_tm4c_start.c
+++ b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
@@ -87,97 +87,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
# define showprogress(c)
#endif
-/****************************************************************************
- * Name: tiva_fpuconfig
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void tiva_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void tiva_fpuconfig(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behavior. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define tiva_fpuconfig()
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -201,7 +110,7 @@ void __start(void)
tiva_clock_configure();
tiva_lowsetup();
- tiva_fpuconfig();
+ arm_fpuconfig();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c
index c9e7958b37..dfdadd8dd7 100644
--- a/arch/arm/src/tms570/tms570_boot.c
+++ b/arch/arm/src/tms570/tms570_boot.c
@@ -54,7 +54,6 @@
#include "chip.h"
#include "arm.h"
-#include "fpu.h"
#include "sctlr.h"
#include "arm_internal.h"
@@ -375,11 +374,9 @@ void arm_boot(void)
tms570_esm_initialize();
-#ifdef CONFIG_ARCH_FPU
/* Initialize the FPU */
arm_fpuconfig();
-#endif
#ifdef CONFIG_ARMV7R_MEMINIT
/* Initialize the .bss and .data sections as well as RAM functions
diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs
index 0fde410f5d..fc4b2c0340 100644
--- a/arch/arm/src/xmc4/Make.defs
+++ b/arch/arm/src/xmc4/Make.defs
@@ -75,6 +75,7 @@ endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
+CMN_CSRCS += arm_fpuconfig.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index 11d3968e75..d36870a842 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -44,9 +44,6 @@
* Private Function prototypes
****************************************************************************/
-#ifdef CONFIG_ARCH_FPU
-static inline void xmc4_fpu_config(void);
-#endif
static inline void xmc4_unaligned(void);
static inline void xmc4_flash_waitstates(void);
@@ -119,97 +116,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
void __start(void) noinstrument_function;
#endif
-/****************************************************************************
- * Name: xmc4_fpu_config
- *
- * Description:
- * Configure the FPU. Relative bit settings:
- *
- * CPACR: Enables access to CP10 and CP11
- * CONTROL.FPCA: Determines whether the FP extension is active in the
- * current context:
- * FPCCR.ASPEN: Enables automatic FP state preservation, then the
- * processor sets this bit to 1 on successful completion of any FP
- * instruction.
- * FPCCR.LSPEN: Enables lazy context save of FP state. When this is
- * done, the processor reserves space on the stack for the FP state,
- * but does not save that state information to the stack.
- *
- * Software must not change the value of the ASPEN bit or LSPEN bit while
- * either:
- * - the CPACR permits access to CP10 and CP11, that give access to the FP
- * extension, or
- * - the CONTROL.FPCA bit is set to 1
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ARCH_FPU
-#ifndef CONFIG_ARMV7M_LAZYFPU
-
-static inline void xmc4_fpu_config(void)
-{
- uint32_t regval;
-
- /* Set CONTROL.FPCA so that we always get the extended context frame
- * with the volatile FP registers stacked above the basic context.
- */
-
- regval = getcontrol();
- regval |= CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to turn on CONTROL.FPCA for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#else
-
-static inline void xmc4_fpu_config(void)
-{
- uint32_t regval;
-
- /* Clear CONTROL.FPCA so that we do not get the extended context frame
- * with the volatile FP registers stacked in the saved context.
- */
-
- regval = getcontrol();
- regval &= ~CONTROL_FPCA;
- setcontrol(regval);
-
- /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
- * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
- * are going to keep CONTROL.FPCA off for all contexts.
- */
-
- regval = getreg32(NVIC_FPCCR);
- regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
- putreg32(regval, NVIC_FPCCR);
-
- /* Enable full access to CP10 and CP11 */
-
- regval = getreg32(NVIC_CPACR);
- regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
- putreg32(regval, NVIC_CPACR);
-}
-
-#endif
-
-#else
-# define xmc4_fpu_config()
-#endif
-
/****************************************************************************
* Name: xmc4_unaligned
*
@@ -330,7 +236,7 @@ void __start(void)
/* Initialize the FPU (if configured) */
- xmc4_fpu_config();
+ arm_fpuconfig();
showprogress('B');
#ifdef USE_EARLYSERIALINIT