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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/05/07 08:02:06 UTC
[GitHub] [incubator-nuttx] hotislandn opened a new pull request, #6217: riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.
hotislandn opened a new pull request, #6217:
URL: https://github.com/apache/incubator-nuttx/pull/6217
## Summary
On RV64, when PMP entry >= 4, the current code generates unexpected instructions "sllw":
5300050c: 3a202773 csrr a4,pmpcfg2
PMP_MASK_SET_ONE_REGION(region, attr, cfg);
53000510: 8b9d andi a5,a5,7
53000512: 00379513 slli a0,a5,0x3
53000516: 0ff00793 li a5,255
5300051a: 00a797bb sllw a5,a5,a0
5300051e: fff7c793 not a5,a5
53000522: 2781 sext.w a5,a5
53000524: 8ff9 and a5,a5,a4
53000526: 00a59533 sll a0,a1,a0
5300052a: 8d5d or a0,a0,a5
WRITE_CSR(pmpcfg2, cfg);
5300052c: 3a251073 csrw pmpcfg2,a0
Which leads to the wrong PMPCFG settings: pmpcfg0[7:0] gets cleared when PMP entry=4.
## Impact
All RISC-V builds utilize the PMP.
## Testing
Verified.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6217: riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6217:
URL: https://github.com/apache/incubator-nuttx/pull/6217#discussion_r867344409
##########
arch/risc-v/src/common/riscv_pmp.c:
##########
@@ -58,7 +58,7 @@
#define BLOCK_ALIGN_MASK (MIN_BLOCK_SIZE - 1)
#define PMP_CFG_BITS_CNT (8)
-#define PMP_CFG_FLAG_MASK (0xFF)
+#define PMP_CFG_FLAG_MASK ((uintptr_t)0xFF)
Review Comment:
I think that change is fine, but maybe we can add `ul` or `l` instead of type cast? Just as an option
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[GitHub] [incubator-nuttx] gustavonihei commented on a diff in pull request #6217: riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.
Posted by GitBox <gi...@apache.org>.
gustavonihei commented on code in PR #6217:
URL: https://github.com/apache/incubator-nuttx/pull/6217#discussion_r867395025
##########
arch/risc-v/src/common/riscv_pmp.c:
##########
@@ -58,7 +58,7 @@
#define BLOCK_ALIGN_MASK (MIN_BLOCK_SIZE - 1)
#define PMP_CFG_BITS_CNT (8)
-#define PMP_CFG_FLAG_MASK (0xFF)
+#define PMP_CFG_FLAG_MASK ((uintptr_t)0xFF)
Review Comment:
Unfortunately we can't add these because this file applies for both RV32 and RV64.
One portable way to suffix constants is via the `INTxx_C` macros, but there isn't one for PTR type.
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[GitHub] [incubator-nuttx] pkarashchenko merged pull request #6217: riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.
Posted by GitBox <gi...@apache.org>.
pkarashchenko merged PR #6217:
URL: https://github.com/apache/incubator-nuttx/pull/6217
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[GitHub] [incubator-nuttx] hotislandn commented on pull request #6217: riscv/pmp: fix bug: PMP_CFG_FLAG_MASK makes pmp cfg fail.
Posted by GitBox <gi...@apache.org>.
hotislandn commented on PR #6217:
URL: https://github.com/apache/incubator-nuttx/pull/6217#issuecomment-1120161918
Code generation with this patch:
cfg = READ_CSR(pmpcfg0);
5300053c: 3a002773 csrr a4,pmpcfg0
PMP_MASK_SET_ONE_REGION(region, attr, cfg);
53000540: 0037951b slliw a0,a5,0x3
53000544: 0ff00793 li a5,255
53000548: 00a797b3 sll a5,a5,a0
5300054c: fff7c793 not a5,a5
53000550: 8ff9 and a5,a5,a4
53000552: 00a59533 sll a0,a1,a0
53000556: 8d5d or a0,a0,a5
WRITE_CSR(pmpcfg0, cfg);
53000558: 3a051073 csrw pmpcfg0,a0
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