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Posted to commits@nuttx.apache.org by ac...@apache.org on 2023/06/02 14:13:08 UTC
[nuttx] branch master updated (4c9e11d559 -> d193c50947)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from 4c9e11d559 tools: Support string upper/lower case in make
new 4d49f80e16 mpfs_corespi: Fix DEBUGASSERT() for clk divider
new d193c50947 mpfs_corespi: Change default motorola mode to MODE3
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Summary of changes:
arch/risc-v/src/mpfs/mpfs_corespi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[nuttx] 02/02: mpfs_corespi: Change default motorola mode to MODE3
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit d193c5094786bec6f16b0d29cab3ca1861caabd2
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Thu Jun 1 14:34:12 2023 +0300
mpfs_corespi: Change default motorola mode to MODE3
---
arch/risc-v/src/mpfs/mpfs_corespi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c
index da1b576a6c..43b1cacf3a 100644
--- a/arch/risc-v/src/mpfs/mpfs_corespi.c
+++ b/arch/risc-v/src/mpfs/mpfs_corespi.c
@@ -192,7 +192,7 @@ static void mpfs_spi_enable(struct mpfs_spi_priv_s *priv, uint8_t enable);
static const struct mpfs_spi_config_s mpfs_spi_config =
{
.clk_freq = MPFS_SPI_FREQ_DEFAULT,
- .mode = SPIDEV_MODE0,
+ .mode = SPIDEV_MODE3,
.nbits = 8,
.use_irq = true,
};
[nuttx] 01/02: mpfs_corespi: Fix DEBUGASSERT() for clk divider
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 4d49f80e16d98f3f1d2f0c246c72fe38a84dee3b
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Thu Jun 1 14:33:58 2023 +0300
mpfs_corespi: Fix DEBUGASSERT() for clk divider
Valid range is 0...255, not 2...512
---
arch/risc-v/src/mpfs/mpfs_corespi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c
index 1bf5cb0396..da1b576a6c 100644
--- a/arch/risc-v/src/mpfs/mpfs_corespi.c
+++ b/arch/risc-v/src/mpfs/mpfs_corespi.c
@@ -540,7 +540,7 @@ static uint32_t mpfs_spi_setfrequency(struct spi_dev_s *dev,
divider = ((MPFS_FPGA_PERIPHERAL_CLK / frequency) >> 1) - 1;
priv->actual = MPFS_FPGA_PERIPHERAL_CLK / ((divider + 1) << 1);
- DEBUGASSERT(divider >= 2u && divider <= 512u);
+ DEBUGASSERT(divider < 256u);
putreg32(divider, MPFS_SPI_CLK_GEN);