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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2021/02/20 18:35:35 UTC

[GitHub] [tvm] vegaluisjose commented on pull request #6126: [VTA][OpenCL] intelfocl

vegaluisjose commented on pull request #6126:
URL: https://github.com/apache/tvm/pull/6126#issuecomment-782729723


   If the instruction layout changed, then definitely the [ISA](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/ISA.scala) and [Decode](https://github.com/apache/tvm-vta/blob/main/hardware/chisel/src/main/scala/core/Decode.scala) module have to be updated accordingly.
   
   Chisel Bundles, used to decode the instructions, are pretty similar to the C-struct used in the vta-hardware-spec to define instructions. The WIDTHs for instruction field are defined in the ISA module.
   
   Hope it helps!


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